From: Jeff Law <jlaw@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: Re: [committed] RISC-V: XVentanaCondops support
Date: Wed, 26 Apr 2023 15:16:10 -0600 [thread overview]
Message-ID: <ddf70367-15a4-f500-4516-9a61c5db3aae@ventanamicro.com> (raw)
In-Reply-To: <mhng-8e6881c0-c319-4662-8fc5-70d65f26cb42@palmer-ri-x1c9>
On 4/26/23 15:09, Palmer Dabbelt wrote:
>>
>> The Veyron V1 processor implements XVentanaCondOps, but not Zicond.
>> That's simply due to timing.
>
> Do you have a link to anything that says this? I don't think we ever
> got a hard definition of what the requirements are, just some sort of
> annocement that the chip is going to be publicly availiable. There's
> some stuff on the Ventana website, but it's all sort of vague marketing
> type stuff.
The processor was announced back in December at the summit which I
thought was the requirement that you and Philipp had worked out.
We're still waiting on hardware for bring-up. But in terms of the
processor features/ISA, that's immutable at this point (as much as I
wish that weren't the case).
jeff
next prev parent reply other threads:[~2023-04-26 21:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 20:28 Jeff Law
2023-04-26 21:09 ` Palmer Dabbelt
2023-04-26 21:16 ` Jeff Law [this message]
2023-04-26 21:42 ` Palmer Dabbelt
2023-04-28 18:43 ` Jeff Law
2023-04-28 20:14 ` Palmer Dabbelt
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