From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 391A9385742C for ; Thu, 22 Sep 2022 06:32:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 391A9385742C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 90244300089; Thu, 22 Sep 2022 06:32:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1663828366; bh=kEc0geLW0ACSI5IcvENKEIfPy18fYnuQliLNZrlgu9s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=e3Su5ujxzSCIU0+UhwJY5qt0einLmI2tzXKk1cabMNDa3S4eyQD1ftrERf3DWcGNS wU5eqM/Sw2uhj4Lsuhgj9ee3r4jyE+yFuMlup4T0hgfC4SA0lY8exCEmO1vB4TR8xh 5uwzmo1WiqPA8eYXOeLqcEfmdgq5GqCBCbvJu2pI= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v3 1/2] RISC-V: Assign DWARF numbers to vector registers Date: Thu, 22 Sep 2022 06:32:33 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This commit is to comply RISC-V DWARF Specification version 1.0-rc4 (in the frozen state): https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4 binutils/ChangeLog: * dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers 96..127 to vector registers v0-v31. gas/ChangeLog: * config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support vector registers. --- binutils/dwarf.c | 28 ++++++++++++++++++---------- gas/config/tc-riscv.c | 3 +++ 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/binutils/dwarf.c b/binutils/dwarf.c index aef0f77eab6..c6340a28906 100644 --- a/binutils/dwarf.c +++ b/binutils/dwarf.c @@ -8540,16 +8540,24 @@ init_dwarf_regnames_s390 (void) static const char *const dwarf_regnames_riscv[] = { - "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", /* 0 - 7 */ - "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", /* 8 - 15 */ - "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", /* 16 - 23 */ - "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", /* 24 - 31 */ - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */ - "fs0", "fs1", /* 40 - 41 */ - "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */ - "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */ - "fs10", "fs11", /* 58 - 59 */ - "ft8", "ft9", "ft10", "ft11" /* 60 - 63 */ + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", /* 0 - 7 */ + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", /* 8 - 15 */ + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", /* 16 - 23 */ + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", /* 24 - 31 */ + "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */ + "fs0", "fs1", /* 40 - 41 */ + "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */ + "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */ + "fs10", "fs11", /* 58 - 59 */ + "ft8", "ft9", "ft10", "ft11", /* 60 - 63 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 64 - 71 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 72 - 79 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 80 - 87 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 88 - 95 */ + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", /* 96 - 103 */ + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", /* 104 - 111 */ + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", /* 112 - 119 */ + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", /* 120 - 127 */ }; /* A RISC-V replacement for REGNAME_INTERNAL_BY_TABLE_ONLY which handles diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 5411d68a401..bc36625311a 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -4319,6 +4319,9 @@ tc_riscv_regname_to_dw2regnum (char *regname) if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) return reg + 32; + if ((reg = reg_lookup_internal (regname, RCLASS_VECR)) >= 0) + return reg + 96; + /* CSRs are numbered 4096 -> 8191. */ if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0) return reg + 4096; -- 2.34.1