From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 6BC40384D183 for ; Thu, 20 Oct 2022 09:29:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6BC40384D183 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C21DB300089; Thu, 20 Oct 2022 09:29:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1666258175; bh=QWdii4iUfSav0OGT3OIIl+amP8T5LgLr7ez/z5okIAE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=H2ZjsTPCTnFvPSNWk6xPw4HpMfchg1oZKga8BqnIsGytrffdas0mS2DI4RzRBr6vD JwVZEhLdkFgedEzv6afL+F5a3qUul8e7cirsWMI8jXw0KJKWrxsAPoTGbBsnLVDEsH WVLecJqIt4WDuNdTZqlOdgUAbPt22sxbcXHTarWk= From: Tsukasa OI To: Tsukasa OI , Andrew Burgess , Mike Frysinger , Nick Clifton Cc: binutils@sourceware.org Subject: [PATCH 17/40] sim/lm32: Add explicit casts Date: Thu, 20 Oct 2022 09:26:03 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP,UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Clang generates a warning if there is an enum value with a mismatching type without an explicit cast ("-Wenum-conversion"). On the default configuration, it causes a build failure (unless "--disable-werror" is specified). This commit adds explicit casts on the LatticeMico32 instruction decoder. Note: This commit touches CGEN-generated files directly. Modifying CGEN is the best way to prevent this issue from happening again but there is another known regression in CGEN or sim/lm32 to resolve. --- sim/lm32/decode.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/sim/lm32/decode.c b/sim/lm32/decode.c index 9faef289132..889a0de9026 100644 --- a/sim/lm32/decode.c +++ b/sim/lm32/decode.c @@ -39,12 +39,12 @@ static IDESC lm32bf_insn_data[LM32BF_INSN__MAX]; static const struct insn_sem lm32bf_insn_sem[] = { - { VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY }, - { VIRTUAL_INSN_X_AFTER, LM32BF_INSN_X_AFTER, LM32BF_SFMT_EMPTY }, - { VIRTUAL_INSN_X_BEFORE, LM32BF_INSN_X_BEFORE, LM32BF_SFMT_EMPTY }, - { VIRTUAL_INSN_X_CTI_CHAIN, LM32BF_INSN_X_CTI_CHAIN, LM32BF_SFMT_EMPTY }, - { VIRTUAL_INSN_X_CHAIN, LM32BF_INSN_X_CHAIN, LM32BF_SFMT_EMPTY }, - { VIRTUAL_INSN_X_BEGIN, LM32BF_INSN_X_BEGIN, LM32BF_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, LM32BF_INSN_X_AFTER, LM32BF_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, LM32BF_INSN_X_BEFORE, LM32BF_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, LM32BF_INSN_X_CTI_CHAIN, LM32BF_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, LM32BF_INSN_X_CHAIN, LM32BF_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, LM32BF_INSN_X_BEGIN, LM32BF_SFMT_EMPTY }, { LM32_INSN_ADD, LM32BF_INSN_ADD, LM32BF_SFMT_ADD }, { LM32_INSN_ADDI, LM32BF_INSN_ADDI, LM32BF_SFMT_ADDI }, { LM32_INSN_AND, LM32BF_INSN_AND, LM32BF_SFMT_ADD }, @@ -111,7 +111,7 @@ static const struct insn_sem lm32bf_insn_sem[] = static const struct insn_sem lm32bf_insn_sem_invalid = { - VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY + (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY }; /* Initialize an IDESC from the compile-time computable parts. */ -- 2.34.1