Hi Jan,

On 2/12/2024 8:00 AM, Jan Beulich wrote:
> Srinath,
>
> may I ask against what specification these were written? There are many
> aspects I can't bring in line with what DDI0596 from December has, i.e.
> even newer than the patch (dating back to October), to a degree that I
> have to even question gas/NEWS stating (supposedly complete) support for
> the feature:
>
> 1) dupq uses encodings different from the doc, in part resulting in
>     supposedly reserved encodings (tsz=0).
>
> 2) extq uses syntax (operands) pretty different from what the doc says.
>
> 3) ld1q and st1q expect a plain first register operand, not one enclosed
>     in figure braces.
>
> 4) ld2q, ld3q, ld4q, st2q, st3q, and st4q don't permit a wrapping
>     sequence of vector registers, when the doc using "modulo" imo can't be
>     read any way other than meaning to permit that.
>
> 5) ld2q's scalar plus scalar encoding has bits 13 and 14 set, which is
>     inconsistent not only with the doc, but also with ld3q and ld4q.
>
> 6) ld3q/st3q and ld4q/st4q scalar plus immediate forms demand an immediate
>     that's a multiple of 2, when the doc says 3 and 4 respectively.

Thanks for the email and posting the issues with the sve2p1 
instructions. I have

checked the above mentioned instructions against the latest specs, the

documentation is correct and the issues are from the posted patches

(needs further tests as well). I will create a bugzilla (if it isn't 
created already)

ticket for all the mentioned instructions and work on fixing those issues.

> 7) orqv, pmov, tblq, tbxq, uzpq{1,2}, and zipq{1,2} are entirely missing.

I'm aware the above mentioned instructions are missing in binutils and 
I'm currently

working on adding support for these instructions. I will update you once 
the patches

are committed.

Regards,

Srinath

> Despite being newer it's of course possible that documentation is what
> actually needs fixing. Can you please clarify which way it is?
>
> Thanks, Jan