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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2024 18:02:30.5696 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e172e7e8-23c5-478f-ab54-08dc871bffd3 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF00009527.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB8344 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,GIT_PATCH_0,KAM_LOTSOFHASH,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This includes all the instructions under the following features: - FEAT_FP8FMA (+fp8fma) - FEAT_FP8DOT4 (+fp8dot4) - FEAT_FP8DOT2 (+fp8dot2) - FEAT_SSVE_FP8FMA (+ssve-fp8fma) - FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4) - FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2) Is this ok for master? diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index c421bfdac1f423344f5ecdb998d1d0b8d24f3ae5..e88b8401690da6e62b54088814d45e9b5b23e5db 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -820,6 +820,10 @@ vectype_to_qualifier (const struct vector_type_el *vectype) if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH)) { + /* Special case S_2B. */ + if (vectype->type == NT_b && vectype->width == 2) + return AARCH64_OPND_QLF_S_2B; + /* Special case S_4B. */ if (vectype->type == NT_b && vectype->width == 4) return AARCH64_OPND_QLF_S_4B; @@ -1010,7 +1014,7 @@ aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier) succeeds; otherwise return FALSE. Accept only one occurrence of: - 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d + 2b 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d b h s d q */ static bool parse_vector_type_for_operand (aarch64_reg_type reg_type, @@ -1074,6 +1078,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type, if (width != 0 && width * element_size != 64 && width * element_size != 128 && !(width == 2 && element_size == 16) + && !(width == 2 && element_size == 8) && !(width == 4 && element_size == 8)) { first_error_fmt (_ @@ -6271,6 +6276,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: operand->reglane.regno = default_value; break; @@ -6791,6 +6797,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: @@ -6816,6 +6823,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: reg_type = REG_TYPE_V; vector_reg_index: @@ -10551,6 +10559,15 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"faminmax", AARCH64_FEATURE (FAMINMAX), AARCH64_FEATURE (SIMD)}, {"fp8", AARCH64_FEATURE (FP8), AARCH64_FEATURE (SIMD)}, {"lut", AARCH64_FEATURE (LUT), AARCH64_FEATURE (SIMD)}, + {"fp8fma", AARCH64_FEATURE (FP8FMA), AARCH64_FEATURE (FP8)}, + {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8FMA)}, + {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8DOT4)}, + {"ssve-fp8fma", AARCH64_FEATURE (SSVE_FP8FMA), + AARCH64_FEATURES (2, FP8, SME2)}, + {"ssve-fp8dot4", AARCH64_FEATURE (SSVE_FP8DOT4), + AARCH64_FEATURE (SSVE_FP8FMA)}, + {"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2), + AARCH64_FEATURE (SSVE_FP8DOT4)}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index bdfb504a5c55598d595ac13448b6af7ca0142da9..057f54d2bcb6dc7ac5155a481ffaffec356fb95d 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -189,6 +189,12 @@ automatically cause those extensions to be disabled. @tab Enable Flag Manipulation instructions. @item @code{flagm2} @tab @code{flagm} @tab Enable FlagM2 flag conversion instructions. +@item @code{fp8dot2} @tab @code{fp8dot4} + @tab Enable the FP8 2-way dot product instructions. +@item @code{fp8dot4} @tab @code{fp8fma} + @tab Enable the FP8 4-way dot product instructions. +@item @code{fp8fma} @tab @code{fp8} + @tab Enable the FP8 FMA instructions. @item @code{fp16fml} @tab @code{fp16} @tab Enable Armv8.2 16-bit floating-point multiplication variant support. @item @code{fp16} @tab @code{fp} @@ -267,6 +273,12 @@ automatically cause those extensions to be disabled. @tab Enable SME2.1. @item @code{ssbs} @tab @tab Enable Speculative Store Bypassing Safe state read and write. +@item @code{ssve-fp8dot2} @tab @code{ssve-fp8dot4} + @tab Enable the Streaming SVE FP8 2-way dot product instructions. These can also be enabled using @code{+fp8dot2+sme2}. +@item @code{ssve-fp8dot4} @tab @code{ssve-fp8fma} + @tab Enable the Streaming SVE FP8 4-way dot product instructions. These can also be enabled using @code{+fp8dot4+sme2}. +@item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8} + @tab Enable the Streaming SVE FP8 FMA instructions. These can also be enabled using @code{+fp8fma+sme2}. @item @code{sve} @tab @code{fcma} @tab Enable the Scalable Vector Extension. @item @code{sve2} @tab @code{sve} diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..1dac59a5d820670e94f65d7dba510b011609d631 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+fp8dot2 +#error_output: fp8-mul-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..155c24b035ccbf664cb2f26bce9f267d4d197931 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l @@ -0,0 +1,24 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.4h,v0\.8b,v16\.2b\[0\]' +[^:]*:2: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.4h,v0\.8b,v0\.2b\[8\]' +[^:]*:3: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.8h,v0\.16b,v16\.2b\[0\]' +[^:]*:4: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.8h,v0\.16b,v0\.2b\[8\]' +[^:]*:6: Error: operand mismatch -- `fmlalb v0\.4h,v0\.8b,v0\.8b' +[^:]*:6: Info: did you mean this\? +[^:]*:6: Info: \tfmlalb v0\.8h, v0\.16b, v0\.16b +[^:]*:8: Error: register number out of range 0 to 7 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v8\.b\[0\]' +[^:]*:9: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v0\.b\[16\]' +[^:]*:10: Error: register number out of range 0 to 7 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v8\.b\[0\]' +[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v0\.b\[16\]' +[^:]*:13: Error: operand mismatch -- `fmlallbb v0\.2s,v0\.8b,v0\.8b' +[^:]*:13: Info: did you mean this\? +[^:]*:13: Info: \tfmlallbb v0\.4s, v0\.16b, v0\.16b +[^:]*:15: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:16: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:17: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:18: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:19: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:21: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:22: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v0\.b\[16\]' + diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..1b75cb68a1dde911285d4d978e6180a61660c5a7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s @@ -0,0 +1,24 @@ +fdot v0.4h, v0.8b, v16.2b[0] +fdot v0.4h, v0.8b, v0.2b[8] +fdot v0.8h, v0.16b, v16.2b[0] +fdot v0.8h, v0.16b, v0.2b[8] + +fmlalb v0.4h, v0.8b, v0.8b + +fmlalb v0.8h, v0.16b, v8.b[0] +fmlalb v0.8h, v0.16b, v0.b[16] +fmlalt v0.8h, v0.16b, v8.b[0] +fmlalt v0.8h, v0.16b, v0.b[16] + +fmlallbb v0.2s, v0.8b, v0.8b + +fmlallbb v0.4s, v0.16b, v8.b[0] +fmlallbb v0.4s, v0.16b, v0.b[16] +fmlallbt v0.4s, v0.16b, v8.b[0] +fmlallbt v0.4s, v0.16b, v0.b[16] +fmlalltb v0.4s, v0.16b, v8.b[0] +fmlalltb v0.4s, v0.16b, v0.b[16] +fmlalltt v0.4s, v0.16b, v8.b[0] +fmlalltt v0.4s, v0.16b, v0.b[16] + + diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.d b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d new file mode 100644 index 0000000000000000000000000000000000000000..7d740b711d2155b7d11638f24cc106da6b3ee109 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d @@ -0,0 +1,25 @@ +#as: -march=armv8-a+fp8dot2 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0e40fc00 fdot v0\.4h, v0\.8b, v0\.8b + *[0-9a-f]+: 0e5dff77 fdot v23\.4h, v27\.8b, v29\.8b + *[0-9a-f]+: 0e53feb9 fdot v25\.4h, v21\.8b, v19\.8b + *[0-9a-f]+: 4e40fc00 fdot v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 4e5dff77 fdot v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 4e53feb9 fdot v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 0f400000 fdot v0\.4h, v0\.8b, v0\.2b\[0\] + *[0-9a-f]+: 0f500000 fdot v0\.4h, v0\.8b, v0\.2b\[1\] + *[0-9a-f]+: 0f6e0377 fdot v23\.4h, v27\.8b, v14\.2b\[2\] + *[0-9a-f]+: 0f4d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[4\] + *[0-9a-f]+: 0f7d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[7\] + *[0-9a-f]+: 4f400000 fdot v0\.8h, v0\.16b, v0\.2b\[0\] + *[0-9a-f]+: 4f500000 fdot v0\.8h, v0\.16b, v0\.2b\[1\] + *[0-9a-f]+: 4f6e0377 fdot v23\.8h, v27\.16b, v14\.2b\[2\] + *[0-9a-f]+: 4f4d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[4\] + *[0-9a-f]+: 4f7d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[7\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.s b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s new file mode 100644 index 0000000000000000000000000000000000000000..3fff78afbc96bee395523d6e50b66021d207b3f4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s @@ -0,0 +1,19 @@ +fdot v0.4h, v0.8b, v0.8b +fdot v23.4h, v27.8b, v29.8b +fdot v25.4h, v21.8b, v19.8b + +fdot v0.8h, v0.16b, v0.16b +fdot v23.8h, v27.16b, v29.16b +fdot v25.8h, v21.16b, v19.16b + +fdot v0.4h, v0.8b, v0.2b[0] +fdot v0.4h, v0.8b, v0.2b[1] +fdot v23.4h, v27.8b, v14.2b[2] +fdot v25.4h, v21.8b, v13.2b[4] +fdot v25.4h, v21.8b, v13.2b[7] + +fdot v0.8h, v0.16b, v0.2b[0] +fdot v0.8h, v0.16b, v0.2b[1] +fdot v23.8h, v27.16b, v14.2b[2] +fdot v25.8h, v21.16b, v13.2b[4] +fdot v25.8h, v21.16b, v13.2b[7] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.d b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d new file mode 100644 index 0000000000000000000000000000000000000000..bf4632c30dddf70b58ca56b8de940c9bd73c8b88 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d @@ -0,0 +1,21 @@ +#as: -march=armv8-a+fp8dot4 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0e00fc00 fdot v0\.2s, v0\.8b, v0\.8b + *[0-9a-f]+: 0e1dff77 fdot v23\.2s, v27\.8b, v29\.8b + *[0-9a-f]+: 0e13feb9 fdot v25\.2s, v21\.8b, v19\.8b + *[0-9a-f]+: 4e00fc00 fdot v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e1dff77 fdot v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e13feb9 fdot v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 0f000000 fdot v0\.2s, v0\.8b, v0\.4b\[0\] + *[0-9a-f]+: 0f3d0377 fdot v23\.2s, v27\.8b, v29\.4b\[1\] + *[0-9a-f]+: 0f330ab9 fdot v25\.2s, v21\.8b, v19\.4b\[3\] + *[0-9a-f]+: 4f000000 fdot v0\.4s, v0\.16b, v0\.4b\[0\] + *[0-9a-f]+: 4f3d0377 fdot v23\.4s, v27\.16b, v29\.4b\[1\] + *[0-9a-f]+: 4f330ab9 fdot v25\.4s, v21\.16b, v19\.4b\[3\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.s b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s new file mode 100644 index 0000000000000000000000000000000000000000..cfd7283aed6708b5dc5186cb2951969338499ac8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s @@ -0,0 +1,15 @@ +fdot v0.2s, v0.8b, v0.8b +fdot v23.2s, v27.8b, v29.8b +fdot v25.2s, v21.8b, v19.8b + +fdot v0.4s, v0.16b, v0.16b +fdot v23.4s, v27.16b, v29.16b +fdot v25.4s, v21.16b, v19.16b + +fdot v0.2s, v0.8b, v0.4b[0] +fdot v23.2s, v27.8b, v29.4b[1] +fdot v25.2s, v21.8b, v19.4b[3] + +fdot v0.4s, v0.16b, v0.4b[0] +fdot v23.4s, v27.16b, v29.4b[1] +fdot v25.4s, v21.16b, v19.4b[3] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.d b/gas/testsuite/gas/aarch64/fp8-simd-fma.d new file mode 100644 index 0000000000000000000000000000000000000000..c9c8be6ef1360fcefba802a295123662bc375db2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.d @@ -0,0 +1,51 @@ +#as: -march=armv8-a+fp8fma +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0ec0fc00 fmlalb v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 0eddff77 fmlalb v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 0ed3feb9 fmlalb v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 4ec0fc00 fmlalt v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 4eddff77 fmlalt v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 4ed3feb9 fmlalt v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 0fc00000 fmlalb v0\.8h, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 0fdd0377 fmlalb v23\.8h, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 0fe702b9 fmlalb v25\.8h, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 0fc70ab9 fmlalb v25\.8h, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 4fc00000 fmlalt v0\.8h, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 4fdd0377 fmlalt v23\.8h, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 4fe702b9 fmlalt v25\.8h, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 4fc70ab9 fmlalt v25\.8h, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 0e00c400 fmlallbb v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 0e1dc777 fmlallbb v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 0e13c6b9 fmlallbb v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 0e40c400 fmlallbt v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 0e5dc777 fmlallbt v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 0e53c6b9 fmlallbt v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 4e00c400 fmlalltb v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e1dc777 fmlalltb v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e13c6b9 fmlalltb v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 4e40c400 fmlalltt v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e5dc777 fmlalltt v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e53c6b9 fmlalltt v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 2f008000 fmlallbb v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 2f1d8377 fmlallbb v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 2f2782b9 fmlallbb v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 2f078ab9 fmlallbb v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 2f408000 fmlallbt v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 2f5d8377 fmlallbt v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 2f6782b9 fmlallbt v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 2f478ab9 fmlallbt v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 6f008000 fmlalltb v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 6f1d8377 fmlalltb v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 6f2782b9 fmlalltb v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 6f078ab9 fmlalltb v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 6f408000 fmlalltt v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 6f5d8377 fmlalltt v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 6f6782b9 fmlalltt v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 6f478ab9 fmlalltt v25\.4s, v21\.16b, v7\.b\[8\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.s b/gas/testsuite/gas/aarch64/fp8-simd-fma.s new file mode 100644 index 0000000000000000000000000000000000000000..be7951465a0e40d1fbe373bfb59fffc3fb0fa74c --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.s @@ -0,0 +1,53 @@ +fmlalb v0.8h, v0.16b, v0.16b +fmlalb v23.8h, v27.16b, v29.16b +fmlalb v25.8h, v21.16b, v19.16b + +fmlalt v0.8h, v0.16b, v0.16b +fmlalt v23.8h, v27.16b, v29.16b +fmlalt v25.8h, v21.16b, v19.16b + +fmlalb v0.8h, v0.16b, v0.b[0] +fmlalb v23.8h, v27.16b, v5.b[3] +fmlalb v25.8h, v21.16b, v7.b[4] +fmlalb v25.8h, v21.16b, v7.b[8] + +fmlalt v0.8h, v0.16b, v0.b[0] +fmlalt v23.8h, v27.16b, v5.b[3] +fmlalt v25.8h, v21.16b, v7.b[4] +fmlalt v25.8h, v21.16b, v7.b[8] + +fmlallbb v0.4s, v0.16b, v0.16b +fmlallbb v23.4s, v27.16b, v29.16b +fmlallbb v25.4s, v21.16b, v19.16b + +fmlallbt v0.4s, v0.16b, v0.16b +fmlallbt v23.4s, v27.16b, v29.16b +fmlallbt v25.4s, v21.16b, v19.16b + +fmlalltb v0.4s, v0.16b, v0.16b +fmlalltb v23.4s, v27.16b, v29.16b +fmlalltb v25.4s, v21.16b, v19.16b + +fmlalltt v0.4s, v0.16b, v0.16b +fmlalltt v23.4s, v27.16b, v29.16b +fmlalltt v25.4s, v21.16b, v19.16b + +fmlallbb v0.4s, v0.16b, v0.b[0] +fmlallbb v23.4s, v27.16b, v5.b[3] +fmlallbb v25.4s, v21.16b, v7.b[4] +fmlallbb v25.4s, v21.16b, v7.b[8] + +fmlallbt v0.4s, v0.16b, v0.b[0] +fmlallbt v23.4s, v27.16b, v5.b[3] +fmlallbt v25.4s, v21.16b, v7.b[4] +fmlallbt v25.4s, v21.16b, v7.b[8] + +fmlalltb v0.4s, v0.16b, v0.b[0] +fmlalltb v23.4s, v27.16b, v5.b[3] +fmlalltb v25.4s, v21.16b, v7.b[4] +fmlalltb v25.4s, v21.16b, v7.b[8] + +fmlalltt v0.4s, v0.16b, v0.b[0] +fmlalltt v23.4s, v27.16b, v5.b[3] +fmlalltt v25.4s, v21.16b, v7.b[4] +fmlalltt v25.4s, v21.16b, v7.b[8] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.d b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d new file mode 100644 index 0000000000000000000000000000000000000000..d2633aa84532ba74c27944639a6440e95a2d7c40 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d @@ -0,0 +1,18 @@ +#as: -march=armv8-a+sve2+fp8dot2 +#as: -march=armv8-a+ssve-fp8dot2 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64208400 fdot z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 643d8777 fdot z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 643386b9 fdot z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64204400 fdot z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 642d4f77 fdot z23\.h, z27\.b, z5\.b\[3\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 643f4eb9 fdot z25\.h, z21\.b, z7\.b\[7\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.s b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s new file mode 100644 index 0000000000000000000000000000000000000000..839222eb7ead5887ee414fc1eba7c0d924241d29 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s @@ -0,0 +1,9 @@ +fdot z0.h, z0.b, z0.b +fdot z23.h, z27.b, z29.b +movprfx z25, z31 +fdot z25.h, z21.b, z19.b + +fdot z0.h, z0.b, z0.b[0] +fdot z23.h, z27.b, z5.b[3] +movprfx z25, z31 +fdot z25.h, z21.b, z7.b[7] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.d b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d new file mode 100644 index 0000000000000000000000000000000000000000..ffb8d4ce18b7fcb43b6fe7438c9efa3f1ca68015 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d @@ -0,0 +1,18 @@ +#as: -march=armv8-a+sve2+fp8dot4 +#as: -march=armv8-a+ssve-fp8dot4 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64608400 fdot z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 647d8777 fdot z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 647386b9 fdot z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64604400 fdot z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 646d4777 fdot z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 647f46b9 fdot z25\.s, z21\.b, z7\.b\[3\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.s b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s new file mode 100644 index 0000000000000000000000000000000000000000..5cb8227f0403729857bd2fd24281a2d015a8b81b --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s @@ -0,0 +1,9 @@ +fdot z0.s, z0.b, z0.b +fdot z23.s, z27.b, z29.b +movprfx z25, z31 +fdot z25.s, z21.b, z19.b + +fdot z0.s, z0.b, z0.b[0] +fdot z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fdot z25.s, z21.b, z7.b[3] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.d b/gas/testsuite/gas/aarch64/fp8-sve-fma.d new file mode 100644 index 0000000000000000000000000000000000000000..97eae9e8c004e00658fdbdaef89a0261b50cde72 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.d @@ -0,0 +1,64 @@ +#as: -march=armv8-a+sve2+fp8fma +#as: -march=armv8-a+ssve-fp8fma +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64a08800 fmlalb z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 64bd8b77 fmlalb z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64b38ab9 fmlalb z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64205000 fmlalb z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64255777 fmlalb z23\.h, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 642f5ab9 fmlalb z25\.h, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 643f5eb9 fmlalb z25\.h, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64208800 fmlallbb z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643d8b77 fmlallbb z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64338ab9 fmlallbb z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 6420c000 fmlallbb z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 6425c777 fmlallbb z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 642fcab9 fmlallbb z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 643fceb9 fmlallbb z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64209800 fmlallbt z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643d9b77 fmlallbt z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64339ab9 fmlallbt z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 6460c000 fmlallbt z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 6465c777 fmlallbt z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 646fcab9 fmlallbt z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 647fceb9 fmlallbt z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 6420a800 fmlalltb z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643dab77 fmlalltb z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 6433aab9 fmlalltb z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64a0c000 fmlalltb z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64a5c777 fmlalltb z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64afcab9 fmlalltb z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64bfceb9 fmlalltb z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 6420b800 fmlalltt z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643dbb77 fmlalltt z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 6433bab9 fmlalltt z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64e0c000 fmlalltt z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64e5c777 fmlalltt z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64efcab9 fmlalltt z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64ffceb9 fmlalltt z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64a09800 fmlalt z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 64bd9b77 fmlalt z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64b39ab9 fmlalt z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64a05000 fmlalt z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64a55777 fmlalt z23\.h, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64af5ab9 fmlalt z25\.h, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64bf5eb9 fmlalt z25\.h, z21\.b, z7\.b\[15\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.s b/gas/testsuite/gas/aarch64/fp8-sve-fma.s new file mode 100644 index 0000000000000000000000000000000000000000..368e8da3656d755c781c493ab6f886f1edd1621d --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.s @@ -0,0 +1,65 @@ +fmlalb z0.h, z0.b, z0.b +fmlalb z23.h, z27.b, z29.b +movprfx z25, z31 +fmlalb z25.h, z21.b, z19.b + +fmlalb z0.h, z0.b, z0.b[0] +fmlalb z23.h, z27.b, z5.b[1] +movprfx z25, z31 +fmlalb z25.h, z21.b, z7.b[6] +fmlalb z25.h, z21.b, z7.b[15] + +fmlallbb z0.s, z0.b, z0.b +fmlallbb z23.s, z27.b, z29.b +movprfx z25, z31 +fmlallbb z25.s, z21.b, z19.b + +fmlallbb z0.s, z0.b, z0.b[0] +fmlallbb z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlallbb z25.s, z21.b, z7.b[6] +fmlallbb z25.s, z21.b, z7.b[15] + +fmlallbt z0.s, z0.b, z0.b +fmlallbt z23.s, z27.b, z29.b +movprfx z25, z31 +fmlallbt z25.s, z21.b, z19.b + +fmlallbt z0.s, z0.b, z0.b[0] +fmlallbt z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlallbt z25.s, z21.b, z7.b[6] +fmlallbt z25.s, z21.b, z7.b[15] + +fmlalltb z0.s, z0.b, z0.b +fmlalltb z23.s, z27.b, z29.b +movprfx z25, z31 +fmlalltb z25.s, z21.b, z19.b + +fmlalltb z0.s, z0.b, z0.b[0] +fmlalltb z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlalltb z25.s, z21.b, z7.b[6] +fmlalltb z25.s, z21.b, z7.b[15] + +fmlalltt z0.s, z0.b, z0.b +fmlalltt z23.s, z27.b, z29.b +movprfx z25, z31 +fmlalltt z25.s, z21.b, z19.b + +fmlalltt z0.s, z0.b, z0.b[0] +fmlalltt z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlalltt z25.s, z21.b, z7.b[6] +fmlalltt z25.s, z21.b, z7.b[15] + +fmlalt z0.h, z0.b, z0.b +fmlalt z23.h, z27.b, z29.b +movprfx z25, z31 +fmlalt z25.h, z21.b, z19.b + +fmlalt z0.h, z0.b, z0.b[0] +fmlalt z23.h, z27.b, z5.b[1] +movprfx z25, z31 +fmlalt z25.h, z21.b, z7.b[6] +fmlalt z25.h, z21.b, z7.b[15] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..f1d98eec161d095e59b922d7e682665634bd8d01 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sve2+fp8dot2 +#error_output: fp8-sve-mul-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..4f09c233de0921c415d032b26dc9181d891e791f --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: z0-z7 expected at operand 3 -- `fdot z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:2: Error: register element index out of range 0 to 3 at operand 3 -- `fdot z0\.s,z0\.b,z0\.b\[4\]' +[^:]*:4: Error: z0-z7 expected at operand 3 -- `fdot z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:5: Error: register element index out of range 0 to 7 at operand 3 -- `fdot z0\.h,z0\.b,z0\.b\[8\]' +[^:]*:7: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:8: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb z0\.h,z0\.b,z0\.b\[16\]' +[^:]*:10: Error: z0-z7 expected at operand 3 -- `fmlallbb z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:13: Error: z0-z7 expected at operand 3 -- `fmlallbt z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:16: Error: z0-z7 expected at operand 3 -- `fmlalltb z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:17: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:19: Error: z0-z7 expected at operand 3 -- `fmlalltt z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:22: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:23: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt z0\.h,z0\.b,z0\.b\[16\]' +[^:]*:26: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.s,z0\.b,z0\.b\[0\]' +[^:]*:29: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.h,z0\.b,z0\.b\[0\]' +[^:]*:32: Warning: predicated instruction expected after `movprfx' -- `fmlalb z25\.h,z0\.b,z0\.b\[0\]' +[^:]*:35: Warning: predicated instruction expected after `movprfx' -- `fmlallbb z25\.s,z0\.b,z0\.b\[0\]' diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..c8e3f9dc84084119984597dbd271fdce4e9bd015 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s @@ -0,0 +1,35 @@ +fdot z0.s, z0.b, z8.b[0] +fdot z0.s, z0.b, z0.b[4] + +fdot z0.h, z0.b, z8.b[0] +fdot z0.h, z0.b, z0.b[8] + +fmlalb z0.h, z0.b, z8.b[0] +fmlalb z0.h, z0.b, z0.b[16] + +fmlallbb z0.s, z0.b, z8.b[0] +fmlallbb z0.s, z0.b, z0.b[16] + +fmlallbt z0.s, z0.b, z8.b[0] +fmlallbt z0.s, z0.b, z0.b[16] + +fmlalltb z0.s, z0.b, z8.b[0] +fmlalltb z0.s, z0.b, z0.b[16] + +fmlalltt z0.s, z0.b, z8.b[0] +fmlalltt z0.s, z0.b, z0.b[16] + +fmlalt z0.h, z0.b, z8.b[0] +fmlalt z0.h, z0.b, z0.b[16] + +movprfx z25.s, p0/m, z31.s +fdot z25.s, z0.b, z0.b[0] + +movprfx z25.h, p0/z, z31.h +fdot z25.h, z0.b, z0.b[0] + +movprfx z25.h, p0/z, z31.h +fmlalb z25.h, z0.b, z0.b[0] + +movprfx z25.s, p0/m, z31.s +fmlallbb z25.s, z0.b, z0.b[0] diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index 20b7a5e1d4d558aac9632e8213ee58a419f27d68..778c40d87a51cbefe17477185e0e962686ebb114 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -419,11 +419,11 @@ [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]' [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]' -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: fmlalb z0\.s, z0\.h, z0\.h\[0\] -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalb z0\.s,z0\.h,z32\.h' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d' @@ -432,11 +432,11 @@ [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]' [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]' -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: fmlalt z0\.s, z0\.h, z0\.h\[0\] -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalt z0\.s,z0\.h,z32\.h' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d' diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9da73a932f7083b0e6d9964eda5e38124808f5da..7b4145c8e820070654481a2e84e3565581a4924e 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -238,6 +238,18 @@ enum aarch64_feature_bit { AARCH64_FEATURE_FP8, /* LUT instructions. */ AARCH64_FEATURE_LUT, + /* FP8FMA instructions. */ + AARCH64_FEATURE_FP8FMA, + /* FP8DOT4 instructions. */ + AARCH64_FEATURE_FP8DOT4, + /* FP8DOT2 instructions. */ + AARCH64_FEATURE_FP8DOT2, + /* SSVE FP8FMA instructions. */ + AARCH64_FEATURE_SSVE_FP8FMA, + /* SSVE FP8DOT4 instructions. */ + AARCH64_FEATURE_SSVE_FP8DOT4, + /* SSVE FP8DOT2 instructions. */ + AARCH64_FEATURE_SSVE_FP8DOT2, AARCH64_NUM_FEATURES }; @@ -524,7 +536,9 @@ enum aarch64_opnd AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when - qualifier is S_H. */ + qualifier is S_H or S_2B. */ + AARCH64_OPND_Em8, /* AdvSIMD Vector Element Vm restricted to V0 - V7, + used only with qualifier S_B. */ AARCH64_OPND_Em_INDEX1_14, /* AdvSIMD 1-bit encoded index in Vm at [14] */ AARCH64_OPND_Em_INDEX2_13, /* AdvSIMD 2-bit encoded index in Vm at [14:13] */ AARCH64_OPND_Em_INDEX3_12, /* AdvSIMD 3-bit encoded index in Vm at [14:12] */ @@ -744,6 +758,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm3_12_INDEX, /* SVE bit index in Zm, bits 12 plus bit [23,22]. */ AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ + AARCH64_OPND_SVE_Zm3_10_INDEX, /* z0-z7[0-15] in Zm3_INDEX plus bit 11:10. */ AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ @@ -858,11 +873,12 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_S_S, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_Q, - /* These type qualifiers have a special meaning in that they mean 4 x 1 byte - or 2 x 2 byte are selected by the instruction. Other than that they have - no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely - for syntactical reasons and is an exception from normal AArch64 - disassembly scheme. */ + /* These type qualifiers have a special meaning in that they mean 2 x 1 byte, + 4 x 1 byte or 2 x 2 byte are selected by the instruction. Other than that + they have no difference with AARCH64_OPND_QLF_S_B in encoding. They are + here purely for syntactical reasons and is an exception from normal + AArch64 disassembly scheme. */ + AARCH64_OPND_QLF_S_2B, AARCH64_OPND_QLF_S_4B, AARCH64_OPND_QLF_S_2H, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index a4b02cd9a258e4b9bd4fc477573a1fcd6365401b..8db8f78c8ba4752e39908c07e94c72250aa24768 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -650,9 +650,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 121: case 122: - case 180: + case 123: case 181: case 182: case 183: @@ -666,30 +665,31 @@ aarch64_insert_operand (const aarch64_operand *self, case 191: case 192: case 193: - case 208: + case 194: case 209: case 210: case 211: - case 220: + case 212: case 221: case 222: case 223: case 224: - case 235: - case 239: - case 243: - case 250: - case 251: - case 258: - case 259: + case 225: + case 237: + case 241: + case 245: + case 252: + case 253: case 260: case 261: + case 262: + case 263: return aarch64_ins_regno (self, info, code, inst, errors); case 6: - case 118: case 119: - case 293: + case 120: case 295: + case 297: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -703,18 +703,17 @@ aarch64_insert_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 297: - return aarch64_ins_reglane (self, info, code, inst, errors); case 39: + case 299: + return aarch64_ins_reglane (self, info, code, inst, errors); case 40: case 41: - case 225: + case 42: case 226: - case 229: - case 262: - case 263: - case 278: - case 279: + case 227: + case 230: + case 264: + case 265: case 280: case 281: case 282: @@ -726,22 +725,23 @@ aarch64_insert_operand (const aarch64_operand *self, case 288: case 289: case 290: + case 291: + case 292: return aarch64_ins_simple_index (self, info, code, inst, errors); - case 42: - return aarch64_ins_reglist (self, info, code, inst, errors); case 43: - return aarch64_ins_ldst_reglist (self, info, code, inst, errors); + return aarch64_ins_reglist (self, info, code, inst, errors); case 44: - return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 45: - return aarch64_ins_lut_reglist (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 46: - return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ins_lut_reglist (self, info, code, inst, errors); case 47: + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); case 48: case 49: case 50: - case 60: + case 51: case 61: case 62: case 63: @@ -758,14 +758,14 @@ aarch64_insert_operand (const aarch64_operand *self, case 74: case 75: case 76: - case 88: + case 77: case 89: case 90: case 91: - case 117: - case 177: - case 179: - case 200: + case 92: + case 118: + case 178: + case 180: case 201: case 202: case 203: @@ -773,102 +773,102 @@ aarch64_insert_operand (const aarch64_operand *self, case 205: case 206: case 207: - case 264: - case 291: - case 292: + case 208: + case 266: + case 293: case 294: case 296: - case 301: - case 302: + case 298: + case 303: + case 304: return aarch64_ins_imm (self, info, code, inst, errors); - case 51: case 52: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 53: + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 54: case 55: + case 56: return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); - case 59: - case 167: + case 60: + case 168: return aarch64_ins_fpimm (self, info, code, inst, errors); - case 77: - case 175: - return aarch64_ins_limm (self, info, code, inst, errors); case 78: - return aarch64_ins_aimm (self, info, code, inst, errors); + case 176: + return aarch64_ins_limm (self, info, code, inst, errors); case 79: - return aarch64_ins_imm_half (self, info, code, inst, errors); + return aarch64_ins_aimm (self, info, code, inst, errors); case 80: + return aarch64_ins_imm_half (self, info, code, inst, errors); + case 81: return aarch64_ins_fbits (self, info, code, inst, errors); - case 82: case 83: - case 172: - return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 84: - case 171: case 173: - return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 85: + case 172: + case 174: + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 86: + case 87: return aarch64_ins_cond (self, info, code, inst, errors); - case 92: - case 101: - return aarch64_ins_addr_simple (self, info, code, inst, errors); case 93: - return aarch64_ins_addr_regoff (self, info, code, inst, errors); + case 102: + return aarch64_ins_addr_simple (self, info, code, inst, errors); case 94: + return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 95: case 96: - case 98: - case 100: - return aarch64_ins_addr_simm (self, info, code, inst, errors); case 97: - return aarch64_ins_addr_simm10 (self, info, code, inst, errors); case 99: + case 101: + return aarch64_ins_addr_simm (self, info, code, inst, errors); + case 98: + return aarch64_ins_addr_simm10 (self, info, code, inst, errors); + case 100: return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); - case 102: - return aarch64_ins_addr_offset (self, info, code, inst, errors); case 103: - return aarch64_ins_simd_addr_post (self, info, code, inst, errors); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 104: + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 105: - return aarch64_ins_sysreg (self, info, code, inst, errors); case 106: - return aarch64_ins_pstatefield (self, info, code, inst, errors); + return aarch64_ins_sysreg (self, info, code, inst, errors); case 107: + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 108: case 109: case 110: case 111: case 112: - return aarch64_ins_sysins_op (self, info, code, inst, errors); case 113: - case 115: - return aarch64_ins_barrier (self, info, code, inst, errors); + return aarch64_ins_sysins_op (self, info, code, inst, errors); case 114: - return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); case 116: + return aarch64_ins_barrier (self, info, code, inst, errors); + case 115: + return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); + case 117: return aarch64_ins_prfop (self, info, code, inst, errors); - case 120: + case 121: return aarch64_ins_hint (self, info, code, inst, errors); - case 123: case 124: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 125: + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 126: case 127: case 128: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 129: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 130: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 131: + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 132: case 133: case 134: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 135: + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 136: case 137: case 138: @@ -883,8 +883,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 147: case 148: case 149: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 150: + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 151: case 152: case 153: @@ -892,116 +892,118 @@ aarch64_insert_operand (const aarch64_operand *self, case 155: case 156: case 157: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 158: + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 159: case 160: case 161: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 162: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 163: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 164: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 165: - return aarch64_ins_sve_aimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 166: + return aarch64_ins_sve_aimm (self, info, code, inst, errors); + case 167: return aarch64_ins_sve_asimm (self, info, code, inst, errors); - case 168: - return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 169: - return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 170: + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + case 171: return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); - case 174: + case 175: return aarch64_ins_inv_limm (self, info, code, inst, errors); - case 176: + case 177: return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); - case 178: + case 179: return aarch64_ins_sve_scale (self, info, code, inst, errors); - case 194: case 195: case 196: - return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 197: + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 198: case 199: - case 277: + case 200: + case 279: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 212: case 213: case 214: case 215: - return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 216: + return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 217: case 218: case 219: + case 220: return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors); - case 227: case 228: - case 230: + case 229: case 231: case 232: case 233: case 234: - return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 235: case 236: + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 238: return aarch64_ins_sve_index_imm (self, info, code, inst, errors); - case 237: + case 239: return aarch64_ins_sve_index (self, info, code, inst, errors); - case 238: case 240: - case 257: - case 303: - case 304: + case 242: + case 259: case 305: + case 306: + case 307: return aarch64_ins_sve_reglist (self, info, code, inst, errors); - case 241: - case 242: + case 243: case 244: - case 245: case 246: case 247: - case 256: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 248: case 249: + case 258: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); + case 250: + case 251: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 252: case 254: - case 265: + case 256: + case 267: return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); - case 253: case 255: + case 257: return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 266: - case 267: case 268: case 269: case 270: case 271: case 272: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 273: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 274: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 275: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 276: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 277: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 278: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 298: - case 299: case 300: + case 301: + case 302: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 306: - case 307: case 308: case 309: - return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 310: + case 311: + return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 312: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 5c6a31167c617f59e62a108e00c6e806cd6ec4ed..83d9dd3212751748fbbdc401310bb36d7250f32a 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -153,10 +153,15 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, { case AARCH64_OPND_QLF_S_4B: case AARCH64_OPND_QLF_S_2H: - /* L:H */ + /* H:L */ assert (reglane_index < 4); insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H); break; + case AARCH64_OPND_QLF_S_2B: + /* H:L:M */ + assert (reglane_index < 8); + insert_fields (code, reglane_index, 0, 3, FLD_M, FLD_L, FLD_H); + break; default: return false; } @@ -180,6 +185,11 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + assert (reglane_index < 16); + insert_fields (code, reglane_index, 0, 2, FLD_imm3_19, FLD_H); + break; case AARCH64_OPND_QLF_S_H: /* H:L:M */ assert (reglane_index < 8); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 35501d6777e06de4a7d8784648c436c29b22554b..81d71f28fd191a22830d34165378e9404b18f54b 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -17252,11 +17252,33 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0001xxxxx010xxxxxxxxxxxxx - fdot. */ - return 2472; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0100x0xxxxxxxxxx + fdot. */ + return 2472; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0100x1xxxxxxxxxx + fdot. */ + return 3412; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0101xxxxxxxxxxxx + fmlalb. */ + return 3414; + } } else { @@ -17271,21 +17293,32 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0101xxxxx010xx0xxxxxxxxxx - fmlalb. */ - return 2145; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx0100x0xxxxxxxxxx + fmlalb. */ + return 2145; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx0100x1xxxxxxxxxx + fmlalt. */ + return 2147; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0101xxxxx010xx1xxxxxxxxxx + 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 2147; + return 3424; } } else @@ -17304,11 +17337,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0011xxxxx010xxxxxxxxxxxxx - bfdot. */ - return 3065; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0011xxxxx010xx0xxxxxxxxxx + bfdot. */ + return 3065; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0011xxxxx010xx1xxxxxxxxxx + fdot. */ + return 3410; + } } else { @@ -17358,31 +17402,108 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x0001xxxxx1x0xxxxxxxxxxxxx - fdot. */ - return 2473; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx100000xxxxxxxxxx + fdot. */ + return 2473; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx100010xxxxxxxxxx + fmlallbb. */ + return 3415; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1000x1xxxxxxxxxx + fdot. */ + return 3411; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1100xxxxxxxxxxxx + fmlallbb. */ + return 3416; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1x01xxxxxxxxxxxx + fmlallbt. */ + return 3417; + } } else { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0101xxxxx1x0xx0xxxxxxxxxx - fmlalb. */ - return 2146; + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx100000xxxxxxxxxx + fmlalb. */ + return 2146; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx100010xxxxxxxxxx + fmlalb. */ + return 3413; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx1000x1xxxxxxxxxx + fmlalt. */ + return 2148; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx1100xxxxxxxxxxxx + fmlalltb. */ + return 3420; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0101xxxxx1x0xx1xxxxxxxxxx + 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 2148; + return 3423; } } else @@ -17399,31 +17520,64 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x0011xxxxx1x0xxxxxxxxxxxxx - bfdot. */ - return 3064; + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx100xx0xxxxxxxxxx + bfdot. */ + return 3064; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx100xx1xxxxxxxxxx + fdot. */ + return 3409; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx110xxxxxxxxxxxxx + fmlallbt. */ + return 3418; + } } else { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0111xxxxx1x0xx0xxxxxxxxxx - bfmlalb. */ - return 3070; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0111xxxxx100xx0xxxxxxxxxx + bfmlalb. */ + return 3070; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0111xxxxx100xx1xxxxxxxxxx + bfmlalt. */ + return 3069; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0111xxxxx1x0xx1xxxxxxxxxx - bfmlalt. */ - return 3069; + 011001x0111xxxxx110xxxxxxxxxxxxx + fmlalltt. */ + return 3422; } } else @@ -17729,32 +17883,54 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - if (((word >> 31) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0x01xxxxx101xx0xxxxxxxxxx - fmlslb. */ - return 2150; + x11001x0001xxxxx1010xxxxxxxxxxxx + fmlalltb. */ + return 3419; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0x01xxxxx101xx1xxxxxxxxxx - fmlslt. */ - return 2152; + x11001x0001xxxxx1011xxxxxxxxxxxx + fmlalltt. */ + return 3421; } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 111001x0x01xxxxx101xxxxxxxxxxxxx - st1h. */ - return 1953; + if (((word >> 31) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx101xx0xxxxxxxxxx + fmlslb. */ + return 2150; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx101xx1xxxxxxxxxx + fmlslt. */ + return 2152; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 111001x0101xxxxx101xxxxxxxxxxxxx + st1h. */ + return 1953; + } } } else @@ -25943,31 +26119,75 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 13) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110x00xxxxxxx0001xxxxxxxxxx - dup. */ - return 149; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxx00001xxxxxxxxxx + dup. */ + return 149; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx00001xxxxxxxxxx + fmaxnm. */ + return 292; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxx00001xxxxxxxxxx + fminnm. */ + return 308; + } + } } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110010xxxxxxx0001xxxxxxxxxx - fmaxnm. */ - return 292; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110x00xxxxxx10001xxxxxxxxxx + fmlallbb. */ + return 3401; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110x00xxxxxx10001xxxxxxxxxx + fmlalltb. */ + return 3403; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110110xxxxxxx0001xxxxxxxxxx - fminnm. */ - return 308; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110x10xxxxxx10001xxxxxxxxxx + fmlallbt. */ + return 3402; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110x10xxxxxx10001xxxxxxxxxx + fmlalltt. */ + return 3404; + } } } } @@ -26176,37 +26396,81 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 22) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110x00xxxxxxx1111xxxxxxxxxx - umov. */ - return 152; - } - else + if (((word >> 14) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 0x001110010xxxxxxx1111xxxxxxxxxx - frecps. */ - return 304; + 0x001110x00xxxxxx01111xxxxxxxxxx + umov. */ + return 152; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110110xxxxxxx1111xxxxxxxxxx - frsqrts. */ - return 316; - } - } - } - } - } - } + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx01111xxxxxxxxxx + frecps. */ + return 304; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxx01111xxxxxxxxxx + frsqrts. */ + return 316; + } + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxx11111xxxxxxxxxx + fdot. */ + return 3393; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx11111xxxxxxxxxx + fdot. */ + return 3395; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110110xxxxxx11111xxxxxxxxxx + fmlalb. */ + return 3397; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110110xxxxxx11111xxxxxxxxxx + fmlalt. */ + return 3398; + } + } + } + } + } + } + } + } } else { @@ -31639,21 +31903,65 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 29) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0001111xxxxxxxx0000x0xxxxxxxxxx - fmlal. */ - return 3012; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx00111100xxxxxx0000x0xxxxxxxxxx + fdot. */ + return 3394; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x000111110xxxxxx0000x0xxxxxxxxxx + fmlal. */ + return 3012; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x100111110xxxxxx0000x0xxxxxxxxxx + fmlal. */ + return 3016; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1001111xxxxxxxx0000x0xxxxxxxxxx - fmlal. */ - return 3016; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx00111101xxxxxx0000x0xxxxxxxxxx + fdot. */ + return 3396; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x000111111xxxxxx0000x0xxxxxxxxxx + fmlalb. */ + return 3399; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x100111111xxxxxx0000x0xxxxxxxxxx + fmlalt. */ + return 3400; + } + } } } else @@ -32183,21 +32491,65 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 30) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0101111xxxxxxxx1000x0xxxxxxxxxx - fmlal2. */ - return 3014; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x010111100xxxxxx1000x0xxxxxxxxxx + fmlallbb. */ + return 3405; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x110111100xxxxxx1000x0xxxxxxxxxx + fmlalltb. */ + return 3407; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x010111110xxxxxx1000x0xxxxxxxxxx + fmlal2. */ + return 3014; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x110111110xxxxxx1000x0xxxxxxxxxx + fmlal2. */ + return 3018; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1101111xxxxxxxx1000x0xxxxxxxxxx - fmlal2. */ - return 3018; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0101111x1xxxxxx1000x0xxxxxxxxxx + fmlallbt. */ + return 3406; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1101111x1xxxxxx1000x0xxxxxxxxxx + fmlalltt. */ + return 3408; + } } } } @@ -33647,9 +33999,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 121: case 122: - case 180: + case 123: case 181: case 182: case 183: @@ -33663,30 +34014,31 @@ aarch64_extract_operand (const aarch64_operand *self, case 191: case 192: case 193: - case 208: + case 194: case 209: case 210: case 211: - case 220: + case 212: case 221: case 222: case 223: case 224: - case 235: - case 239: - case 243: - case 250: - case 251: - case 258: - case 259: + case 225: + case 237: + case 241: + case 245: + case 252: + case 253: case 260: case 261: + case 262: + case 263: return aarch64_ext_regno (self, info, code, inst, errors); case 6: - case 118: case 119: - case 293: + case 120: case 295: + case 297: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -33705,18 +34057,17 @@ aarch64_extract_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 297: - return aarch64_ext_reglane (self, info, code, inst, errors); case 39: + case 299: + return aarch64_ext_reglane (self, info, code, inst, errors); case 40: case 41: - case 225: + case 42: case 226: - case 229: - case 262: - case 263: - case 278: - case 279: + case 227: + case 230: + case 264: + case 265: case 280: case 281: case 282: @@ -33728,22 +34079,23 @@ aarch64_extract_operand (const aarch64_operand *self, case 288: case 289: case 290: + case 291: + case 292: return aarch64_ext_simple_index (self, info, code, inst, errors); - case 42: - return aarch64_ext_reglist (self, info, code, inst, errors); case 43: - return aarch64_ext_ldst_reglist (self, info, code, inst, errors); + return aarch64_ext_reglist (self, info, code, inst, errors); case 44: - return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 45: - return aarch64_ext_lut_reglist (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); case 46: - return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ext_lut_reglist (self, info, code, inst, errors); case 47: + return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); case 48: case 49: case 50: - case 60: + case 51: case 61: case 62: case 63: @@ -33760,15 +34112,15 @@ aarch64_extract_operand (const aarch64_operand *self, case 74: case 75: case 76: - case 87: + case 77: case 88: case 89: case 90: case 91: - case 117: - case 177: - case 179: - case 200: + case 92: + case 118: + case 178: + case 180: case 201: case 202: case 203: @@ -33776,104 +34128,104 @@ aarch64_extract_operand (const aarch64_operand *self, case 205: case 206: case 207: - case 264: - case 291: - case 292: + case 208: + case 266: + case 293: case 294: case 296: - case 301: - case 302: + case 298: + case 303: + case 304: return aarch64_ext_imm (self, info, code, inst, errors); - case 51: case 52: - return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 53: + return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 54: case 55: - return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); case 56: + return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); + case 57: return aarch64_ext_shll_imm (self, info, code, inst, errors); - case 59: - case 167: + case 60: + case 168: return aarch64_ext_fpimm (self, info, code, inst, errors); - case 77: - case 175: - return aarch64_ext_limm (self, info, code, inst, errors); case 78: - return aarch64_ext_aimm (self, info, code, inst, errors); + case 176: + return aarch64_ext_limm (self, info, code, inst, errors); case 79: - return aarch64_ext_imm_half (self, info, code, inst, errors); + return aarch64_ext_aimm (self, info, code, inst, errors); case 80: + return aarch64_ext_imm_half (self, info, code, inst, errors); + case 81: return aarch64_ext_fbits (self, info, code, inst, errors); - case 82: case 83: - case 172: - return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 84: - case 171: case 173: - return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 85: + case 172: + case 174: + return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); case 86: + case 87: return aarch64_ext_cond (self, info, code, inst, errors); - case 92: - case 101: - return aarch64_ext_addr_simple (self, info, code, inst, errors); case 93: - return aarch64_ext_addr_regoff (self, info, code, inst, errors); + case 102: + return aarch64_ext_addr_simple (self, info, code, inst, errors); case 94: + return aarch64_ext_addr_regoff (self, info, code, inst, errors); case 95: case 96: - case 98: - case 100: - return aarch64_ext_addr_simm (self, info, code, inst, errors); case 97: - return aarch64_ext_addr_simm10 (self, info, code, inst, errors); case 99: + case 101: + return aarch64_ext_addr_simm (self, info, code, inst, errors); + case 98: + return aarch64_ext_addr_simm10 (self, info, code, inst, errors); + case 100: return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); - case 102: - return aarch64_ext_addr_offset (self, info, code, inst, errors); case 103: - return aarch64_ext_simd_addr_post (self, info, code, inst, errors); + return aarch64_ext_addr_offset (self, info, code, inst, errors); case 104: + return aarch64_ext_simd_addr_post (self, info, code, inst, errors); case 105: - return aarch64_ext_sysreg (self, info, code, inst, errors); case 106: - return aarch64_ext_pstatefield (self, info, code, inst, errors); + return aarch64_ext_sysreg (self, info, code, inst, errors); case 107: + return aarch64_ext_pstatefield (self, info, code, inst, errors); case 108: case 109: case 110: case 111: case 112: - return aarch64_ext_sysins_op (self, info, code, inst, errors); case 113: - case 115: - return aarch64_ext_barrier (self, info, code, inst, errors); + return aarch64_ext_sysins_op (self, info, code, inst, errors); case 114: - return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); case 116: + return aarch64_ext_barrier (self, info, code, inst, errors); + case 115: + return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); + case 117: return aarch64_ext_prfop (self, info, code, inst, errors); - case 120: + case 121: return aarch64_ext_hint (self, info, code, inst, errors); - case 123: case 124: - return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 125: + return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 126: case 127: case 128: - return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 129: - return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 130: - return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 131: + return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 132: case 133: case 134: - return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 135: + return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 136: case 137: case 138: @@ -33888,8 +34240,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 147: case 148: case 149: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 150: + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 151: case 152: case 153: @@ -33897,117 +34249,119 @@ aarch64_extract_operand (const aarch64_operand *self, case 155: case 156: case 157: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 158: + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 159: case 160: case 161: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 162: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 163: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 164: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 165: - return aarch64_ext_sve_aimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 166: + return aarch64_ext_sve_aimm (self, info, code, inst, errors); + case 167: return aarch64_ext_sve_asimm (self, info, code, inst, errors); - case 168: - return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 169: - return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 170: + return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + case 171: return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); - case 174: + case 175: return aarch64_ext_inv_limm (self, info, code, inst, errors); - case 176: + case 177: return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); - case 178: + case 179: return aarch64_ext_sve_scale (self, info, code, inst, errors); - case 194: case 195: case 196: - return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 197: + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 198: case 199: - case 277: + case 200: + case 279: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 212: case 213: case 214: case 215: - return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 216: + return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 217: case 218: case 219: + case 220: return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors); - case 227: case 228: - case 230: + case 229: case 231: case 232: case 233: case 234: - return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 235: case 236: + return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 238: return aarch64_ext_sve_index_imm (self, info, code, inst, errors); - case 237: + case 239: return aarch64_ext_sve_index (self, info, code, inst, errors); - case 238: case 240: - case 257: - return aarch64_ext_sve_reglist (self, info, code, inst, errors); - case 241: case 242: + case 259: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); + case 243: case 244: - case 245: case 246: case 247: - case 256: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 248: case 249: + case 258: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); + case 250: + case 251: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 252: case 254: - case 265: + case 256: + case 267: return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); - case 253: case 255: + case 257: return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 266: - case 267: case 268: case 269: case 270: case 271: case 272: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 273: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 274: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 275: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 276: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 277: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 278: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 298: - case 299: case 300: + case 301: + case 302: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); - case 303: - case 304: case 305: - return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 306: case 307: + return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 308: case 309: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 310: + case 311: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 312: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index d92bc38ab6075a0bc989b576785a125ba67d696c..309e2922026316c5a2864fc407f7f5fffef8565f 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -402,6 +402,12 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); info->reglane.regno &= 0x1f; break; + case AARCH64_OPND_QLF_S_2B: + /* h:l:m */ + info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, + FLD_M); + info->reglane.regno &= 0xf; + break; default: return false; } @@ -422,7 +428,15 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, return 0; switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + info->reglane.index = extract_fields (code, 0, 2, FLD_H, + FLD_imm3_19); + info->reglane.regno &= 0x7; + break; + case AARCH64_OPND_QLF_S_H: + case AARCH64_OPND_QLF_S_2B: if (info->type == AARCH64_OPND_Em16) { /* h:l:m */ @@ -437,6 +451,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, } break; case AARCH64_OPND_QLF_S_S: + case AARCH64_OPND_QLF_S_4B: /* h:l */ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); break; diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index bd1aa4f27c19a3e4bc2aabb51e5f1a725556ca57..bead02701f55c37f53f432de7ed2601b49e0862b 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -63,6 +63,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V7"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm1_14}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm2_13}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm3_12}, "a SIMD vector without a type qualifier encoding a bit index"}, @@ -256,6 +257,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 8bf3fc8b874c940dbde2ca0ff4487050da3bea5b..7461bd8621b06129572074c44de88b996c3130b7 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -112,6 +112,7 @@ enum aarch64_field_kind FLD_SVE_i3h3, FLD_SVE_i3l, FLD_SVE_i3l2, + FLD_SVE_i4l2, FLD_SVE_imm3, FLD_SVE_imm4, FLD_SVE_imm5, @@ -169,6 +170,7 @@ enum aarch64_field_kind FLD_imm3_12, FLD_imm3_14, FLD_imm3_15, + FLD_imm3_19, FLD_imm4_0, FLD_imm4_5, FLD_imm4_10, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 29909606dc27798de57d568775efb7e8dc822a70..9e2440691d1567aa8ece76085a38d8636bc34a79 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -302,6 +302,7 @@ const aarch64_field fields[] = { 22, 2 }, /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */ { 12, 1 }, /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */ + { 10, 2 }, /* SVE_i4l2: two low bits of 4bit immediate, bits [11,10]. */ { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */ { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */ { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */ @@ -359,6 +360,7 @@ const aarch64_field fields[] = { 12, 3 }, /* imm3_12: general immediate in bits [14:12]. */ { 14, 3 }, /* imm3_14: general immediate in bits [16:14]. */ { 15, 3 }, /* imm3_15: general immediate in bits [17:15]. */ + { 19, 3 }, /* imm3_19: general immediate in bits [21:19]. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ @@ -809,6 +811,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] = {4, 1, 0x2, "s", OQK_OPD_VARIANT}, {8, 1, 0x3, "d", OQK_OPD_VARIANT}, {16, 1, 0x4, "q", OQK_OPD_VARIANT}, + {2, 1, 0x0, "2b", OQK_OPD_VARIANT}, {4, 1, 0x0, "4b", OQK_OPD_VARIANT}, {4, 1, 0x0, "2h", OQK_OPD_VARIANT}, @@ -1807,6 +1810,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: size = get_operand_fields_width (get_operand_from_code (type)); @@ -3215,12 +3219,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, 01 0:Rm 10 M:Rm 11 RESERVED */ - if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H + if (type == AARCH64_OPND_Em16 + && (qualifier == AARCH64_OPND_QLF_S_H + || qualifier == AARCH64_OPND_QLF_S_2B) && !value_in_range_p (opnd->reglane.regno, 0, 15)) { set_regno_out_of_range_error (mismatch_detail, idx, 0, 15); return 0; } + if (type == AARCH64_OPND_Em8 + && !value_in_range_p (opnd->reglane.regno, 0, 7)) + { + set_regno_out_of_range_error (mismatch_detail, idx, 0, 7); + return 0; + } break; case AARCH64_OPND_CLASS_MODIFIED_REG: @@ -4093,6 +4105,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: snprintf (buf, size, "%s[%s]", style_reg (styler, "v%d.%s", opnd->reglane.regno, @@ -4218,6 +4231,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 117806621484aad4c2d7907957d4b7c74bfa745f..78472deb073d7b661a22035e866f8aa38945543a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2199,6 +2199,10 @@ { \ QLF3(S_S,S_B,S_B), \ } +#define OP_SVE_VVV_H_B \ +{ \ + QLF3(S_H,S_B,S_B), \ +} #define OP_SVE_VVV_Q_D \ { \ QLF3(S_Q,S_D,S_D), \ @@ -2448,6 +2452,20 @@ QLF3(V_4S, V_16B, S_4B),\ } +/* e.g. FDOT .4H, .8B, .8B. */ +#define QL_V3DOTH \ +{ \ + QLF3(V_4H, V_8B, V_8B), \ + QLF3(V_8H, V_16B, V_16B),\ +} + +/* e.g. FDOT .4H, .8B, .2B[]. */ +#define QL_V2DOTH \ +{ \ + QLF3(V_4H, V_8B, S_2B),\ + QLF3(V_8H, V_16B, S_2B),\ +} + /* e.g. SHA512H , , .2D . */ #define QL_SHA512UPT \ { \ @@ -2514,6 +2532,30 @@ QLF3(V_4S, V_4H, S_H),\ } +/* e.g. FMLALB .8H, .16B, .16B. */ +#define QL_V3FML8H \ +{ \ + QLF3(V_8H, V_16B, V_16B),\ +} + +/* e.g. FMLALB .8H, .16B, .B. */ +#define QL_V2FML8H \ +{ \ + QLF3(V_8H, V_16B, S_B),\ +} + +/* e.g. FMLALLBB .4S, .16B, .16B. */ +#define QL_V3FMLL4S \ +{ \ + QLF3(V_4S, V_16B, V_16B),\ +} + +/* e.g. FMLALLBB .4S, .16B, .B. */ +#define QL_V2FMLL4S \ +{ \ + QLF3(V_4S, V_16B, S_B),\ +} + /* e.g. RMIF , #, #. */ #define QL_RMIF \ { \ @@ -2686,6 +2728,15 @@ FEATURE_SET_OR_1(fp8_sve2, AARCH64_FEATURES (2, FP8, SVE2)) FEATURE_SET_OR_1(fp8_sme2, AARCH64_FEATURES (2, FP8, SME2)) FEATURE_SET_OR_1(lut, AARCH64_FEATURE (LUT)) FEATURE_SET_OR_1(lut_sve2, AARCH64_FEATURES (2, LUT, SVE2)) +FEATURE_SET_OR_1(fp8fma, AARCH64_FEATURE (FP8FMA)) +FEATURE_SET_OR_1(fp8dot4, AARCH64_FEATURE (FP8DOT4)) +FEATURE_SET_OR_1(fp8dot2, AARCH64_FEATURE (FP8DOT2)) +FEATURE_SET_OR_2(fp8fma_sve, AARCH64_FEATURES (2, FP8FMA, SVE2), + AARCH64_FEATURE (SSVE_FP8FMA)) +FEATURE_SET_OR_2(fp8dot4_sve, AARCH64_FEATURES (2, FP8DOT4, SVE2), + AARCH64_FEATURE (SSVE_FP8DOT4)) +FEATURE_SET_OR_2(fp8dot2_sve, AARCH64_FEATURES (2, FP8DOT2, SVE2), + AARCH64_FEATURE (SSVE_FP8DOT2)) #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2762,6 +2813,12 @@ FEATURE_SET_OR_1(lut_sve2, AARCH64_FEATURES (2, LUT, SVE2)) #define FP8_SME2 &aarch64_feature_fp8_sme2 #define LUT &aarch64_feature_lut #define LUT_SVE2 &aarch64_feature_lut_sve2 +#define FP8FMA &aarch64_feature_fp8fma +#define FP8DOT4 &aarch64_feature_fp8dot4 +#define FP8DOT2 &aarch64_feature_fp8dot2 +#define FP8FMA_SVE &aarch64_feature_fp8fma_sve +#define FP8DOT4_SVE &aarch64_feature_fp8dot4_sve +#define FP8DOT2_SVE &aarch64_feature_fp8dot2_sve #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2960,6 +3017,18 @@ FEATURE_SET_OR_1(lut_sve2, AARCH64_FEATURES (2, LUT, SVE2)) #define LUT_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS,CONSTRAINTS) \ { NAME, OPCODE, MASK, lut, 0, LUT_SVE2, OPS, QUALS, \ FLAGS, CONSTRAINTS, 0, NULL } +#define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8DOT2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8FMA_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define FP8DOT4_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define FP8DOT2_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -6545,6 +6614,40 @@ const struct aarch64_opcode aarch64_opcode_table[] = LUT_SVE2_INSN ("luti4", 0x4520b400, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(2), 0), LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0), + FP8DOT4_INSN("fdot", 0x0e00fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + FP8DOT4_INSN("fdot", 0x0f000000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), + FP8DOT2_INSN("fdot", 0x0e40fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOTH, F_SIZEQ), + FP8DOT2_INSN("fdot", 0x0f400000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em16), QL_V2DOTH, F_SIZEQ), + FP8FMA_INSN("fmlalb", 0x0ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), + FP8FMA_INSN("fmlalt", 0x4ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), + FP8FMA_INSN("fmlalb", 0x0fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0), + FP8FMA_INSN("fmlalt", 0x4fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0), + FP8FMA_INSN("fmlallbb", 0x0e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlallbt", 0x0e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlalltb", 0x4e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlalltt", 0x4e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlallbb", 0x2f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlallbt", 0x2f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlalltb", 0x6f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlalltt", 0x6f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + + FP8DOT4_SVE_INSNC("fdot", 0x64608400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT4_SVE_INSNC("fdot", 0x64604400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT2_SVE_INSNC("fdot", 0x64208400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT2_SVE_INSNC("fdot", 0x64204400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalb", 0x64a08800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalb", 0x64205000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbb", 0x64208800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbb", 0x6420c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbt", 0x64209800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbt", 0x6460c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltb", 0x6420a800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltb", 0x64a0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltt", 0x6420b800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltt", 0x64e0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalt", 0x64a09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalt", 0x64a05000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -6620,6 +6723,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a SIMD vector element") \ Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ "a SIMD vector element limited to V0-V15") \ + Y(SIMD_ELEMENT, reglane, "Em8", 0, F(FLD_Rm), \ + "a SIMD vector element limited to V0-V7") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX1_14", 0, F(FLD_Rm, FLD_imm1_14), \ "a SIMD vector without a type qualifier encoding a bit index") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX2_13", 0, F(FLD_Rm, FLD_imm2_13), \ @@ -7039,6 +7144,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ + Y(SVE_REG, sve_quad_index, "SVE_Zm3_10_INDEX", \ + 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3), \ + "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \ 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \ "an indexed SVE vector register") \