From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 470333889E3B for ; Sun, 20 Nov 2022 01:09:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 470333889E3B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 9A2DC300089; Sun, 20 Nov 2022 01:09:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1668906551; bh=bqVKxVIxyP+rGuYBtRFvslLlo3JqQ7uHZKUZGeif3og=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=JLGVthPxg46iXX+Fep6E/cizuOr8CBnUXLaOGeiIpNapkwghAhKI2RjWBXISeIjAR /zBzGFq0OKsCqFDkL55TlTrnDsol01nnLKThokR+aAZA3v5XepJNYtsRVx6jXbBPdX tHTCjZh6b3muh9WyzeCeeA9KXRBipTYfInRSrUkE= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 2/3] RISC-V: Fallback on faster hash table Date: Sun, 20 Nov 2022 01:08:41 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Tsukasa OI Although it does not have a problem on current GNU Binutils implementation, if the custom vendor implements an instruction which spans across multiple major opcodes (e.g. uses both CUSTOM_0 and CUSTOM_1 in a *single* custom instruction), the original assumption of the sorted hash table breaks. In this case, this commit enables the fallback mode to disable all optimizations except filtering macros out. Note that, if a such instruction (that disables this disassembler optimization) is upstreamed to Binutils, a separate solution will be required to avoid major performance degradation when such instruction is not used. The intent of this commit is to make a room for custom vendors to implement such instructions in *their* tree without causing disassembler problems. opcodes/ChangeLog: * riscv-dis.c (is_riscv_hash_fallback) New. (build_riscv_opcodes_hash_table): If an instruction spans across multiple major opcodes, enable fallback mode and disable sorting. (riscv_disassemble_insn): If the fallback mode is enabled, scan through all instructions instead of scanning only instruction entries matching the hash value. --- opcodes/riscv-dis.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index a4a74e5733a5..197f6a31d439 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -838,6 +838,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info static const struct riscv_opcode **riscv_hash[OP_HASH_LEN + 1]; static const struct riscv_opcode **riscv_opcodes_sorted; +/* Whether the fallback should be used. */ +static bool is_riscv_hash_fallback = false; + /* Compare two riscv_opcode* objects to sort by hash index. */ static int @@ -868,15 +871,25 @@ build_riscv_opcodes_hash_table (void) /* Sort riscv_opcodes entry pointers (except macros). */ for (op = riscv_opcodes; op->name; op++) - if (op->pinfo != INSN_MACRO) + { + if (op->pinfo == INSN_MACRO) + continue; len++; + if (is_riscv_hash_fallback) + continue; + if (OP_HASH_IDX (op->match) < OP_MASK_OP2 + ? (op->mask & OP_MASK_OP2) != OP_MASK_OP2 + : (op->mask & OP_MASK_OP) != OP_MASK_OP) + is_riscv_hash_fallback = true; + } riscv_opcodes_sorted = xcalloc (len, sizeof (struct riscv_opcode *)); pop_end = riscv_opcodes_sorted; for (op = riscv_opcodes; op->name; op++) if (op->pinfo != INSN_MACRO) *pop_end++ = op; - qsort (riscv_opcodes_sorted, len, sizeof (struct riscv_opcode *), - compare_opcodes); + if (!is_riscv_hash_fallback) + qsort (riscv_opcodes_sorted, len, sizeof (struct riscv_opcode *), + compare_opcodes); /* Initialize faster hash table. */ pop = riscv_opcodes_sorted; @@ -919,8 +932,16 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) info->target2 = 0; matched_op = NULL; - pop = riscv_hash[OP_HASH_IDX (word)]; - pop_end = riscv_hash[OP_HASH_IDX (word) + 1]; + if (!is_riscv_hash_fallback) + { + pop = riscv_hash[OP_HASH_IDX (word)]; + pop_end = riscv_hash[OP_HASH_IDX (word) + 1]; + } + else + { + pop = riscv_hash[0]; + pop_end = riscv_hash[OP_HASH_LEN]; + } for (; pop != pop_end; pop++) { op = *pop; -- 2.38.1