From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20409 invoked by alias); 1 May 2019 17:08:17 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 20392 invoked by uid 89); 1 May 2019 17:08:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.9 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:08:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DC73580D for ; Wed, 1 May 2019 10:08:12 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60D953F719 for ; Wed, 1 May 2019 10:08:12 -0700 (PDT) Subject: [PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: Date: Wed, 01 May 2019 17:08:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------93523550DDEAB7D6B588CBCD" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00043.txt.bz2 This is a multi-part message in MIME format. --------------93523550DDEAB7D6B588CBCD Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1352 Hi, This patch adds support for MVE instructions VCADD, VCMLA, and VCMUL. gas/ChangeLog: 2019-05-01 Andre Vieira * config/tc-arm.c (enum operand_parse_code): New operands. (parse_operands): Handle new operands. (do_mve_vcmul): New encoding function. (do_vcmla): Change to support MVE variants. (do_vcadd): Change to support MVE variants. (insns): Change existing to support MVE variants and add new. * testsuite/gas/arm/mve-vcadd-bad-1.d: New test. * testsuite/gas/arm/mve-vcadd-bad-1.l: New test. * testsuite/gas/arm/mve-vcadd-bad-1.s: New test. * testsuite/gas/arm/mve-vcadd-bad-2.d: New test. * testsuite/gas/arm/mve-vcadd-bad-2.l: New test. * testsuite/gas/arm/mve-vcadd-bad-2.s: New test. * testsuite/gas/arm/mve-vcmla-bad-1.d: New test. * testsuite/gas/arm/mve-vcmla-bad-1.l: New test. * testsuite/gas/arm/mve-vcmla-bad-1.s: New test. * testsuite/gas/arm/mve-vcmla-bad-2.d: New test. * testsuite/gas/arm/mve-vcmla-bad-2.l: New test. * testsuite/gas/arm/mve-vcmla-bad-2.s: New test. * testsuite/gas/arm/mve-vcmul-bad-1.d: New test. * testsuite/gas/arm/mve-vcmul-bad-1.l: New test. * testsuite/gas/arm/mve-vcmul-bad-1.s: New test. * testsuite/gas/arm/mve-vcmul-bad-2.d: New test. * testsuite/gas/arm/mve-vcmul-bad-2.l: New test. * testsuite/gas/arm/mve-vcmul-bad-2.s: New test. --------------93523550DDEAB7D6B588CBCD Content-Type: text/x-patch; name="14.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="14.patch" Content-length: 21094 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index ce50b9e6040c8af62b7a5c3a4461da881b77d817..171ae9be36bfb5733037fbb0e4647be4acc2279f 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -6954,6 +6954,7 @@ enum operand_parse_code OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register. */ OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ + OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */ OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ OP_VMOV, /* Neon VMOV operands. */ OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ @@ -7349,6 +7350,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) } break; + case OP_RNDQMQ_RNSC: + po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc); + break; + try_rndq_rnsc: case OP_RNDQ_RNSC: { po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD); @@ -15577,6 +15582,38 @@ do_mve_vcmp (void) return; } +static void +do_mve_vcmul (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + unsigned rot = inst.relocs[0].exp.X_add_number; + constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, + _("immediate out of range")); + + if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg + || inst.operands[0].reg == inst.operands[2].reg)) + as_tsktsk (BAD_MVE_SRCDEST); + + inst.instruction |= (et.size == 32) << 28; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= (rot > 90) << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= HI1 (inst.operands[2].reg) << 5; + inst.instruction |= LOW4 (inst.operands[2].reg); + inst.instruction |= (rot == 90 || rot == 270); + inst.is_neon = 1; +} + static void do_vfp_nsyn_cmp (void) { @@ -19679,16 +19716,23 @@ neon_scalar_for_vcmla (unsigned opnd, unsigned elsize) static void do_vcmla (void) { - constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), - _(BAD_FPU)); + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) + && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8) + || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU)); constraint (inst.relocs[0].exp.X_op != O_constant, _("expression too complex")); unsigned rot = inst.relocs[0].exp.X_add_number; constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, _("immediate out of range")); rot /= 90; + + if (check_simd_pred_availability (1, NEON_CHECK_ARCH8 | NEON_CHECK_CC)) + return; + if (inst.operands[2].isscalar) { + if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) + first_error (_("invalid instruction shape")); enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL); unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32).size; @@ -19707,9 +19751,19 @@ do_vcmla (void) } else { - enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); + enum neon_shape rs; + if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) + rs = neon_select_shape (NS_QQQI, NS_NULL); + else + rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); + unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32).size; + if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32 + && (inst.operands[0].reg == inst.operands[1].reg + || inst.operands[0].reg == inst.operands[2].reg)) + as_tsktsk (BAD_MVE_SRCDEST); + neon_three_same (neon_quad (rs), 0, -1); inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ inst.instruction |= 0xfc200800; @@ -19721,20 +19775,60 @@ do_vcmla (void) static void do_vcadd (void) { - constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), - _(BAD_FPU)); + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) + && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8) + || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU)); constraint (inst.relocs[0].exp.X_op != O_constant, _("expression too complex")); + unsigned rot = inst.relocs[0].exp.X_add_number; constraint (rot != 90 && rot != 270, _("immediate out of range")); - enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); - unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, - N_KEY | N_F16 | N_F32).size; - neon_three_same (neon_quad (rs), 0, -1); - inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ - inst.instruction |= 0xfc800800; - inst.instruction |= (rot == 270) << 24; - inst.instruction |= (size == 32) << 20; + enum neon_shape rs; + struct neon_type_el et; + if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) + { + rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); + et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32); + } + else + { + rs = neon_select_shape (NS_QQQI, NS_NULL); + et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8 + | N_I16 | N_I32); + if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg) + as_tsktsk (_("Warning: 32-bit element size and same first and third " + "operand makes instruction UNPREDICTABLE")); + } + + if (et.type == NT_invtype) + return; + + if (check_simd_pred_availability (et.type == NT_float, NEON_CHECK_ARCH8 + | NEON_CHECK_CC)) + return; + + if (et.type == NT_float) + { + neon_three_same (neon_quad (rs), 0, -1); + inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ + inst.instruction |= 0xfc800800; + inst.instruction |= (rot == 270) << 24; + inst.instruction |= (et.size == 32) << 20; + } + else + { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); + inst.instruction = 0xfe000f00; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= neon_logbits (et.size) << 20; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= (rot == 270) << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= HI1 (inst.operands[2].reg) << 5; + inst.instruction |= LOW4 (inst.operands[2].reg); + inst.is_neon = 1; + } } /* Dot Product instructions encoding support. */ @@ -22721,8 +22815,6 @@ static const struct asm_opcode insns[] = #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v8_3 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt), - NUF (vcmla, 0, 4, (RNDQ, RNDQ, RNDQ_RNSC, EXPi), vcmla), - NUF (vcadd, 0, 4, (RNDQ, RNDQ, RNDQ, EXPi), vcadd), #undef ARM_VARIANT #define ARM_VARIANT & fpu_neon_ext_dotprod @@ -24089,6 +24181,10 @@ static const struct asm_opcode insns[] = mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv), mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv), +#undef THUMB_VARIANT +#define THUMB_VARIANT & mve_fp_ext + mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), + #undef ARM_VARIANT #define ARM_VARIANT & fpu_vfp_ext_v1 #undef THUMB_VARIANT @@ -24143,6 +24239,13 @@ static const struct asm_opcode insns[] = mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v8_3 +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2_v8m + MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd), + MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla), }; #undef ARM_VARIANT #undef THUMB_VARIANT diff --git a/gas/testsuite/gas/arm/mve-vcadd-bad-1.d b/gas/testsuite/gas/arm/mve-vcadd-bad-1.d new file mode 100644 index 0000000000000000000000000000000000000000..dbadb30cc8d0b2173b7ebcfc20edf86baab7f600 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcadd-bad-1.d @@ -0,0 +1,5 @@ +#name: bad MVE VCADD instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vcadd-bad-1.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vcadd-bad-1.l b/gas/testsuite/gas/arm/mve-vcadd-bad-1.l new file mode 100644 index 0000000000000000000000000000000000000000..dee86afb03018df799f689e087d730be2066617e --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcadd-bad-1.l @@ -0,0 +1,17 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: selected FPU does not support instruction -- `vcadd.f16 q0,q1,q2,#90' +[^:]*:11: Error: bad type in SIMD instruction -- `vcadd.64 q0,q1,q2,#90' +[^:]*:12: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#180' +[^:]*:13: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#0' +[^:]*:14: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90' +[^:]*:18: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90' +[^:]*:20: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcaddt.i16 q0,q1,q2,#90' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vcadd.i16 q0,q1,q2,#90' diff --git a/gas/testsuite/gas/arm/mve-vcadd-bad-1.s b/gas/testsuite/gas/arm/mve-vcadd-bad-1.s new file mode 100644 index 0000000000000000000000000000000000000000..23a686e63c1b5d506ccdd349ad8eb0e0cc69bae2 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcadd-bad-1.s @@ -0,0 +1,23 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vcadd.i16 q0, q1, q2, #90 +.endr +.endm + +.syntax unified +.thumb +vcadd.f16 q0, q1, q2, #90 +vcadd.64 q0, q1, q2, #90 +vcadd.i32 q0, q1, q2, #180 +vcadd.i32 q0, q1, q2, #0 +vcadd.i32 q0, q1, q0, #90 +cond +it eq +vcaddeq.i16 q0, q1, q2, #90 +vcaddeq.i16 q0, q1, q2, #90 +vpst +vcaddeq.i16 q0, q1, q2, #90 +vcaddt.i16 q0, q1, q2, #90 +vpst +vcadd.i16 q0, q1, q2, #90 diff --git a/gas/testsuite/gas/arm/mve-vcadd-bad-2.d b/gas/testsuite/gas/arm/mve-vcadd-bad-2.d new file mode 100644 index 0000000000000000000000000000000000000000..271160c31cee95b417c588c9c13359cf9b4f1e71 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcadd-bad-2.d @@ -0,0 +1,5 @@ +#name: bad MVE FP VCADD instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vcadd-bad-2.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vcadd-bad-2.l b/gas/testsuite/gas/arm/mve-vcadd-bad-2.l new file mode 100644 index 0000000000000000000000000000000000000000..cdf3fd3af9b5c7cd846d7659f24a8899d9561c6f --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcadd-bad-2.l @@ -0,0 +1,17 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vcadd.f64 q0,q1,q2,#90' +[^:]*:11: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#180' +[^:]*:12: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#0' +[^:]*:13: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90' +[^:]*:17: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90' +[^:]*:19: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90' +[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vcaddt.f16 q0,q1,q2,#90' +[^:]*:22: Error: instruction missing MVE vector predication code -- `vcadd.f16 q0,q1,q2,#90' + diff --git a/gas/testsuite/gas/arm/mve-vcadd-bad-2.s b/gas/testsuite/gas/arm/mve-vcadd-bad-2.s new file mode 100644 index 0000000000000000000000000000000000000000..9634840dbdaca5622aa9ba5333a1ae3c46b4e349 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcadd-bad-2.s @@ -0,0 +1,22 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vcadd.f32 q0, q1, q2, #90 +.endr +.endm + +.syntax unified +.thumb +vcadd.f64 q0, q1, q2, #90 +vcadd.f32 q0, q1, q2, #180 +vcadd.f32 q0, q1, q2, #0 +vcadd.f32 q0, q1, q0, #90 +cond +it eq +vcaddeq.f16 q0, q1, q2, #90 +vcaddeq.f16 q0, q1, q2, #90 +vpst +vcaddeq.f16 q0, q1, q2, #90 +vcaddt.f16 q0, q1, q2, #90 +vpst +vcadd.f16 q0, q1, q2, #90 diff --git a/gas/testsuite/gas/arm/mve-vcmla-bad-1.d b/gas/testsuite/gas/arm/mve-vcmla-bad-1.d new file mode 100644 index 0000000000000000000000000000000000000000..477486d7b0bc364c3a13962fbd557c4bb54554f0 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmla-bad-1.d @@ -0,0 +1,5 @@ +#name: bad MVE VCMLA instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vcmla-bad-1.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vcmla-bad-1.l b/gas/testsuite/gas/arm/mve-vcmla-bad-1.l new file mode 100644 index 0000000000000000000000000000000000000000..d660f4972ea6b66445cd3806ac9a5ba7542c99a3 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmla-bad-1.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:3: Error: selected FPU does not support instruction -- `vcmla.f16 q0,q1,q2,#0' +[^:]*:4: Error: selected FPU does not support instruction -- `vcmla.f32 q0,q1,q2,#0' diff --git a/gas/testsuite/gas/arm/mve-vcmla-bad-1.s b/gas/testsuite/gas/arm/mve-vcmla-bad-1.s new file mode 100644 index 0000000000000000000000000000000000000000..68202040a2e5112eb62f356696631843dc210be0 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmla-bad-1.s @@ -0,0 +1,4 @@ +.syntax unified +.thumb +vcmla.f16 q0, q1, q2, #0 +vcmla.f32 q0, q1, q2, #0 diff --git a/gas/testsuite/gas/arm/mve-vcmla-bad-2.d b/gas/testsuite/gas/arm/mve-vcmla-bad-2.d new file mode 100644 index 0000000000000000000000000000000000000000..6a95d41b4b6a6e8205991fa4a9589a2c6a5f10dd --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmla-bad-2.d @@ -0,0 +1,5 @@ +#name: bad MVE FP VCMLA instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vcmla-bad-2.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vcmla-bad-2.l b/gas/testsuite/gas/arm/mve-vcmla-bad-2.l new file mode 100644 index 0000000000000000000000000000000000000000..ca1d34950de044aa3c8ae108145d58f4a9704a0c --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmla-bad-2.l @@ -0,0 +1,17 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: immediate out of range -- `vcmla.f16 q0,q1,q2,#20' +[^:]*:11: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE +[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE +[^:]*:13: Error: bad type in SIMD instruction -- `vcmla.f64 q0,q1,q2,#0' +[^:]*:14: Error: bad type in SIMD instruction -- `vcmla.i16 q0,q1,q2,#0' +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0' +[^:]*:18: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0' +[^:]*:20: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcmlat.f16 q0,q1,q2,#0' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vcmla.f16 q0,q1,q2,#0' diff --git a/gas/testsuite/gas/arm/mve-vcmla-bad-2.s b/gas/testsuite/gas/arm/mve-vcmla-bad-2.s new file mode 100644 index 0000000000000000000000000000000000000000..d9ddb1f8735f4c01e97b2361e37db0bec122e04d --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmla-bad-2.s @@ -0,0 +1,23 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vcmla.f32 q0, q1, q2, #0 +.endr +.endm + +.syntax unified +.thumb +vcmla.f16 q0, q1, q2, #20 +vcmla.f32 q0, q0, q1, #0 +vcmla.f32 q0, q1, q0, #0 +vcmla.f64 q0, q1, q2, #0 +vcmla.i16 q0, q1, q2, #0 +cond +it eq +vcmlaeq.f16 q0, q1, q2, #0 +vcmlaeq.f16 q0, q1, q2, #0 +vpst +vcmlaeq.f16 q0, q1, q2, #0 +vcmlat.f16 q0, q1, q2, #0 +vpst +vcmla.f16 q0, q1, q2, #0 diff --git a/gas/testsuite/gas/arm/mve-vcmul-bad-1.d b/gas/testsuite/gas/arm/mve-vcmul-bad-1.d new file mode 100644 index 0000000000000000000000000000000000000000..34fb38f60885be72df5a8feb879f88985a30c8eb --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmul-bad-1.d @@ -0,0 +1,5 @@ +#name: bad MVE VCMUL instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vcmul-bad-1.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vcmul-bad-1.l b/gas/testsuite/gas/arm/mve-vcmul-bad-1.l new file mode 100644 index 0000000000000000000000000000000000000000..2b2e6c43317feaa4e0f0148c53b0f3762df538bf --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmul-bad-1.l @@ -0,0 +1,4 @@ +[^:]*: Assembler messages: +[^:]*:3: Error: selected processor does not support `vcmul.f16 q0,q1,q2,#0' in Thumb mode +[^:]*:4: Error: selected processor does not support `vcmul.f32 q0,q1,q2,#0' in Thumb mode +[^:]*:5: Error: selected processor does not support `vcmul.i16 q0,q1,q2,#0' in Thumb mode diff --git a/gas/testsuite/gas/arm/mve-vcmul-bad-1.s b/gas/testsuite/gas/arm/mve-vcmul-bad-1.s new file mode 100644 index 0000000000000000000000000000000000000000..e8b405d775f3b7e4ce902683376bd9976a6fe381 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmul-bad-1.s @@ -0,0 +1,5 @@ +.syntax unified +.thumb +vcmul.f16 q0, q1, q2, #0 +vcmul.f32 q0, q1, q2, #0 +vcmul.i16 q0, q1, q2, #0 diff --git a/gas/testsuite/gas/arm/mve-vcmul-bad-2.d b/gas/testsuite/gas/arm/mve-vcmul-bad-2.d new file mode 100644 index 0000000000000000000000000000000000000000..c440cbc87cbc7dde84140c2fa73da002eea9ca97 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmul-bad-2.d @@ -0,0 +1,5 @@ +#name: bad MVE FP VCMUL instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vcmul-bad-2.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vcmul-bad-2.l b/gas/testsuite/gas/arm/mve-vcmul-bad-2.l new file mode 100644 index 0000000000000000000000000000000000000000..c2e58a46cafeed9987ce6096c8264495f0cd9a61 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmul-bad-2.l @@ -0,0 +1,17 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vcmul.i16 q0,q1,q2,#0' +[^:]*:11: Error: bad type in SIMD instruction -- `vcmul.f64 q0,q1,q2,#0' +[^:]*:12: Error: immediate out of range -- `vcmul.f32 q0,q1,q2,#20' +[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE +[^:]*:14: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0' +[^:]*:18: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0' +[^:]*:20: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcmult.f32 q0,q1,q2,#0' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vcmul.f32 q0,q1,q2,#0' diff --git a/gas/testsuite/gas/arm/mve-vcmul-bad-2.s b/gas/testsuite/gas/arm/mve-vcmul-bad-2.s new file mode 100644 index 0000000000000000000000000000000000000000..4eedefabb1883c4eef8ef2d7e70010b61ca8ce48 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcmul-bad-2.s @@ -0,0 +1,23 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vcmul.f32 q0, q1, q2, #0 +.endr +.endm + +.syntax unified +.thumb +vcmul.i16 q0, q1, q2, #0 +vcmul.f64 q0, q1, q2, #0 +vcmul.f32 q0, q1, q2, #20 +vcmul.f32 q0, q1, q0, #0 +vcmul.f32 q0, q0, q1, #0 +cond +it eq +vcmuleq.f32 q0, q1, q2, #0 +vcmuleq.f32 q0, q1, q2, #0 +vpst +vcmuleq.f32 q0, q1, q2, #0 +vcmult.f32 q0, q1, q2, #0 +vpst +vcmul.f32 q0, q1, q2, #0 --------------93523550DDEAB7D6B588CBCD--