From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 38600 invoked by alias); 1 May 2019 17:38:57 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 38590 invoked by uid 89); 1 May 2019 17:38:57 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=mandated X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:38:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2CA7180D for ; Wed, 1 May 2019 10:38:55 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C10F43F719 for ; Wed, 1 May 2019 10:38:54 -0700 (PDT) Subject: [PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coprocessor instructions To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: Date: Wed, 01 May 2019 17:38:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------A4350442ED12A272F560A328" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00068.txt.bz2 This is a multi-part message in MIME format. --------------A4350442ED12A272F560A328 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 401 Hi, This patch disables the use of coprocessor numbers 8, 14 and 15 in coprocessor instructions for Armv8.1-M Mainline, adding to the already disabled 9, 10 and 11, as mandated by the architecture. opcodes/ChangeLog: 2019-05-01 Andre Vieira * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors 8, 14 and 15 for Armv8.1-M Mainline. --------------A4350442ED12A272F560A328 Content-Type: text/x-patch; name="38.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="38.patch" Content-length: 717 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 28c7f16de4b39f6aa580a0a9f4d4d775e1c4b768..8cd3514e7e53fc3a61ee97c7df1988c11a8143d0 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -3782,6 +3782,13 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes, { if (cp_num == 9 || cp_num == 10 || cp_num == 11) is_unpredictable = TRUE; + + /* Armv8.1-M Mainline FP & MVE instructions. */ + if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) + && !ARM_CPU_IS_ANY (allowed_arches) + && (cp_num == 8 || cp_num == 14 || cp_num == 15)) + continue; + } else if (insn->value == 0x0e000000 /* cdp */ || insn->value == 0xfe000000 /* cdp2 */ --------------A4350442ED12A272F560A328--