From: Jan Beulich <jbeulich@suse.com>
To: "Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "H.J. Lu" <hjl.tools@gmail.com>, "Cui, Lili" <lili.cui@intel.com>,
Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 6/6] x86: optimize {,V}PEXTR{D,Q} with immediate of 0
Date: Mon, 17 Jun 2024 10:56:29 +0200 [thread overview]
Message-ID: <eae404b6-6736-4301-abc5-cb1dc4a0fb10@suse.com> (raw)
In-Reply-To: <SA1PR11MB594696E38686CE943FE8BDC7ECCD2@SA1PR11MB5946.namprd11.prod.outlook.com>
On 17.06.2024 08:49, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Friday, June 14, 2024 8:15 PM
>> To: Binutils <binutils@sourceware.org>
>> Cc: H.J. Lu <hjl.tools@gmail.com>; Cui, Lili <lili.cui@intel.com>
>> Subject: [PATCH 6/6] x86: optimize {,V}PEXTR{D,Q} with immediate of 0
>>
>> Such are equivalent to simple moves, which are up to 3 bytes shorter to
>> encode (and perhaps also cheaper to execute).
>>
>
> The optimization is problematic. Instead of movd/q, we should optimize to
> psrldq, which has lower latency and it is exactly what GCC is doing for 0,1,2,3
> in immediate.
>
> psrldq has only 1 latency, while movd has 3 latency.
Wait. While the compiler may use PSRLDQ here, based on knowing assumptions
made elsewhere, the assembler can't: The replacement insn must generate the
exact same result in the destination register. PSRLDQ with an immediate of
0 (which effectively you're suggesting to use here) doesn't alter the
destination register at all, though. When really we want the upper bits of
the register cleared.
By implication I question the use of PSRLDQ (should it really happen) when
the immediate is 0: If the upper bits are of no interest, a yet simpler
MOVDQ{A,U} could then be used. Or, if source and destination match, no insn
would need emitting at all.
> Also, I suppose the optimization related to latency should not be done in
> assembler.
Why? We have -O, -O1, and -O2 alongside -Os for a reason.
Jan
next prev parent reply other threads:[~2024-06-17 8:56 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-14 12:10 [PATCH 0/6] x86: a few more optimizations Jan Beulich
2024-06-14 12:12 ` [PATCH 1/6] x86: optimize left-shift-by-1 Jan Beulich
2024-06-17 2:56 ` Jiang, Haochen
2024-06-17 8:40 ` Jan Beulich
2024-06-14 12:12 ` [PATCH 2/6] x86/APX: optimize {nf} forms of ADD/SUB with immediate of 0x80 Jan Beulich
2024-06-14 12:13 ` [PATCH 3/6] x86/APX: optimize {nf}-form rotate-by-width-less-1 Jan Beulich
2024-06-14 12:13 ` [PATCH 4/6] x86/APX: optimize certain {nf}-form insns to LEA Jan Beulich
2024-06-14 12:14 ` [PATCH 5/6] x86/APX: optimize certain {nf}-form insns to BMI2 ones Jan Beulich
2024-06-17 6:36 ` Jiang, Haochen
2024-06-14 12:14 ` [PATCH 6/6] x86: optimize {,V}PEXTR{D,Q} with immediate of 0 Jan Beulich
2024-06-17 6:49 ` Jiang, Haochen
2024-06-17 8:56 ` Jan Beulich [this message]
2024-06-18 3:25 ` Jiang, Haochen
2024-06-18 6:14 ` Jan Beulich
2024-06-18 6:23 ` Jiang, Haochen
2024-06-18 20:37 ` H.J. Lu
2024-06-19 2:01 ` Jiang, Haochen
2024-06-17 2:51 ` [PATCH 0/6] x86: a few more optimizations Jiang, Haochen
2024-06-17 8:33 ` Jan Beulich
2024-06-17 8:09 ` Cui, Lili
2024-06-17 8:37 ` Jan Beulich
2024-06-17 9:12 ` Cui, Lili
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