From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 5EED0384B0EE for ; Sat, 9 Jul 2022 09:10:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5EED0384B0EE Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id A932D300089; Sat, 9 Jul 2022 09:10:11 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 5/5] RISC-V: Make alias instructions aliases Date: Sat, 9 Jul 2022 18:09:14 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jul 2022 09:10:14 -0000 This commit makes following alias instruction real aliases. - scall - fmv.x.s - fmv.s.x opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Make alias instructions aliases. --- opcodes/riscv-opc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index c71e59d6e8a..80ce8e6c8b6 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -429,7 +429,7 @@ const struct riscv_opcode riscv_opcodes[] = {"rdinstreth", 32, INSN_CLASS_I, "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, {"rdtimeh", 32, INSN_CLASS_I, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, {"ecall", 0, INSN_CLASS_I, "", MATCH_ECALL, MASK_ECALL, match_opcode, 0 }, -{"scall", 0, INSN_CLASS_I, "", MATCH_ECALL, MASK_ECALL, match_opcode, 0 }, +{"scall", 0, INSN_CLASS_I, "", MATCH_ECALL, MASK_ECALL, match_opcode, INSN_ALIAS }, {"xori", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, {"xor", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, {"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, @@ -664,8 +664,8 @@ const struct riscv_opcode riscv_opcodes[] = {"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, {"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, 0 }, {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, 0 }, -{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, 0 }, -{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, 0 }, +{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, INSN_ALIAS }, +{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, INSN_ALIAS }, {"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, -- 2.34.1