From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: binutils@sourceware.org
Subject: [PATCH, binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline
Date: Thu, 04 Apr 2019 13:38:00 -0000 [thread overview]
Message-ID: <ef0f5620-2a60-9aed-c6bc-ff18a8f0c3db@arm.com> (raw)
In-Reply-To: <cfedf9a3-8a0e-d9cd-3b65-683d00e83621@arm.com>
[-- Attachment #1: Type: text/plain, Size: 1092 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This patch adds the BFX and BFLX instructions.
Testing: Added new test for the valid and invalid instructions operands.
Testsuite shows no regression when run for arm-none-eabi targets.
Thanks
Sudi
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
(do_t_v8_1_branch): New switch cases for bfx and bflx.
(insns): New instruction for bfx and bflx.
* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
Arm register with r13 and r15 unpredictable.
(thumb32_opcodes): New instructions for bfx and bflx.
[-- Attachment #2: 7.patch --]
[-- Type: text/x-patch, Size: 5584 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 04bd9b0e612b2e88db275effeec2749a4ba3605f..c7c1a82a998ce08330e05f3f2b3e34e453b87b2c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10506,6 +10506,8 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
X(_bf, 0000, f040e001), \
+ X(_bfx, 0000, f060e001), \
+ X(_bflx, 0000, f070e001), \
X(_bic, 4380, ea200000), \
X(_bics, 4380, ea300000), \
X(_cmn, 42c0, eb100f00), \
@@ -13362,6 +13364,11 @@ do_t_branch_future (void)
}
break;
+ case T_MNEM_bfx:
+ case T_MNEM_bflx:
+ inst.instruction |= inst.operands[1].reg << 16;
+ break;
+
default: abort ();
}
}
@@ -21679,6 +21686,8 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_1m_main
toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
+ toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
+ toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
@@ -21711,7 +21720,6 @@ static const struct asm_opcode insns[] =
#undef ToC
#undef toC
#undef ToU
-#undef
\f
/* MD interface: bits in the object file. */
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..3ee7df81610c45f68aced3982cb04589104d6873
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline BF-exchange instructions
+#source: armv8_1-m-bf-exchange-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-bf-exchange-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..1033b71e6ea2ad7a6886ba1d45e34537ea650a04
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:6: Error: branch out of range or not a multiple of 2
+.*:7: Error: branch out of range or not a multiple of 2
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:11: Error: r15 not allowed here -- `bfx 2,PC'
+.*:12: Error: r13 not allowed here -- `bflx 2,SP'
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..ca06eaf3d4fa6cf692b78b0dee87c6c75a888f71
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ # OP0 : Unsigned, 5-bit, even
+ bfx 0, r3
+ bfx -2, r3
+ bflx 3, r3
+ bflx 32, r3
+ # OP1 : no SP or PC
+ bfx 2, PC
+ bflx 2, SP
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d
new file mode 100644
index 0000000000000000000000000000000000000000..e88bb941acd7ebe29867dba940a69992932e6ada
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d
@@ -0,0 +1,14 @@
+#name: Valid Armv8.1-M Mainline BF-exchange instructions
+#source: armv8_1-m-bf-exchange.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f265 e001 bfx 8, r5
+0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
+0[0-9a-f]+ <[^>]+> f173 e001 bflx 4, r3
+0[0-9a-f]+ <[^>]+> 460a mov r2, r1
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s
new file mode 100644
index 0000000000000000000000000000000000000000..e3d9dfcdc7a2f518a10c4e71568b32dc6694aaba
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s
@@ -0,0 +1,12 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bfx .LB1, r5
+ mov r1, r1
+ bflx .LB2, r3
+ mov r2, r1
+.LB1:
+ mov r3, r2
+.LB2:
+ mov r4, r2
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 966a4d4d92fa660b1754c4c703648ec008efcfb0..2929522fa359bd55305d50da84598a17813c2510 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2731,6 +2731,7 @@ static const struct opcode16 thumb_opcodes[] =
%<bitfield>W print bitfield*4 in decimal
%<bitfield>r print bitfield as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
+ %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
%<bitfield>c print bitfield as a condition code
%<bitfield>'c print specified char iff bitfield is all ones
@@ -2750,6 +2751,10 @@ static const struct opcode32 thumb32_opcodes[] =
/* Armv8.1-M Mainline instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
@@ -6057,6 +6062,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
value_in_comment = val * 4;
break;
+ case 'S':
+ if (val == 13)
+ is_unpredictable = TRUE;
+ /* Fall through. */
case 'R':
if (val == 15)
is_unpredictable = TRUE;
next prev parent reply other threads:[~2019-04-04 13:38 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support " Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, GAS, ARM, 2/16] Add CLI extension " Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI Andre Vieira (lists)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch Andre Vieira (lists)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct arm_it Andre Vieira (lists)
2019-04-04 13:36 ` [PATCH, binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 Andre Vieira (lists)
2019-04-04 13:37 ` [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-12 10:41 ` Andre Vieira (lists)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 Andre Vieira (lists)
2019-04-04 13:38 ` Andre Vieira (lists) [this message]
2019-04-04 13:39 ` [PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-12 10:40 ` Andre Vieira (lists)
2019-04-04 13:40 ` [PATCH, binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 Andre Vieira (lists)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-12 10:40 ` Andre Vieira (lists)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 11/16] New BFCSEL instruction " Andre Vieira (lists)
2019-04-12 10:39 ` Andre Vieira (lists)
2019-04-04 13:42 ` [PATCH, binutils, ARM, 13/16] Add support for CLRM Andre Vieira (lists)
2019-04-04 13:43 ` [PATCH, opcodes, ARM, 14/16] Add mode availability to coprocessor table entries Andre Vieira (lists)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 15/16] Add support for VSCCLRM Andre Vieira (lists)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers Andre Vieira (lists)
2019-04-11 10:04 ` [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Nick Clifton
2019-04-12 10:39 ` Andre Vieira (lists)
2019-04-12 13:51 ` Nick Clifton
2019-04-15 9:41 ` Andre Simoes Dias Vieira
2019-04-16 1:58 ` Alan Modra
2019-04-16 11:52 ` Andre Simoes Dias Vieira
2019-04-16 12:36 ` Alan Modra
2019-05-01 9:32 ` Andre Vieira (lists)
2019-05-02 1:21 ` Alan Modra
2019-05-15 15:34 ` Andre Vieira (lists)
2019-05-20 10:31 ` Nick Clifton
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