From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id E90E43835C08 for ; Sat, 27 Aug 2022 00:11:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E90E43835C08 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 374C3300089; Sat, 27 Aug 2022 00:11:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1661559091; bh=fyQ/p0vQHyrccvgHudq8BFrdeGoEyvU/6AKW0HqFWBk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=DiKdveBnC3ARgrbk4Y+CvOS5gdvGICBTqq/3PGkQnx+JVH5PkIf61fVLcvD+QLr2e Hkxp263qwslfRBw964zuwA9Z3dQKHTdeslZE0BlBfVNryqN/PRC7V+IUgg/svBx8mK kWeN3Oc+zcCk1U1d4mKAnGb43Nk9h97BejZEQj6A= From: Tsukasa OI To: Tsukasa OI , "H . Peter Anvin" , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v8 2/7] RISC-V: Fix JALR target address computation Date: Sat, 27 Aug 2022 00:10:59 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,KAM_MANYTO,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: H. Peter Anvin discovered that we have wrong address computation for JALR instruction (the initial bug is back in 2018). This commit will fix that based on the idea of Palmer Dabbelt. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix JALR address computation. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): --- opcodes/riscv-dis.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 164fd209dbd..4c03f113650 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -397,7 +397,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'b': case 's': if ((l & MASK_JALR) == MATCH_JALR) - maybe_print_address (pd, rs1, 0, 0); + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]); break; -- 2.34.1