From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 02AC63858437 for ; Wed, 2 Feb 2022 00:36:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 02AC63858437 Message-ID: Date: Wed, 2 Feb 2022 09:36:39 +0900 Mime-Version: 1.0 Subject: Re: [PATCH] RISC-V: Update Zihintpause extension version Content-Language: en-US To: Palmer Dabbelt Cc: binutils@sourceware.org References: From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Feb 2022 00:36:47 -0000 On 2022/02/02 9:12, Palmer Dabbelt wrote: > On Tue, 01 Feb 2022 05:46:56 PST (-0800), research_trasio@irq.a4lg.com wrote: >> Sorry for no background on the first submission.  Probably I will have >> to create cover letters even if the patch is very small. >> >> Yup, old 2.0 -> new 1.0 -> new 2.0. >> >> I list some RISC-V ISA Manual commits with author/committer dates: >> >> [Old 2.0 (initially proposed)] >> https://github.com/riscv/riscv-isa-manual/commit/ea9410a6a5ea2b7cabfbef1ed0bf3507bb784c36 (2019-08-26 / 2020-10-17) >> [New 1.0 (version number changed)] >> https://github.com/riscv/riscv-isa-manual/commit/773a6c4cc9db7585d42ec732d5db24f930d1157a (2020-10-09 / 2020-10-17) >> [New 1.0 (Ratified!?)] >> https://github.com/riscv/riscv-isa-manual/commit/d8ab5c78c207d7138684fc92cc8f34c463975620 (2021-08-02 / 2021-08-02) >> [New 2.0 (Ratified version corrected in a day)] >> https://github.com/riscv/riscv-isa-manual/commit/7a58119dad5bd43e2171a26b56ef60f9591a1c9c (2021-08-02 / 2021-08-02) >> >> Latest draft still says that ratified version is "2.0": >> https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220125-23a1255 >> >> On 2022/02/01 11:20, Andrew Waterman wrote: >>> On Mon, Jan 31, 2022 at 8:45 AM Palmer Dabbelt wrote: >>>> >>>> On Sun, 30 Jan 2022 03:37:41 PST (-0800), binutils@sourceware.org wrote: >>>>> Because ratified Zihintpause extension has a version number of 2.0 >>>>> (not 1.0), we should update the number. >>>> >>>> The ISA manual also says it's ratified so having it in the draft set is >>>> kind of odd, but I'm not sure which spec version it should be included >>>> in.  The commits saying it was ratified are in August 2021, but I can't >>>> find a spec version that's listed as ratified and contains the new 2.0 >>>> (there was also an earlier 2.0, from before the 1.0). >>>> >>>> Not sure if this matters, though.  Looks like the only non-commentary >>>> differents are: from the original 2.0 to 1.0, the text "No architectural >>>> state is changed." was added; and from 1.0 to 2.0 the text "{\em fm}=0, >>>> {\em rd}={\tt x0}, and {\em rs1}={\tt x0}" was added (to the encoding >>>> section).  The second one isn't substantive, and while the first one >>>> reads like a change to me IIRC we've been through that before and I just >>>> have the definition of architectural state change wrong. >>> >>> The first one isn't substantive, either, because of the definition of >>> HINT.  It's just a clarification. >> >> Although that version change is not substantive, this version > > OK, sorry, I guess I'm just confused here.  No big deal, though -- if they're the same that's all that matters, I don't really care about the why part. > >> number is copied to RISC-V attributes section >> (e.g. with -march=rv32gc_zihintpause) so I thought it would be better to >> be an actual ratified version. >> >> (Before the patch) >> Contents of section .riscv.attributes: >>  0000 415a0000 00726973 63760001 50000000  AZ...riscv..P... >>  0010 05727633 32693270 315f6d32 70305f61  .rv32i2p1_m2p0_a >>  0020 3270315f 66327032 5f643270 325f6332  2p1_f2p2_d2p2_c2 >>  0030 70305f7a 69637372 3270305f 7a696665  p0_zicsr2p0_zife >>  0040 6e636569 3270305f 7a696869 6e747061  ncei2p0_zihintpa >>  0050 75736531 70300008 010a0b             use1p0..... >> >> (After the patch [offset 0x53 is changed]) >> Contents of section .riscv.attributes: >>  0000 415a0000 00726973 63760001 50000000  AZ...riscv..P... >>  0010 05727633 32693270 315f6d32 70305f61  .rv32i2p1_m2p0_a >>  0020 3270315f 66327032 5f643270 325f6332  2p1_f2p2_d2p2_c2 >>  0030 70305f7a 69637372 3270305f 7a696665  p0_zicsr2p0_zife >>  0040 6e636569 3270305f 7a696869 6e747061  ncei2p0_zihintpa >>  0050 75736532 70300008 010a0b             use2p0..... > > Works for me, and given that there's no difference between the three I don't see any reason to worry about the spec versioning. > > Looks like the copyright assignment might still be in limbo (I left my FSF keys at home, so I can't check right now), we can probably call this one trivial but I don't see any particular rush and given that a lot of your other patch sets are defiantly not trivial that has to get sorted out anyway. As I mentioned in my latest (and big) Zfinx patch set (Part 1), my copyright assignment to FSF is completed. I didn't detailed it in the e-mail above but... it's completed in 2022-01-20 [gnu.org #1788718]. I agree that we don't have to rush about it. As long as patches are reviewed properly, that's fine. Still, I hope that my Zfinx patchsets are sorted out in February so that we can implement Zfh/Zfhmin on the tree with my Zfinx patchsets either accepted, rejected or postponed. Thanks, Tsukasa > > Thanks! > >> >> Thanks, >> Tsukasa >> >>> >>>> >>>>> >>>>> bfd/ChangeLog: >>>>> >>>>>       * elfxx-riscv.c (riscv_supported_std_z_ext): Update version >>>>>       number of Zihintpause extension. >>>>> --- >>>>>  bfd/elfxx-riscv.c | 2 +- >>>>>  1 file changed, 1 insertion(+), 1 deletion(-) >>>>> >>>>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c >>>>> index 9f52bb545ac..29755a6cb0a 100644 >>>>> --- a/bfd/elfxx-riscv.c >>>>> +++ b/bfd/elfxx-riscv.c >>>>> @@ -1183,7 +1183,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = >>>>>    {"zicsr",          ISA_SPEC_CLASS_20190608,        2, 0,  0 }, >>>>>    {"zifencei",               ISA_SPEC_CLASS_20191213,        2, 0,  0 }, >>>>>    {"zifencei",               ISA_SPEC_CLASS_20190608,        2, 0,  0 }, >>>>> -  {"zihintpause",    ISA_SPEC_CLASS_DRAFT,           1, 0,  0 }, >>>>> +  {"zihintpause",    ISA_SPEC_CLASS_DRAFT,           2, 0,  0 }, >>>>>    {"zfinx",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 }, >>>>>    {"zdinx",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 }, >>>>>    {"zqinx",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 }, >>>>> >>>>> base-commit: 35b5767cf47169d11aa059fce0ed5b0fc213045d >>> >