Re: [PATCH] LoongArch: gas: Add LVZ and LBT instructions support

[WANG Xuerui <i.swmail@xen0n.name>]

Hi,

On 2023/6/29 20:29, Chenghua Xu wrote:
> 
> WANG Xuerui writes:
> 
>> On 2023/6/29 17:08, mengqinggang wrote:
>>> gas/ChangeLog:
>>> 	* testsuite/gas/loongarch/uleb128.d: Regenerated.
>>> 	* testsuite/gas/loongarch/lvz-lbt.d: New test.
>>> 	* testsuite/gas/loongarch/lvz-lbt.s: New test.
>>> opcodes/ChangeLog:
>>> 	* loongarch-opc.c (struct loongarch_ase): Add LVZ and LBT
>>> instructions.
>>> ---
>>>    gas/testsuite/gas/loongarch/lvz-lbt.d | 196 ++++++++++++++++++++++++
>>>    gas/testsuite/gas/loongarch/lvz-lbt.s | 186 +++++++++++++++++++++++
>>>    gas/testsuite/gas/loongarch/uleb128.d |  52 +++----
>>>    opcodes/loongarch-opc.c               | 205 +++++++++++++++++++++++++-
>>>    4 files changed, 611 insertions(+), 28 deletions(-)
>>>    create mode 100644 gas/testsuite/gas/loongarch/lvz-lbt.d
>>>    create mode 100644 gas/testsuite/gas/loongarch/lvz-lbt.s
>>> [snip]
>>>
>>> diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
>>> index bd104465ca7..202614390db 100644
>>> --- a/opcodes/loongarch-opc.c
>>> +++ b/opcodes/loongarch-opc.c
>>> @@ -1646,6 +1646,7 @@ static struct loongarch_opcode loongarch_lsx_opcodes[] =
>>>      { 0x73e40000, 0xfffc0000, "vpermi.w", "v0:5,v5:5,u10:8", 0, 0, 0, 0},
>>>      { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list.  */
>>>    };
>>> +
>>>    static struct loongarch_opcode loongarch_lasx_opcodes[] =
>>>    {
>>>    /* match,    mask,       name, format, macro, include, exclude, pinfo.  */
>>> @@ -2321,6 +2322,204 @@ static struct loongarch_opcode loongarch_lasx_opcodes[] =
>>>      { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list.  */
>>>    };
>>>    +static struct loongarch_opcode loongarch_lvz_opcodes[] =
>>> +{
>>> +  /* match,    mask,       name,     format, macro, include, exclude, pinfo.  */
>>> +  {0x05000000, 0xff0003e0, "gcsrrd", "r0:5,u10:14", 0, 0, 0, 0},
>>> +  {0x05000020, 0xff0003e0, "gcsrwr", "r0:5,u10:14", 0, 0, 0, 0},
>>> +  {0x05000000, 0xff000000, "gcsrxchg", "r0:5,r5:5,u10:14", 0, 0, 0, 0},
>>> +  {0x06482801, 0xffffffff, "gtlbsrch", "", 0, 0, 0, 0},
>>> +  {0x06482c01, 0xffffffff, "gtlbrd", "", 0, 0, 0, 0},
>>> +  {0x06483001, 0xffffffff, "gtlbwr", "", 0, 0, 0, 0},
>>> +  {0x06483401, 0xffffffff, "gtlbfill", "", 0, 0, 0, 0},
>>> +  {0x06482001, 0xffffffff, "gtlbclr", "", 0, 0, 0, 0},
>>> +  {0x06482401, 0xffffffff, "gtlbflush", "", 0, 0, 0, 0},
>>> +  {0x002b8000, 0xffff8000, "hvcl", "u0:15", 0, 0, 0, 0},
>>> +  { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list.  */
>>> +};
>>> +
>>> +static struct loongarch_opcode loongarch_lbt_opcodes[] =
>>> +{
>>> +  /* match,    mask,       name,     format, macro, include, exclude, pinfo.  */
>>> +  {0x00000800, 0xfffffc1c, "gr2scr", "cr0:2,r5:5", 0, 0, 0, 0},
>>> +  {0x00000c00, 0xffffff80, "scr2gr", "r0:5,cr5:2", 0, 0, 0, 0},
>>
>> Hmm why aren't this couple of instructions named "movgr2scr" and
>> "movscr2gr", like other similar ones? I remember suggesting this a
>> while ago (in the now-deleted loongson/linux GitHub repo) but seems
>> the suggestion wasn't taken.
> 
> Thanks for catch this, movgr2src/movscr2gr are fine.

Thank you for the quick response! I've just gone through the list again, 
very carefully, since spotting that point, while working on 
loongarch-opcodes, and I've discovered some more potentially confusing 
places which I've replied to in a new mail.

It could be beneficial to all devs developing for LoongArch if we could 
sort out these too -- compatibility is always possible anyway and we'll 
not surprise users if we do.