* [PATCH 0/4] RISC-V/gas: assorted adjustments
@ 2022-09-30 11:57 Jan Beulich
2022-09-30 11:59 ` [PATCH 1/4] RISC-V/gas: drop riscv_subsets static variable Jan Beulich
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Jan Beulich @ 2022-09-30 11:57 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu
Really the first three were noticed while looking around how to best
put together the last one.
1: drop riscv_subsets static variable
2: drop stray call to install_insn()
3: don't open-code insn_length()
4: allow generating up to 176-bit instructions with .insn
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] RISC-V/gas: drop riscv_subsets static variable
2022-09-30 11:57 [PATCH 0/4] RISC-V/gas: assorted adjustments Jan Beulich
@ 2022-09-30 11:59 ` Jan Beulich
2022-09-30 11:59 ` [PATCH 2/4] RISC-V/gas: drop stray call to install_insn() Jan Beulich
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2022-09-30 11:59 UTC (permalink / raw)
To: Binutils
It's fully redundant with the subset_list member of riscv_rps_as.
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -265,11 +265,10 @@ riscv_set_tso (void)
elf_flags |= EF_RISCV_TSO;
}
-/* This linked list records all enabled extensions, which are parsed from
- the architecture string. The architecture string can be set by the
- -march option, the elf architecture attributes, and the --with-arch
- configure option. */
-static riscv_subset_list_t *riscv_subsets = NULL;
+/* The linked list hanging off of .subsets_list records all enabled extensions,
+ which are parsed from the architecture string. The architecture string can
+ be set by the -march option, the elf architecture attributes, and the
+ --with-arch configure option. */
static riscv_parse_subset_t riscv_rps_as =
{
NULL, /* subset_list, we will set it later once
@@ -302,14 +301,13 @@ riscv_set_arch (const char *s)
return;
}
- if (riscv_subsets == NULL)
+ if (riscv_rps_as.subset_list == NULL)
{
- riscv_subsets = XNEW (riscv_subset_list_t);
- riscv_subsets->head = NULL;
- riscv_subsets->tail = NULL;
- riscv_rps_as.subset_list = riscv_subsets;
+ riscv_rps_as.subset_list = XNEW (riscv_subset_list_t);
+ riscv_rps_as.subset_list->head = NULL;
+ riscv_rps_as.subset_list->tail = NULL;
}
- riscv_release_subset_list (riscv_subsets);
+ riscv_release_subset_list (riscv_rps_as.subset_list);
riscv_parse_subset (&riscv_rps_as, s);
riscv_set_rvc (false);
@@ -3986,10 +3984,9 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
s = XNEW (struct riscv_option_stack);
s->next = riscv_opts_stack;
s->options = riscv_opts;
- s->subset_list = riscv_subsets;
+ s->subset_list = riscv_rps_as.subset_list;
riscv_opts_stack = s;
- riscv_subsets = riscv_copy_subset_list (s->subset_list);
- riscv_rps_as.subset_list = riscv_subsets;
+ riscv_rps_as.subset_list = riscv_copy_subset_list (s->subset_list);
}
else if (strcmp (name, "pop") == 0)
{
@@ -4000,11 +3997,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
as_bad (_(".option pop with no .option push"));
else
{
- riscv_subset_list_t *release_subsets = riscv_subsets;
+ riscv_subset_list_t *release_subsets = riscv_rps_as.subset_list;
riscv_opts_stack = s->next;
riscv_opts = s->options;
- riscv_subsets = s->subset_list;
- riscv_rps_as.subset_list = riscv_subsets;
+ riscv_rps_as.subset_list = s->subset_list;
riscv_release_subset_list (release_subsets);
free (s);
}
@@ -4502,7 +4498,7 @@ riscv_write_out_attrs (void)
unsigned int i;
/* Re-write architecture elf attribute. */
- arch_str = riscv_arch_str (xlen, riscv_subsets);
+ arch_str = riscv_arch_str (xlen, riscv_rps_as.subset_list);
bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
xfree ((void *) arch_str);
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/4] RISC-V/gas: drop stray call to install_insn()
2022-09-30 11:57 [PATCH 0/4] RISC-V/gas: assorted adjustments Jan Beulich
2022-09-30 11:59 ` [PATCH 1/4] RISC-V/gas: drop riscv_subsets static variable Jan Beulich
@ 2022-09-30 11:59 ` Jan Beulich
2022-09-30 11:59 ` [PATCH 3/4] RISC-V/gas: don't open-code insn_length() Jan Beulich
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2022-09-30 11:59 UTC (permalink / raw)
To: Binutils
add_fixed_insn(), by calling move_insn(), already invokes install_insn().
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1476,7 +1476,6 @@ append_insn (struct riscv_cl_insn *ip, e
}
add_fixed_insn (ip);
- install_insn (ip);
/* We need to start a new frag after any instruction that can be
optimized away or compressed by the linker during relaxation, to prevent
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] RISC-V/gas: don't open-code insn_length()
2022-09-30 11:57 [PATCH 0/4] RISC-V/gas: assorted adjustments Jan Beulich
2022-09-30 11:59 ` [PATCH 1/4] RISC-V/gas: drop riscv_subsets static variable Jan Beulich
2022-09-30 11:59 ` [PATCH 2/4] RISC-V/gas: drop stray call to install_insn() Jan Beulich
@ 2022-09-30 11:59 ` Jan Beulich
2022-09-30 12:00 ` [PATCH 4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn Jan Beulich
2022-09-30 14:39 ` [PATCH 0/4] RISC-V/gas: assorted adjustments Nelson Chu
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2022-09-30 11:59 UTC (permalink / raw)
To: Binutils
Use the helper when it can be used.
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1445,7 +1445,7 @@ append_insn (struct riscv_cl_insn *ip, e
|| reloc_type == BFD_RELOC_RISCV_JMP)
{
int j = reloc_type == BFD_RELOC_RISCV_JMP;
- int best_case = riscv_insn_length (ip->insn_opcode);
+ int best_case = insn_length (ip);
unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
if (now_seg == absolute_section)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn
2022-09-30 11:57 [PATCH 0/4] RISC-V/gas: assorted adjustments Jan Beulich
` (2 preceding siblings ...)
2022-09-30 11:59 ` [PATCH 3/4] RISC-V/gas: don't open-code insn_length() Jan Beulich
@ 2022-09-30 12:00 ` Jan Beulich
2022-09-30 14:39 ` [PATCH 0/4] RISC-V/gas: assorted adjustments Nelson Chu
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2022-09-30 12:00 UTC (permalink / raw)
To: Binutils
For the time being simply utilize O_big to avoid widening other fields,
bypassing append_insn() etc.
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3389,8 +3389,15 @@ riscv_ip_hardcode (char *str,
do
{
expression (imm_expr);
- if (imm_expr->X_op != O_constant)
+ switch (imm_expr->X_op)
{
+ case O_constant:
+ values[num++] = (insn_t) imm_expr->X_add_number;
+ break;
+ case O_big:
+ values[num++] = generic_bignum[0];
+ break;
+ default:
/* The first value isn't constant, so it should be
.insn <type> <operands>. We have been parsed it
in the riscv_ip. */
@@ -3398,9 +3405,8 @@ riscv_ip_hardcode (char *str,
return error;
return _("values must be constant");
}
- values[num++] = (insn_t) imm_expr->X_add_number;
}
- while (*input_line_pointer++ == ',' && num < 2);
+ while (*input_line_pointer++ == ',' && num < 2 && imm_expr->X_op != O_big);
input_line_pointer--;
if (*input_line_pointer != '\0')
@@ -3410,8 +3416,22 @@ riscv_ip_hardcode (char *str,
insn->match = values[num - 1];
create_insn (ip, insn);
unsigned int bytes = riscv_insn_length (insn->match);
- if ((bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0)
- || (num == 2 && values[0] != bytes))
+
+ if (num == 2 && values[0] != bytes)
+ return _("value conflicts with instruction length");
+
+ if (imm_expr->X_op == O_big)
+ {
+ if (bytes != imm_expr->X_add_number * CHARS_PER_LITTLENUM)
+ return _("value conflicts with instruction length");
+ char *f = frag_more (bytes);
+ for (num = 0; num < imm_expr->X_add_number; ++num)
+ number_to_chars_littleendian (f + num * CHARS_PER_LITTLENUM,
+ generic_bignum[num], CHARS_PER_LITTLENUM);
+ return NULL;
+ }
+
+ if (bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0)
return _("value conflicts with instruction length");
return NULL;
@@ -4473,7 +4493,7 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
else
as_bad ("%s `%s'", error.msg, error.statement);
}
- else
+ else if (imm_expr.X_op != O_big)
{
gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
append_insn (&insn, &imm_expr, imm_reloc);
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -37,6 +37,9 @@ static inline unsigned int riscv_insn_le
return 6;
if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */
return 8;
+ /* 80- ... 176-bit instructions. */
+ if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000)
+ return 10 + ((insn >> 11) & 0xe);
/* Longer instructions not supported at the moment. */
return 2;
}
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -74,7 +74,21 @@ Disassembly of section .text:
[^:]+:[ ]+00000013[ ]+nop
[^:]+:[ ]+001f 0000 0000[ ].*
[^:]+:[ ]+0000003f 00000000[ ].*
+[^:]+:[ ]+007f 0000 0000 0000[ ]+[._a-z].*
+[^:]+:[ ]+0000 ?
+[^:]+:[ ]+0000107f 00000000[ ]+[._a-z].*
+[^:]+:[ ]+00000000 ?
+[^:]+:[ ]+607f 0000 0000 0000[ ]+[._a-z].*
+[^:]+:[ ]+0000 0000 0000 0000 ?
+[^:]+:[ ]+0000 0000 0000 ?
[^:]+:[ ]+0001[ ]+nop
[^:]+:[ ]+00000013[ ]+nop
[^:]+:[ ]+001f 0000 0000[ ].*
[^:]+:[ ]+0000003f 00000000[ ].*
+[^:]+:[ ]+007f 0000 0000 0000[ ]+[._a-z].*
+[^:]+:[ ]+0000 ?
+[^:]+:[ ]+0000107f 00000000[ ]+[._a-z].*
+[^:]+:[ ]+00000000 ?
+[^:]+:[ ]+607f 0000 0000 0000[ ]+[._a-z].*
+[^:]+:[ ]+0000 0000 0000 0000 ?
+[^:]+:[ ]+0000 0000 0000 ?
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -60,7 +60,13 @@ target:
.insn 0x00000013
.insn 0x0000001f
.insn 0x0000003f
+ .insn 0x007f
+ .insn 0x107f
+ .insn 0x607f
.insn 0x2, 0x0001
.insn 0x4, 0x00000013
.insn 6, 0x0000001f
.insn 8, 0x0000003f
+ .insn 10, 0x007f
+ .insn 12, 0x107f
+ .insn 22, 0x607f
--- a/gas/testsuite/gas/riscv/insn-dwarf.d
+++ b/gas/testsuite/gas/riscv/insn-dwarf.d
@@ -65,8 +65,14 @@ insn.s +60 +0xac.*
insn.s +61 +0xb0.*
insn.s +62 +0xb6.*
insn.s +63 +0xbe.*
-insn.s +64 +0xc0.*
-insn.s +65 +0xc4.*
-insn.s +66 +0xca.*
-insn.s +- +0xd2
+insn.s +64 +0xc8.*
+insn.s +65 +0xd4.*
+insn.s +66 +0xea.*
+insn.s +67 +0xec.*
+insn.s +68 +0xf0.*
+insn.s +69 +0xf6.*
+insn.s +70 +0xfe.*
+insn.s +71 +0x108.*
+insn.s +72 +0x114.*
+insn.s +- +0x12a
#pass
--- a/gas/testsuite/gas/riscv/insn-fail.l
+++ b/gas/testsuite/gas/riscv/insn-fail.l
@@ -5,3 +5,13 @@
.*Error: unrecognized values `0x4,0x5,0x6'
.*Error: value conflicts with instruction length `0x4,0x0001'
.*Error: value conflicts with instruction length `0x2,0x00000013'
+.*Error: value conflicts with instruction length `0x10+1f'
+.*Error: value conflicts with instruction length `6,0x10+1f'
+.*Error: value conflicts with instruction length `0x10+3f'
+.*Error: value conflicts with instruction length `8,0x10+3f'
+.*Error: value conflicts with instruction length `0x10+7f'
+.*Error: value conflicts with instruction length `10,0x10+7f'
+.*Error: value conflicts with instruction length `0x10+107f'
+.*Error: value conflicts with instruction length `12,0x10+107f'
+.*Error: value conflicts with instruction length `0x10+607f'
+.*Error: value conflicts with instruction length `22,0x10+607f'
--- a/gas/testsuite/gas/riscv/insn-fail.s
+++ b/gas/testsuite/gas/riscv/insn-fail.s
@@ -4,3 +4,13 @@
.insn 0x4, 0x5, 0x6
.insn 0x4, 0x0001
.insn 0x2, 0x00000013
+ .insn 0x100000000001f
+ .insn 6, 0x100000000001f
+ .insn 0x1000000000000003f
+ .insn 8, 0x1000000000000003f
+ .insn 0x10000000000000000007f
+ .insn 10, 0x10000000000000000007f
+ .insn 0x100000000000000000000107f
+ .insn 12, 0x100000000000000000000107f
+ .insn 0x10000000000000000000000000000000000000000607f
+ .insn 22, 0x10000000000000000000000000000000000000000607f
--- a/gas/testsuite/gas/riscv/insn-na.d
+++ b/gas/testsuite/gas/riscv/insn-na.d
@@ -63,7 +63,13 @@ Disassembly of section .text:
[^:]+:[ ]+00000013[ ]+addi[ ]+zero,zero,0
[^:]+:[ ]+001f 0000 0000[ ].*
[^:]+:[ ]+0000003f 00000000[ ].*
+[^:]+:[ ]+007f 0000 0000 0000 0000[ ]+[._a-z].*
+[^:]+:[ ]+0000107f 00000000 00000000[ ]+[._a-z].*
+[^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+[._a-z].*
[^:]+:[ ]+0001[ ]+c\.addi[ ]+zero,0
[^:]+:[ ]+00000013[ ]+addi[ ]+zero,zero,0
[^:]+:[ ]+001f 0000 0000[ ].*
[^:]+:[ ]+0000003f 00000000[ ].*
+[^:]+:[ ]+007f 0000 0000 0000 0000[ ]+[._a-z].*
+[^:]+:[ ]+0000107f 00000000 00000000[ ]+[._a-z].*
+[^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+[._a-z].*
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/4] RISC-V/gas: assorted adjustments
2022-09-30 11:57 [PATCH 0/4] RISC-V/gas: assorted adjustments Jan Beulich
` (3 preceding siblings ...)
2022-09-30 12:00 ` [PATCH 4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn Jan Beulich
@ 2022-09-30 14:39 ` Nelson Chu
4 siblings, 0 replies; 6+ messages in thread
From: Nelson Chu @ 2022-09-30 14:39 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson
On Fri, Sep 30, 2022 at 7:57 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> Really the first three were noticed while looking around how to best
> put together the last one.
>
> 1: drop riscv_subsets static variable
> 2: drop stray call to install_insn()
> 3: don't open-code insn_length()
> 4: allow generating up to 176-bit instructions with .insn
Looks good and reasonable, please commit, thank you.
Nelson
> Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-09-30 14:39 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2022-09-30 11:57 [PATCH 0/4] RISC-V/gas: assorted adjustments Jan Beulich
2022-09-30 11:59 ` [PATCH 1/4] RISC-V/gas: drop riscv_subsets static variable Jan Beulich
2022-09-30 11:59 ` [PATCH 2/4] RISC-V/gas: drop stray call to install_insn() Jan Beulich
2022-09-30 11:59 ` [PATCH 3/4] RISC-V/gas: don't open-code insn_length() Jan Beulich
2022-09-30 12:00 ` [PATCH 4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn Jan Beulich
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