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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Nelson Chu <nelson@rivosinc.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	binutils@sourceware.org
Subject: Re: [RFC PATCH 1/1] RISC-V: Add privileged extensions without instructions/CSRs
Date: Thu, 22 Sep 2022 18:44:43 +0900	[thread overview]
Message-ID: <f74bc023-0447-4034-5e89-518f2edca31e@irq.a4lg.com> (raw)
In-Reply-To: <CAPpQWtDAzB=_H1k895aFotZVwO0vKJ0-9t5pnfYeEYJ6CopwGg@mail.gmail.com>

On 2022/09/22 17:48, Nelson Chu wrote:
> On Thu, Sep 22, 2022 at 3:59 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>>
>> Currently, GNU Binutils does not support following privileged extensions:
>>
>> -   'Smepmp'
>> -   'Svnapot'
>> -   'Svpbmt'
>>
>> as they do not provide new CSRs or new instructions ('Smepmp' extends the
>> privileged architecture CSRs but does not define the CSR itself).  However,
>> adding them might be useful as we no longer have to "filter" ISA strings
>> just for toolchains (if full ISA string is given by a vendor, we can
>> straightly use it).
> 
> OKay.
> 
> Nelson

Understood.  I'm going to push this patch in a week if there's no other
comments.  But until then, I'll wait for other opinions.

Thanks,
Tsukasa

> 
>> And there's a fact that supports this theory: there's already an
>> (unprivileged) extension which does not provide CSRs or instructions (but
>> only an architectural guarantee): 'Zkt' (constant timing guarantee for
>> certain subset of RISC-V instructions).
>>
>> This simple patchset simply adds three privileged extensions listed above.
>>
>> bfd/ChangeLog:
>>
>>         * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smepmp',
>>         'Svnapot' and 'Svpbmt' extensions.
>> ---
>>  bfd/elfxx-riscv.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index 7eda177bd6e..bbc30c9afc2 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1210,10 +1210,13 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
>>
>>  static struct riscv_supported_ext riscv_supported_std_s_ext[] =
>>  {
>> +  {"smepmp",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>>    {"smstateen",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>>    {"sscofpmf",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>>    {"sstc",             ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>>    {"svinval",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>> +  {"svnapot",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>> +  {"svpbmt",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>>    {NULL, 0, 0, 0, 0}
>>  };
>>
>> --
>> 2.34.1
>>
> 

  reply	other threads:[~2022-09-22  9:44 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-22  7:58 [RFC PATCH 0/1] " Tsukasa OI
2022-09-22  7:58 ` [RFC PATCH 1/1] " Tsukasa OI
2022-09-22  8:48   ` Nelson Chu
2022-09-22  9:44     ` Tsukasa OI [this message]
2022-09-30 15:44       ` Tsukasa OI

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