[PATCH][Binutils][AArch64] Fix cfinv disassembly issues

[PATCH][Binutils][AArch64] Fix cfinv disassembly issues

[Tamar Christina]

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Hi All,

This fixes the preferred disassembly for cfinv.  The Armv8.4-a instruction
overlaps with the possible encoding space for msr.  This because msr allows you
to use unallocated encoding space using the general sA_B_cC_cD_E form.

However when an encoding does become allocated then we need to ensure that it's
used as the preferred disassembly.  The problem with cfinv is that its mask has
all bits sets because it has no arguments.

This causes issues for the Alias resolver in gas as it uses the mask to build
alias graph.  In this case it can't do it since it thinks almost everything
would alias with cfinv.  So instead we can only fix this by moving cfinv before
msr.

NOTE: I have omitted the regenerated file for ease of review.

build on native hardware and regtested on
  aarch64-none-elf, aarch64-none-elf (32 bit host),
  aarch64-none-linux-gnu, aarch64-none-linux-gnu (32 bit host)

Cross-compiled and regtested on
  aarch64-none-linux-gnu, aarch64_be-none-linux-gnu

and no issues.

Ok for master? and for backport to binutils-2.33 branch and to 2.34 once branch is open?

Thanks,
Tamar

gas/ChangeLog:

2020-01-22  Tamar Christina  <tamar.christina@arm.com>

	PR 25403
	* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
	* testsuite/gas/aarch64/armv8_4-a.s: Likewise.

opcodes/ChangeLog:

2020-01-22  Tamar Christina  <tamar.christina@arm.com>

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.

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diff --git a/gas/testsuite/gas/aarch64/armv8_4-a.d b/gas/testsuite/gas/aarch64/armv8_4-a.d
index 5b67c6e44e5de438b5ab624ffe3ec6bf03d0546c..4b1a4e37757b63755903b61b2ef3e194ffd54994 100644
--- a/gas/testsuite/gas/aarch64/armv8_4-a.d
+++ b/gas/testsuite/gas/aarch64/armv8_4-a.d
@@ -2202,3 +2202,4 @@ Disassembly of section \.text:
 [^:]+:\s+998033fe 	ldapursw	x30, \[sp, #3\]
 [^:]+:\s+998523fe 	ldapursw	x30, \[sp, #82\]
 [^:]+:\s+9980d3fe 	ldapursw	x30, \[sp, #13\]
+[^:]+:\s+d500401f 	cfinv
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/armv8_4-a.s b/gas/testsuite/gas/aarch64/armv8_4-a.s
index 45f7ea8a599f31d2268489ab0cf235630e835618..b270d189eccf43b0d8d7e025b416f92e0d062c69 100644
--- a/gas/testsuite/gas/aarch64/armv8_4-a.s
+++ b/gas/testsuite/gas/aarch64/armv8_4-a.s
@@ -144,3 +144,6 @@ func:
 	gen1reg_iter ldapursw x,", [sp]"
 	gen3reg_iter ldapursw x,, [x,,,]
 	gen2reg_iter_offset ldapursw x,,sp
+
+	cfinv
+
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 48872e4c373bbcf344b3dc34bec20872b5972e58..2a9941267312bc5541cfc144f8a866856fd358c4 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3866,6 +3866,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
   PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
+  /* Armv8.4-a flag setting instruction, However this encoding has an encoding clash with the msr
+     below it.  Usually we can resolve this by setting an alias condition on the flags, however that
+     depends on the disassembly masks to be able to quickly find the alias.  The problem is the
+     cfinv instruction has no arguments, so all bits are set in the mask.  Which means it will
+     potentially alias with too many instructions and so the tree can't be constructed.   As a work
+     around we just place cfinv before msr.  This means the order between these two shouldn't be
+     changed.  */
+  V8_4_INSN ("cfinv",  0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
   CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
   CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
   CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
@@ -5043,7 +5051,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
   FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
   FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
   /* System extensions ARMv8.4-a.  */
-  V8_4_INSN ("cfinv",  0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
   V8_4_INSN ("rmif",   0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
   V8_4_INSN ("setf8",  0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
   V8_4_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),

Re: [PATCH][Binutils][AArch64] Fix cfinv disassembly issues

[Nick Clifton]

Hi Tamar,

> Ok for master? and for backport to binutils-2.33 branch and to 2.34 once branch is open?

Approved for all three.  Since this is a bug fix, it is OK to apply to the 2.34 branch now.

> gas/ChangeLog:
> 2020-01-22  Tamar Christina  <tamar.christina@arm.com>
> 
> 	PR 25403
> 	* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
> 	* testsuite/gas/aarch64/armv8_4-a.s: Likewise.
> 
> opcodes/ChangeLog:
> 2020-01-22  Tamar Christina  <tamar.christina@arm.com>
> 
> 	PR 25403
> 	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.

Cheers
  Nick