* [PATCH 3/3] [ARC] Implement NPS-400 PMU Instructions
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
@ 2016-07-22 14:02 ` Graham Markall
2016-07-22 16:41 ` Claudiu Zissulescu
2016-07-22 14:02 ` [PATCH 2/3] [ARC] Implement NPS-400 BMU instructions Graham Markall
` (6 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Graham Markall @ 2016-07-22 14:02 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
gas/ChangeLog:
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
include/ChangeLog:
* opcode/arc.h: Add PMU to insn_class_t enum.
opcodes/ChangeLog:
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
---
gas/ChangeLog | 5 +++++
gas/testsuite/gas/arc/nps400-8.d | 19 +++++++++++++++++++
gas/testsuite/gas/arc/nps400-8.s | 33 +++++++++++++++++++++++++++++++++
include/ChangeLog | 4 ++++
include/opcode/arc.h | 1 +
opcodes/ChangeLog | 6 ++++++
opcodes/arc-nps400-tbl.h | 31 +++++++++++++++++++++++++++++++
opcodes/arc-opc.c | 7 +++++++
8 files changed, 106 insertions(+)
diff --git a/gas/testsuite/gas/arc/nps400-8.d b/gas/testsuite/gas/arc/nps400-8.d
index f93fd58..9f5344c 100644
--- a/gas/testsuite/gas/arc/nps400-8.d
+++ b/gas/testsuite/gas/arc/nps400-8.d
@@ -50,3 +50,22 @@ Disassembly of section .text:
c0: 3b0d 0f82 ffff ffff efabgt r2,r3,0xffffffff
c8: 380d 0000 efabgt r0,r0,r0
cc: 380d 1247 efabgt r7,r8,r9
+ d0: 3e2f 7020 jobget 0,\[cjid:r0\]
+ d4: 3e2f 71a0 jobget 0,\[cjid:r6\]
+ d8: 3e2f 7021 jobget.cl 0,\[cjid:r0\]
+ dc: 3e2f 71a1 jobget.cl 0,\[cjid:r6\]
+ e0: 3812 003e jobdn 0,\[cjid:r0\],r0,r0
+ e4: 3a12 013e jobdn 0,\[cjid:r2\],r2,r4
+ e8: 3852 003e jobdn 0,\[cjid:r0\],r0,0
+ ec: 3a52 03fe jobdn 0,\[cjid:r2\],r2,0xf
+ f0: 381f 0000 jobalc r0,\[cm:r0\],r0,r0
+ f4: 3a1f 00c1 jobalc r1,\[cm:r2\],r2,r3
+ f8: 385f 0840 jobalc r0,\[cm:r0\],r0,0x1
+ fc: 3a5f 0801 jobalc r1,\[cm:r2\],r2,0x4
+ 100: 385f 0040 sjobalc r0,r0
+ 104: 3d5f 0046 sjobalc r6,r5
+ 108: 381a 0000 jobbgt r0,r0,r0
+ 10c: 3d1a 0182 jobbgt r2,r5,r6
+ 110: 3e6f 70ff cnljob 0
+ 114: 386f 0028 qseq r0,\[r0\]
+ 118: 3a6f 0128 qseq r2,\[r4\]
diff --git a/gas/testsuite/gas/arc/nps400-8.s b/gas/testsuite/gas/arc/nps400-8.s
index ad665fd..1042183 100644
--- a/gas/testsuite/gas/arc/nps400-8.s
+++ b/gas/testsuite/gas/arc/nps400-8.s
@@ -57,3 +57,36 @@
efabgt r2,r3,0xffffffff
efabgt r0,r0,r0
efabgt r7,r8,r9
+
+ ;; jobget
+ jobget 0,[cjid:r0]
+ jobget 0,[cjid:r6]
+ jobget.cl 0,[cjid:r0]
+ jobget.cl 0,[cjid:r6]
+
+ ;; jobdn
+ jobdn 0,[cjid:r0],r0,r0
+ jobdn 0,[cjid:r2],r2,r4
+ jobdn 0,[cjid:r0],r0,0
+ jobdn 0,[cjid:r2],r2,15
+
+ ;; jobalc / sjobalc
+ jobalc r0,[cm:r0],r0,r0
+ jobalc r1,[cm:r2],r2,r3
+ jobalc r0,[cm:r0],r0,1
+ jobalc r1,[cm:r2],r2,4
+ sjobalc r0,r0
+ sjobalc r6,r5
+
+ ;; jobbgt
+
+ jobbgt r0,r0,r0
+ jobbgt r2,r5,r6
+
+ ;; cnljob
+
+ cnljob 0
+
+ ;; qseq
+ qseq r0,[r0]
+ qseq r2,[r4]
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 3fb8d88..62580c0 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -55,6 +55,7 @@ typedef enum
LOGICAL,
MEMORY,
NET,
+ PMU,
} insn_class_t;
/* Instruction Subclass. */
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index fbc1f1d..67ae435 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -617,3 +617,34 @@ XLDST_LIKE("xst", 0xe)
/* efabgt dst, src1, src2 */
{ "efabgt", 0x380d0000, 0xf8ff8000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, RC }, { 0 }},
+
+/**** PMU Instructions ****/
+
+/* jobget<.cl> 0, [cjid:src1] */
+{ "jobget", 0x3e2f7020, 0xfffff03f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RC, BRAKET }, { 0 }},
+
+{ "jobget", 0x3e2f7021, 0xfffff03f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RC, BRAKET }, { C_NPS_CL }},
+
+/* jobdn 0, [cjid:src1], src1, src2 */
+{ "jobdn", 0x3812003e, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* jobdn 0, [cjid:src1], src1, nxt_dst */
+{ "jobdn", 0x3852003e, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RB, BRAKETdup, RBdup, NPS_PMU_NXT_DST }, { 0 }},
+
+/* sjobalc dst, src1 */
+{ "sjobalc", 0x385f0040, 0xf8ff8fc0, ARC_OPCODE_ARC700, PMU, NPS400, { RA, RB }, { 0 }},
+
+/* jobalc dst, [cm:src1], src1, num_job */
+{ "jobalc", 0x385f0800, 0xf8ff8800, ARC_OPCODE_ARC700, PMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_PMU_NUM_JOB }, { 0 }},
+
+/* jobalc dst, [cm:src1], src1, src2 */
+{ "jobalc", 0x381f0000, 0xf8ff8000, ARC_OPCODE_ARC700, PMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* jobbgt dst, src1, src2 */
+{ "jobbgt", 0x381a0000, 0xf8ff0000, ARC_OPCODE_ARC700, PMU, NPS400, { RA, RB, RC }, { 0 }},
+
+/* cnljob 0 */
+{ "cnljob", 0x3e6f70ff, 0xffffffff, ARC_OPCODE_ARC700, PMU, NPS400, { ZA }, { 0 }},
+
+/* qseq dst, [src1] */
+{ "qseq", 0x386f0028, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index beba028..ea4209c 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1139,6 +1139,7 @@ MAKE_1BASED_INSERT_EXTRACT_FUNCS(shift_factor, 9, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bits_to_scramble, 12, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bdlen_max_len, 5, 256, 8)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bd_num_buff, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(pmu_num_job, 6, 4, 2)
static unsigned
insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
@@ -2175,6 +2176,12 @@ const struct arc_operand arc_operands[] =
#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
{ 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
+
+#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
+ { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
+ { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/3] [ARC] Begin implementing NPS-400 Accelerator instructions
@ 2016-07-22 14:02 ` Graham Markall
2016-07-22 14:02 ` [PATCH 3/3] [ARC] Implement NPS-400 PMU Instructions Graham Markall
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Graham Markall @ 2016-07-22 14:02 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
This series of patches implements the NPS-400 BMU and PMU instructions,
which are a subset of the Accelerator instructions. Many Accelerator
instructions use address types in their operands, an example being the
bdalc instruction:
bdalc DST, [cm:SRC1], SRC1, SRC2
The address type here is cm, which specifies that the second operand is
an offset given by SRC1 into the CMEM area. There is a limited number
of other address types (cm, cd, cbd, etc...). The first patch in this
series adds support for all address types, and the following two patches
implement the BMU and PMU instructions which make use of some of these
address types.
There are further accelerator instructions to implement. These will
be submitted in future once the support for address types is agreed-upon
and applied.
All patches pass a `make check` for ARC big- and little-endian.
Graham Markall (3):
[ARC] Add support for address type syntax
[ARC] Implement NPS-400 BMU instructions
[ARC] Implement NPS-400 PMU Instructions
gas/ChangeLog | 21 ++++++++
gas/config/tc-arc.c | 92 +++++++++++++++++++++++++++++++++--
gas/testsuite/gas/arc/nps400-8.d | 71 +++++++++++++++++++++++++++
gas/testsuite/gas/arc/nps400-8.s | 92 +++++++++++++++++++++++++++++++++++
include/ChangeLog | 13 +++++
include/opcode/arc.h | 71 ++++++++++++++++++++++++++-
opcodes/ChangeLog | 22 +++++++++
opcodes/arc-dis.c | 39 +++++++++++++--
opcodes/arc-nps400-tbl.h | 96 +++++++++++++++++++++++++++++++++++++
opcodes/arc-opc.c | 101 +++++++++++++++++++++++++++++++++++++++
10 files changed, 610 insertions(+), 8 deletions(-)
create mode 100644 gas/testsuite/gas/arc/nps400-8.d
create mode 100644 gas/testsuite/gas/arc/nps400-8.s
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/3] [ARC] Implement NPS-400 BMU instructions
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
2016-07-22 14:02 ` [PATCH 3/3] [ARC] Implement NPS-400 PMU Instructions Graham Markall
@ 2016-07-22 14:02 ` Graham Markall
2016-07-22 16:43 ` Claudiu Zissulescu
2016-07-22 14:02 ` [PATCH 1/3] [ARC] Add support for address type syntax Graham Markall
` (5 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Graham Markall @ 2016-07-22 14:02 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
gas/ChangeLog:
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
include/ChangeLog:
* opcode/arc.h: Add BMU to insn_class_t enum.
opcodes/ChangeLog:
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
---
gas/ChangeLog | 5 ++++
gas/testsuite/gas/arc/nps400-8.d | 52 ++++++++++++++++++++++++++++++++
gas/testsuite/gas/arc/nps400-8.s | 59 ++++++++++++++++++++++++++++++++++++
include/ChangeLog | 4 +++
include/opcode/arc.h | 1 +
opcodes/ChangeLog | 6 ++++
opcodes/arc-nps400-tbl.h | 65 ++++++++++++++++++++++++++++++++++++++++
opcodes/arc-opc.c | 7 +++++
8 files changed, 199 insertions(+)
create mode 100644 gas/testsuite/gas/arc/nps400-8.d
create mode 100644 gas/testsuite/gas/arc/nps400-8.s
diff --git a/gas/testsuite/gas/arc/nps400-8.d b/gas/testsuite/gas/arc/nps400-8.d
new file mode 100644
index 0000000..f93fd58
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-8.d
@@ -0,0 +1,52 @@
+#as: -mcpu=arc700 -mnps400
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 3810 0000 bdalc r0,\[cm:r0\],r0,r0
+ 4: 3a10 00c1 bdalc r1,\[cm:r2\],r2,r3
+ 8: 3850 0840 bdalc r0,\[cm:r0\],r0,0,0x1
+ c: 3b50 0c42 bdalc r2,\[cm:r3\],r3,0x1,0x1
+ 10: 3c50 0c03 bdalc r3,\[cm:r4\],r4,0x1,0x8
+ 14: 3850 0040 sbdalc r0,r0,0
+ 18: 3c50 0443 sbdalc r3,r4,0x1
+ 1c: 3811 003e bdfre 0,\[cm:r0\],r0,r0
+ 20: 3911 00be bdfre 0,\[cm:r1\],r1,r2
+ 24: 3851 007e bdfre 0,\[cm:r0\],r0,0x1
+ 28: 3a51 003e bdfre 0,\[cm:r2\],r2,0x8
+ 2c: 3851 087e bdfre 0,\[cm:r0\],r0,0,0x1
+ 30: 3e51 083e bdfre 0,\[cm:r6\],r6,0,0x8
+ 34: 3851 0c7e bdfre 0,\[cm:r0\],r0,0x1,0x1
+ 38: 3e51 0c3e bdfre 0,\[cm:r6\],r6,0x1,0x8
+ 3c: 3817 003e sbdfre 0,r0,r0
+ 40: 3917 00be sbdfre 0,r1,r2
+ 44: 3818 003e bdbgt 0,r0,r0
+ 48: 3c18 01be bdbgt 0,r4,r6
+ 4c: 381c 0000 idxalc r0,\[cm:r0\],r0,r0
+ 50: 3a1c 00c1 idxalc r1,\[cm:r2\],r2,r3
+ 54: 3d5c 0884 idxalc r4,\[cm:r5\],r5,0x2
+ 58: 385c 0040 sidxalc r0,r0
+ 5c: 3a5c 0044 sidxalc r4,r2
+ 60: 381e 003e idxfre 0,\[cm:r0\],r0,r0
+ 64: 391e 00be idxfre 0,\[cm:r1\],r1,r2
+ 68: 385e 007e idxfre 0,\[cm:r0\],r0,0x1
+ 6c: 3a5e 003e idxfre 0,\[cm:r2\],r2,0x8
+ 70: 381d 003e sidxfre 0,r0,r0
+ 74: 391d 00be sidxfre 0,r1,r2
+ 78: 3819 003e idxbgt 0,r0,r0
+ 7c: 3f19 023e idxbgt 0,r7,r8
+ 80: 3e0d 703e 0000 0000 efabgt 0,0,r0
+ 88: 3e0d 70fe ffff ffff efabgt 0,0xffffffff,r3
+ 90: 380d 0fbe 0000 0000 efabgt 0,r0,0
+ 98: 3c0d 0fbe ffff ffff efabgt 0,r4,0xffffffff
+ a0: 380d 003e efabgt 0,r0,r0
+ a4: 3f0d 023e efabgt 0,r7,r8
+ a8: 3e0d 7000 0000 0000 efabgt r0,0,r0
+ b0: 3e0d 7184 ffff ffff efabgt r4,0xffffffff,r6
+ b8: 380d 0f80 0000 0000 efabgt r0,r0,0
+ c0: 3b0d 0f82 ffff ffff efabgt r2,r3,0xffffffff
+ c8: 380d 0000 efabgt r0,r0,r0
+ cc: 380d 1247 efabgt r7,r8,r9
diff --git a/gas/testsuite/gas/arc/nps400-8.s b/gas/testsuite/gas/arc/nps400-8.s
new file mode 100644
index 0000000..ad665fd
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-8.s
@@ -0,0 +1,59 @@
+ .text
+
+ ;; bdalc / sbdalc
+ bdalc r0,[cm:r0],r0,r0
+ bdalc r1,[cm:r2],r2,r3
+ bdalc r0,[cm:r0],r0,0,1
+ bdalc r2,[cm:r3],r3,1,1
+ bdalc r3,[cm:r4],r4,1,8
+ sbdalc r0, r0, 0
+ sbdalc r3, r4, 1
+
+ ;; bdfre / sbdfre
+ bdfre 0,[cm:r0],r0,r0
+ bdfre 0,[cm:r1],r1,r2
+ bdfre 0,[cm:r0],r0,1
+ bdfre 0,[cm:r2],r2,8
+ bdfre 0,[cm:r0],r0,0,1
+ bdfre 0,[cm:r6],r6,0,8
+ bdfre 0,[cm:r0],r0,1,1
+ bdfre 0,[cm:r6],r6,1,8
+ sbdfre 0, r0, r0
+ sbdfre 0, r1, r2
+
+ ;; bdbgt
+ bdbgt 0,r0,r0
+ bdbgt 0,r4,r6
+
+ ;; idxalc / sidxalc
+ idxalc r0,[cm:r0],r0,r0
+ idxalc r1,[cm:r2],r2,r3
+ idxalc r4,[cm:r5],r5,2
+ sidxalc r0,r0
+ sidxalc r4,r2
+
+ ;; idxfre / sidxfre
+ idxfre 0,[cm:r0],r0,r0
+ idxfre 0,[cm:r1],r1,r2
+ idxfre 0,[cm:r0],r0,1
+ idxfre 0,[cm:r2],r2,8
+ sidxfre 0, r0, r0
+ sidxfre 0, r1, r2
+
+ ;; idxbgt
+ idxbgt 0,r0,r0
+ idxbgt 0,r7,r8
+
+ ;; efabgt
+ efabgt 0,0x0,r0
+ efabgt 0,0xffffffff,r3
+ efabgt 0,r0,0x0
+ efabgt 0,r4,0xffffffff
+ efabgt 0,r0,r0
+ efabgt 0,r7,r8
+ efabgt r0,0x0,r0
+ efabgt r4,0xffffffff,r6
+ efabgt r0,r0,0x0
+ efabgt r2,r3,0xffffffff
+ efabgt r0,r0,r0
+ efabgt r7,r8,r9
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index fe955ca..3fb8d88 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -43,6 +43,7 @@ typedef enum
ARITH,
AUXREG,
BITOP,
+ BMU,
BRANCH,
CONTROL,
DPI,
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index 580659a..fbc1f1d 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -552,3 +552,68 @@ XLDST_LIKE("xld", 0xa)
XLDST_LIKE("xstb", 0xc)
XLDST_LIKE("xstw", 0xd)
XLDST_LIKE("xst", 0xe)
+
+/**** BMU Instructions ****/
+
+/* sbdalc dst, src1, type */
+{ "sbdalc", 0x38500040, 0xf8ff09c0, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, NPS_BD_TYPE }, { 0 }},
+
+/* bdalc dst, [cm:src1], src1, src2 */
+{ "bdalc", 0x38100000, 0xf8ff0000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* bdalc dst, [cm:src1], src1, type, num_buff */
+{ "bdalc", 0x38500800, 0xf8ff0800, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BD_TYPE, NPS_BMU_NUM }, { 0 }},
+
+/* sbdfre 0, src1, src2 */
+{ "sbdfre", 0x3817003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* bdfre 0, [cm:src1], src1, src2 */
+{ "bdfre", 0x3811003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* bdfre 0, [cm:src1], src1, type, num_buff */
+{ "bdfre", 0x3851083e, 0xf8ff083f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BD_TYPE, NPS_BMU_NUM }, { 0 }},
+
+/* bdfre 0, [cm:src1], src1, num_buff */
+{ "bdfre", 0x3851003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }},
+
+/* bdbgt 0, src1, src2 */
+{ "bdbgt", 0x3818003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* sidxalc dst, src1 */
+{ "sidxalc", 0x385c0040, 0xf8ff0040, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB }, { 0 }},
+
+/* idxalc dst, [cm:src1], src1, src2 */
+{ "idxalc", 0x381c0000, 0xf8ff0000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* idxalc dst, [cm:src1], src1, num_idx */
+{ "idxalc", 0x385c0800, 0xf8ff0800, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }},
+
+/* sidxfre 0, src1, src2 */
+{ "sidxfre", 0x381d003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* idxfre 0, [cm:src1], src1, src2 */
+{ "idxfre", 0x381e003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* idxfre 0, [cm:src1], src1, num_buff */
+{ "idxfre", 0x385e003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }},
+
+/* idxbgt 0, src1, src2 */
+{ "idxbgt", 0x3819003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* efabgt 0, limm, src2 */
+{ "efabgt", 0x3e0d703e, 0xfffff03f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, LIMM, RC }, { 0 }},
+
+/* efabgt 0, src1, limm */
+{ "efabgt", 0x380d0fbe, 0xf8ff80ff, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, LIMM }, { 0 }},
+
+/* efabgt 0, src1, src2 */
+{ "efabgt", 0x380d003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* efabgt dst, limm, src2 */
+{ "efabgt", 0x3e0d7000, 0xfffff000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, LIMM, RC }, { 0 }},
+
+/* efabgt dst, src1, limm */
+{ "efabgt", 0x380d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, LIMM }, { 0 }},
+
+/* efabgt dst, src1, src2 */
+{ "efabgt", 0x380d0000, 0xf8ff8000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, RC }, { 0 }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 111e01d..beba028 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1138,6 +1138,7 @@ MAKE_1BASED_INSERT_EXTRACT_FUNCS(field_size, 6, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(shift_factor, 9, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bits_to_scramble, 12, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bdlen_max_len, 5, 256, 8)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(bd_num_buff, 6, 8, 3)
static unsigned
insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
@@ -2168,6 +2169,12 @@ const struct arc_operand arc_operands[] =
#define NPS_CXD (NPS_CXA + 1)
{ 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
+
+#define NPS_BD_TYPE (NPS_CXD + 1)
+ { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
+ { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/3] [ARC] Add support for address type syntax
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
2016-07-22 14:02 ` [PATCH 3/3] [ARC] Implement NPS-400 PMU Instructions Graham Markall
2016-07-22 14:02 ` [PATCH 2/3] [ARC] Implement NPS-400 BMU instructions Graham Markall
@ 2016-07-22 14:02 ` Graham Markall
2016-07-22 16:53 ` Claudiu Zissulescu
2016-07-25 5:47 ` [PATCH 1/4] [ARC] Change block comments to GNU style Graham Markall
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Graham Markall @ 2016-07-22 14:02 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
Some NPS-400 instructions include an address type in an indirect
argument, which includes the name of the address type followed by
a colon, before the usual register or immediate argument. For
example, the syntax of one instruction using an address type is:
bdalc DST, [cm:SRC1], SRC1, SRC2
where the second argument is an offset into the CMEM area given by
SRC1.
In order to add support for address types, there are two main
changes:
1. Addition of the colon operand, which is handled in much the
same way as brackets are already handled.
2. Addition of support for address type operands. There are a
limited number of address types, which are all implemented in this
patch.
- In the assembler, address types are supported in a similar way to
how registers are supported: a token representing an address type
has its X_op field set to O_addrtype, and its X_add_number is an
enum value that represents a particular address type. These values
are added to include/opcode/arc.h in the arc_nps_address_type
enum. In order for X_op and X_add_number to be set correctly,
arc_parse_name is modified to parse address types as well as
registers, using the arc_addrtype_hash to map from address type
names to enum values.
- In the disassembler, colons and address types are printed out
when necessary, as determined by the operands of opcode that has
been matched.
- In libopcodes, the operands for colons and address types are
declared. The insert functions don't actually insert anything
because the address type for an operand is actually determined
by the combination of major opcode and subopcodes of an
instruction. However, they do check that the address type being
inserted matches the specified address type for the operand, in
order to reject opcodes that are invalid for a given address
type.
gas/ChangeLog:
* config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
include/ChangeLog:
* opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
ARC_NUM_ADDRTYPES.
opcodes/ChangeLog:
* arc-dis.c: Add new globals addrtypenames,
addrtypenames_max, and addtypeunknown.
(get_addrtype): New function.
(print_insn_arc): Print colons and address types when
required.
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
define insert and extract functions for all address types.
(arc_operands): Add operands for colon and all address
types.
---
gas/ChangeLog | 11 +++++++
gas/config/tc-arc.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++---
include/ChangeLog | 5 +++
include/opcode/arc.h | 69 ++++++++++++++++++++++++++++++++++++++-
opcodes/ChangeLog | 10 ++++++
opcodes/arc-dis.c | 39 ++++++++++++++++++++--
opcodes/arc-opc.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++
7 files changed, 305 insertions(+), 8 deletions(-)
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 70886dd..1aeea46 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -420,6 +420,9 @@ static struct hash_control *arc_reg_hash;
/* The hash table of aux register symbols. */
static struct hash_control *arc_aux_hash;
+/* The hash table of address types. */
+static struct hash_control *arc_addrtype_hash;
+
/* A table of CPU names and opcode sets. */
static const struct cpu_type
{
@@ -461,6 +464,12 @@ static const struct cpu_type
/* Used to define a bracket as operand in tokens. */
#define O_bracket O_md32
+/* Used to define a colon as an operand in tokens */
+#define O_colon O_md31
+
+/* Used to define address types in nps400 */
+#define O_addrtype O_md30
+
/* Dummy relocation, to be sorted out. */
#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
@@ -979,6 +988,8 @@ debug_exp (expressionS *t)
case O_logical_or: name = "O_logical_or"; break;
case O_index: name = "O_index"; break;
case O_bracket: name = "O_bracket"; break;
+ case O_colon: name = "O_colon"; break;
+ case O_addrtype: name = "O_addrtype"; break;
}
switch (t->X_md)
@@ -1067,6 +1078,16 @@ tokenize_arguments (char *str,
++num_args;
break;
+ case ':':
+ input_line_pointer++;
+ if (!saw_arg || num_args == ntok)
+ goto err;
+ tok->X_op = O_colon;
+ saw_arg = FALSE;
+ ++tok;
+ ++num_args;
+ break;
+
case '@':
/* We have labels, function names and relocations, all
starting with @ symbol. Sort them out. */
@@ -1694,7 +1715,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
/* Only take input from real operands. */
if ((operand->flags & ARC_OPERAND_FAKE)
- && !(operand->flags & ARC_OPERAND_BRAKET))
+ && !((operand->flags & ARC_OPERAND_BRAKET) ||
+ (operand->flags & ARC_OPERAND_COLON)))
continue;
/* When we expect input, make sure we have it. */
@@ -1704,6 +1726,12 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
/* Match operand type with expression type. */
switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
{
+ case ARC_OPERAND_ADDRTYPE:
+ /* Check to be an address type */
+ if (tok[tokidx].X_op != O_addrtype)
+ goto match_failed;
+ break;
+
case ARC_OPERAND_IR:
/* Check to be a register. */
if ((tok[tokidx].X_op != O_register
@@ -1755,6 +1783,12 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
goto match_failed;
break;
+ case ARC_OPERAND_COLON:
+ /* Check if colon is also in opcode table as operand */
+ if (tok[tokidx].X_op != O_colon)
+ goto match_failed;
+ break;
+
case ARC_OPERAND_LIMM:
case ARC_OPERAND_SIGNED:
case ARC_OPERAND_UNSIGNED:
@@ -2461,6 +2495,22 @@ declare_register_set (void)
}
}
+/* Construct a symbol for an address type. */
+
+static void
+declare_addrtype (const char *name, int number)
+{
+ const char *err;
+ symbolS *addrtypeS = symbol_create (name, undefined_section,
+ number, &zero_address_frag);
+
+ err = hash_insert (arc_addrtype_hash, S_GET_NAME(addrtypeS),
+ (void *) addrtypeS);
+ if (err)
+ as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
+ name, err);
+}
+
/* Port-specific assembler initialization. This function is called
once, at assembler startup time. */
@@ -2575,6 +2625,28 @@ md_begin (void)
as_fatal (_("internal error: can't hash aux register '%s': %s"),
auxr->name, retval);
}
+
+ /* Address type declaration. */
+ arc_addrtype_hash = hash_new ();
+ if (arc_addrtype_hash == NULL)
+ as_fatal (_("Virtual memory exhausted"));
+
+ declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
+ declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
+ declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
+ declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
+ declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
+ declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
+ declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
+ declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
+ declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
+ declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
+ declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
+ declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
+ declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
+ declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
+ declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
+ declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
}
/* Write a value out to the object file, using the appropriate
@@ -3254,7 +3326,7 @@ arc_parse_name (const char *name,
if (!assembling_insn)
return FALSE;
- /* Handle only registers. */
+ /* Handle only registers and address types. */
if (e->X_op != O_absent)
return FALSE;
@@ -3265,6 +3337,15 @@ arc_parse_name (const char *name,
e->X_add_number = S_GET_VALUE (sym);
return TRUE;
}
+
+ sym = hash_find (arc_addrtype_hash, name);
+ if (sym)
+ {
+ e->X_op = O_addrtype;
+ e->X_add_number = S_GET_VALUE (sym);
+ return TRUE;
+ }
+
return FALSE;
}
@@ -3727,7 +3808,8 @@ assemble_insn (const struct arc_opcode *opcode,
const expressionS *t = (const expressionS *) 0;
if ((operand->flags & ARC_OPERAND_FAKE)
- && !(operand->flags & ARC_OPERAND_BRAKET))
+ && !((operand->flags & ARC_OPERAND_BRAKET) ||
+ (operand->flags & ARC_OPERAND_COLON)))
continue;
if (operand->flags & ARC_OPERAND_DUPLICATE)
@@ -3764,7 +3846,9 @@ assemble_insn (const struct arc_opcode *opcode,
break;
case O_bracket:
- /* Ignore brackets. */
+ case O_colon:
+ case O_addrtype:
+ /* Ignore brackets, colons, and address types. */
break;
case O_absent:
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index f0fefbb..fe955ca 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -336,11 +336,18 @@ extern const unsigned arc_NToperand;
/* Mark the braket possition. */
#define ARC_OPERAND_BRAKET 0x1000
+/* Address type operand for NPS400 */
+#define ARC_OPERAND_ADDRTYPE 0x2000
+
+/* Mark the colon position */
+#define ARC_OPERAND_COLON 0x4000
+
/* Mask for selecting the type for typecheck purposes. */
#define ARC_OPERAND_TYPECHECK_MASK \
(ARC_OPERAND_IR | \
ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \
- ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
+ ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET | \
+ ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
/* The flags structure. */
struct arc_flag_operand
@@ -608,6 +615,66 @@ extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
+/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
+ Instruction Set Reference Manual v2.4 for a description of address types. */
+
+typedef enum {
+ /* Addresses in memory. */
+
+ /* Buffer descriptor. */
+ ARC_NPS400_ADDRTYPE_BD,
+
+ /* Job identifier. */
+ ARC_NPS400_ADDRTYPE_JID,
+
+ /* Linked Buffer Descriptor. */
+ ARC_NPS400_ADDRTYPE_LBD,
+
+ /* Multicast Buffer Descriptor. */
+ ARC_NPS400_ADDRTYPE_MBD,
+
+ /* Summarized Address. */
+ ARC_NPS400_ADDRTYPE_SD,
+
+ /* SMEM Security Context Local Memory. */
+ ARC_NPS400_ADDRTYPE_SM,
+
+ /* Extended Address. */
+ ARC_NPS400_ADDRTYPE_XA,
+
+ /* Extended Summarized Address. */
+ ARC_NPS400_ADDRTYPE_XD,
+
+ /* CMEM offset addresses. */
+
+ /* On-demand Counter Descriptor. */
+ ARC_NPS400_ADDRTYPE_CD,
+
+ /* CMEM Buffer Descriptor. */
+ ARC_NPS400_ADDRTYPE_CBD,
+
+ /* CMEM Job Identifier. */
+ ARC_NPS400_ADDRTYPE_CJID,
+
+ /* CMEM Linked Buffer Descriptor. */
+ ARC_NPS400_ADDRTYPE_CLBD,
+
+ /* CMEM Offset. */
+ ARC_NPS400_ADDRTYPE_CM,
+
+ /* CMEM Summarized Address. */
+ ARC_NPS400_ADDRTYPE_CSD,
+
+ /* CMEM Extended Address. */
+ ARC_NPS400_ADDRTYPE_CXA,
+
+ /* CMEM Extended Summarized Address. */
+ ARC_NPS400_ADDRTYPE_CXD,
+
+} arc_nps_address_type;
+
+#define ARC_NUM_ADDRTYPES 16
+
#ifdef __cplusplus
}
#endif
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 7b78bdc..f882b74 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -85,6 +85,16 @@ static const char * const regnames[64] =
"r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
};
+static const char * const addrtypenames[ARC_NUM_ADDRTYPES] =
+{
+ "bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
+ "cd", "cbd", "cjid", "clbd", "cm", "csd", "cxa", "cxd"
+};
+
+static int addrtypenames_max = ARC_NUM_ADDRTYPES - 1;
+
+static const char * const addrtypeunknown = "unknown";
+
/* This structure keeps track which instruction class(es)
should be ignored durring disassembling. */
@@ -653,6 +663,15 @@ get_auxreg (const struct arc_opcode *opcode,
return NULL;
}
+static const char *
+get_addrtype (int value)
+{
+ if (value < 0 || value > addrtypenames_max)
+ return addrtypeunknown;
+
+ return addrtypenames[value];
+}
+
/* Calculate the instruction length for an instruction starting with MSB
and LSB, the most and least significant byte. The ISA_MASK is used to
filter the instructions considered to only those that are part of the
@@ -1105,7 +1124,8 @@ print_insn_arc (bfd_vma memaddr,
/* Only take input from real operands. */
if ((operand->flags & ARC_OPERAND_FAKE)
- && !(operand->flags & ARC_OPERAND_BRAKET))
+ && !((operand->flags & ARC_OPERAND_BRAKET) ||
+ (operand->flags & ARC_OPERAND_COLON)))
continue;
if ((operand->flags & ARC_OPERAND_IGNORE)
@@ -1113,6 +1133,12 @@ print_insn_arc (bfd_vma memaddr,
&& value == -1)
continue;
+ if (operand->flags & ARC_OPERAND_COLON)
+ {
+ (*info->fprintf_func) (info->stream, ":");
+ continue;
+ }
+
if (need_comma)
(*info->fprintf_func) (info->stream, ",");
@@ -1124,6 +1150,8 @@ print_insn_arc (bfd_vma memaddr,
continue;
}
+ need_comma = TRUE;
+
/* Print the operand as directed by the flags. */
if (operand->flags & ARC_OPERAND_IR)
{
@@ -1172,6 +1200,13 @@ print_insn_arc (bfd_vma memaddr,
else
(*info->fprintf_func) (info->stream, "%d", value);
}
+ else if (operand->flags & ARC_OPERAND_ADDRTYPE)
+ {
+ const char *addrtype = get_addrtype (value);
+ (*info->fprintf_func) (info->stream, "%s", addrtype);
+ /* A colon follow an address type. */
+ need_comma = FALSE;
+ }
else
{
if (operand->flags & ARC_OPERAND_TRUNCATE
@@ -1189,8 +1224,6 @@ print_insn_arc (bfd_vma memaddr,
(*info->fprintf_func) (info->stream, "%#x", value);
}
}
-
- need_comma = TRUE;
}
return insn_len;
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index ad50ebc..111e01d 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1160,6 +1160,42 @@ extract_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
return value * 16;
}
+#define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \
+static unsigned \
+insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
+ int value ATTRIBUTE_UNUSED, \
+ const char **errmsg ATTRIBUTE_UNUSED) \
+{ \
+ if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
+ *errmsg = _("Invalid address type for operand"); \
+ return insn; \
+} \
+ \
+static int \
+extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ARC_NPS400_ADDRTYPE_##VALUE; \
+}
+
+MAKE_INSERT_NPS_ADDRTYPE(bd, BD)
+MAKE_INSERT_NPS_ADDRTYPE(jid, JID)
+MAKE_INSERT_NPS_ADDRTYPE(lbd, LBD)
+MAKE_INSERT_NPS_ADDRTYPE(mbd, MBD)
+MAKE_INSERT_NPS_ADDRTYPE(sd, SD)
+MAKE_INSERT_NPS_ADDRTYPE(sm, SM)
+MAKE_INSERT_NPS_ADDRTYPE(xa, XA)
+MAKE_INSERT_NPS_ADDRTYPE(xd, XD)
+MAKE_INSERT_NPS_ADDRTYPE(cd, CD)
+MAKE_INSERT_NPS_ADDRTYPE(cbd, CBD)
+MAKE_INSERT_NPS_ADDRTYPE(cjid, CJID)
+MAKE_INSERT_NPS_ADDRTYPE(clbd, CLBD)
+MAKE_INSERT_NPS_ADDRTYPE(cm, CM)
+MAKE_INSERT_NPS_ADDRTYPE(csd, CSD)
+MAKE_INSERT_NPS_ADDRTYPE(cxa, CXA)
+MAKE_INSERT_NPS_ADDRTYPE(cxd, CXD)
+
+
/* Include the generic extract/insert functions. Order is important
as some of the functions present in the .h may be disabled via
defines. */
@@ -2081,6 +2117,57 @@ const struct arc_operand arc_operands[] =
#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
{ 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 },
+
+#define COLON (NPS_E4BY_INDEX3 + 1)
+ { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
+
+#define NPS_BD (COLON + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd },
+
+#define NPS_JID (NPS_BD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid },
+
+#define NPS_LBD (NPS_JID + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd },
+
+#define NPS_MBD (NPS_LBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd },
+
+#define NPS_SD (NPS_MBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd },
+
+#define NPS_SM (NPS_SD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm },
+
+#define NPS_XA (NPS_SM + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa },
+
+#define NPS_XD (NPS_XA + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd },
+
+#define NPS_CD (NPS_XD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd },
+
+#define NPS_CBD (NPS_CD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd },
+
+#define NPS_CJID (NPS_CBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid },
+
+#define NPS_CLBD (NPS_CJID + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd },
+
+#define NPS_CM (NPS_CLBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm },
+
+#define NPS_CSD (NPS_CM + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd },
+
+#define NPS_CXA (NPS_CSD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa },
+
+#define NPS_CXD (NPS_CXA + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/3] [ARC] Implement NPS-400 PMU Instructions
2016-07-22 14:02 ` [PATCH 3/3] [ARC] Implement NPS-400 PMU Instructions Graham Markall
@ 2016-07-22 16:41 ` Claudiu Zissulescu
0 siblings, 0 replies; 17+ messages in thread
From: Claudiu Zissulescu @ 2016-07-22 16:41 UTC (permalink / raw)
To: Graham Markall, binutils; +Cc: claudiu.zissulescu
Hi,
> @@ -55,6 +55,7 @@ typedef enum
> LOGICAL,
> MEMORY,
> NET,
> + PMU,
Using older compilers this last comma may trigger a warning. You may
remove it if you please.
> +/**** PMU Instructions ****/
This is not a gnu-like comment. Please use dot and 2 spaces.
Best,
Claudiu
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/3] [ARC] Implement NPS-400 BMU instructions
2016-07-22 14:02 ` [PATCH 2/3] [ARC] Implement NPS-400 BMU instructions Graham Markall
@ 2016-07-22 16:43 ` Claudiu Zissulescu
2016-07-22 17:00 ` Graham Markall
0 siblings, 1 reply; 17+ messages in thread
From: Claudiu Zissulescu @ 2016-07-22 16:43 UTC (permalink / raw)
To: Graham Markall, binutils; +Cc: claudiu.zissulescu
Hi,
> +
> +/**** BMU Instructions ****/
> +
This is not a gnu like comment, please fix it.
Thanks,
Claudiu
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/3] [ARC] Add support for address type syntax
2016-07-22 14:02 ` [PATCH 1/3] [ARC] Add support for address type syntax Graham Markall
@ 2016-07-22 16:53 ` Claudiu Zissulescu
2016-07-25 5:50 ` Graham Markall
0 siblings, 1 reply; 17+ messages in thread
From: Claudiu Zissulescu @ 2016-07-22 16:53 UTC (permalink / raw)
To: Graham Markall, binutils; +Cc: claudiu.zissulescu
Hi,
>
> +/* Used to define a colon as an operand in tokens */
Dot space space.
> +#define O_colon O_md31
> +
> +/* Used to define address types in nps400 */
Same here.
> +#define O_addrtype O_md30
> +
> /* Dummy relocation, to be sorted out. */
> #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
>
> @@ -979,6 +988,8 @@ debug_exp (expressionS *t)
> case O_logical_or: name = "O_logical_or"; break;
> case O_index: name = "O_index"; break;
> case O_bracket: name = "O_bracket"; break;
> + case O_colon: name = "O_colon"; break;
> + case O_addrtype: name = "O_addrtype"; break;
Groups of 8 spaces needs to be replaced by tabs.
> if ((operand->flags & ARC_OPERAND_FAKE)
> - && !(operand->flags & ARC_OPERAND_BRAKET))
> + && !((operand->flags & ARC_OPERAND_BRAKET) ||
> + (operand->flags & ARC_OPERAND_COLON)))
May make sense to craft a macro here, as this construction is used
multiple time.
> + case ARC_OPERAND_ADDRTYPE:
> + /* Check to be an address type */
Dot space space.
> + case ARC_OPERAND_COLON:
> + /* Check if colon is also in opcode table as operand */
Same here.
> - && !(operand->flags & ARC_OPERAND_BRAKET))
> + && !((operand->flags & ARC_OPERAND_BRAKET) ||
> + (operand->flags & ARC_OPERAND_COLON)))
Here you can reuse the macro above suggested.
> +/* Address type operand for NPS400 */
Dot space space.
> +#define ARC_OPERAND_ADDRTYPE 0x2000
> +
> +/* Mark the colon position */
Same here.
> + /* CMEM Extended Summarized Address. */
> + ARC_NPS400_ADDRTYPE_CXD,
This last comma may trigger warnings with old compilers.
>
> +static const char *
Missing a short description of the function.
> +get_addrtype (int value)
> +{
> + if (value < 0 || value > addrtypenames_max)
> + return addrtypeunknown;
> +
> + return addrtypenames[value];
> +}
> - && !(operand->flags & ARC_OPERAND_BRAKET))
> + && !((operand->flags & ARC_OPERAND_BRAKET) ||
> + (operand->flags & ARC_OPERAND_COLON)))
Macro used here.
Thanks,
Claudiu
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/3] [ARC] Implement NPS-400 BMU instructions
2016-07-22 16:43 ` Claudiu Zissulescu
@ 2016-07-22 17:00 ` Graham Markall
2016-07-22 17:14 ` Claudiu Zissulescu
0 siblings, 1 reply; 17+ messages in thread
From: Graham Markall @ 2016-07-22 17:00 UTC (permalink / raw)
To: Claudiu Zissulescu, binutils; +Cc: claudiu.zissulescu
[-- Attachment #1.1: Type: text/plain, Size: 823 bytes --]
Hi Claudiu,
Many thanks for the fast review.
On 22/07/16 17:43, Claudiu Zissulescu wrote:
>> +
>> +/**** BMU Instructions
>> ****/
>> +
> This is not a gnu like comment, please fix it.
>
> This is not a gnu-like comment. Please use dot and 2 spaces.
There are quite a few instances of this comment format, and I'd prefer
to correct them all rather than just the two that are introduced by
these patches, which I'll do. However, I'd like to check exactly what
you mean by "Please use dot and 2 spaces." to save going back-and-forth
more than once - did you mean that they should follow this format:
/* BMU Instructions. */
? If I have misunderstood, could you provide me with an example of the
preferred format please?
Many thanks,
Graham.
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/3] [ARC] Implement NPS-400 BMU instructions
2016-07-22 17:00 ` Graham Markall
@ 2016-07-22 17:14 ` Claudiu Zissulescu
0 siblings, 0 replies; 17+ messages in thread
From: Claudiu Zissulescu @ 2016-07-22 17:14 UTC (permalink / raw)
To: Graham Markall, binutils; +Cc: claudiu.zissulescu
>
> /* BMU Instructions. */
>
Sorry for not being clear. This comment is ok. Block comments are not
encouraged within gnu projects. Though, I like them.
//Claudiu
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/4] [ARC] Change block comments to GNU style
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
` (2 preceding siblings ...)
2016-07-22 14:02 ` [PATCH 1/3] [ARC] Add support for address type syntax Graham Markall
@ 2016-07-25 5:47 ` Graham Markall
2016-07-25 5:47 ` [PATCH 2/4] [ARC] Add support for address type syntax Graham Markall
` (3 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Graham Markall @ 2016-07-25 5:47 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
opcodes/ChangeLog:
* arc-nps400-tbl.h: Change block comments to GNU format.
---
opcodes/ChangeLog | 4 ++++
opcodes/arc-nps400-tbl.h | 14 +++++++-------
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index 580659a..f3bd81b 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -1,4 +1,4 @@
-/**** Bit Manipulation Instructions ****/
+/* Bit Manipulation Instructions. */
/* movl<.cl> */
{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
@@ -148,7 +148,7 @@
/* crc32<.r> 0,limm,u6 00111 110 01 110100 R 111 uuuuuu 111110 */
{ "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
-/**** Arithmetic & Logic Instructions ****/
+/* Arithmetic & Logic Instructions. */
#define ADDB_LIKE(NAME,SUBOP2) \
{ NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, NPS_ADDB_SIZE }, { C_NPS_F, C_NPS_SX }},
@@ -367,7 +367,7 @@ ADDL_LIKE ("xorl", 0xE, NPS_UIMM16)
/* hofs a,b,min_hofs,psbc */
{ "hofs", 0x38760000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, NPS_MIN_HOFS, NPS_PSBC }, { C_F }},
-/**** Protocol Decoder Instructions ****/
+/* Protocol Decoder Instructions. */
/* dctcp b,c 00111bbb001011110bbbcccccc000000 */
{ "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }},
@@ -381,12 +381,12 @@ ADDL_LIKE ("xorl", 0xE, NPS_UIMM16)
/* dcet a,b,c 00111bbb001000000bbbccccccaaaaaa */
{ "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }},
-/**** ACL Instructions ****/
+/* ACL Instructions. */
/* dcacl<.f> a,b,c 00111bbb001001010bbbccccccaaaaaa */
{ "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_ARC700, ACL, NPS400, { RA, RB, RC }, { C_F }},
-/**** DPI Instructions ****/
+/* DPI Instructions. */
/* hash dst,src1,src2,width,perm,nonlinear,basemat */
{ "hash", 0x58180000, 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_PERM, NPS_HASH_NONLINEAR, NPS_HASH_BASEMAT }, { 0 }},
@@ -524,7 +524,7 @@ HASH_P(3, 0xC)
/* ldbit<.x2|.x4>.di<.cl> a,[limm,c] 001001100011011X1111CCCCCCAAAAAA */
{ "ldbit", 0x2636f000, 0xff3ef000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
-/**** Pipeline Control Instructions ****/
+/* Pipeline Control Instructions. */
/* schd<.rw|.rd> */
{ "schd", 0x3e6f7004, 0xffffff7f, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SCHD_RW }},
@@ -541,7 +541,7 @@ HASH_P(3, 0xC)
/* hwscd.restore 0,C */
{ "hwschd", 0x3e6f7003, 0xfffff03f, ARC_OPCODE_ARC700, CONTROL, NPS400, { ZA, RC }, { C_NPS_HWS_RESTORE }},
-/**** Load / Store From (0x57f00000 + Offset) Instructions ****/
+/* Load / Store From (0x57f00000 + Offset) Instructions. */
#define XLDST_LIKE(NAME,SUBOP2) \
{ NAME, (0x58000000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_ARC700, MEMORY, NPS400, { NPS_R_DST, BRAKET, NPS_XLDST_UIMM16, BRAKETdup }, { 0 }},
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/4] [ARC] Implement NPS-400 PMU Instructions
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
` (4 preceding siblings ...)
2016-07-25 5:47 ` [PATCH 2/4] [ARC] Add support for address type syntax Graham Markall
@ 2016-07-25 5:47 ` Graham Markall
2016-07-25 5:47 ` [PATCH 3/4] [ARC] Implement NPS-400 BMU instructions Graham Markall
2016-07-27 15:11 ` [PATCH 0/3] [ARC] Begin implementing NPS-400 Accelerator instructions Nick Clifton
7 siblings, 0 replies; 17+ messages in thread
From: Graham Markall @ 2016-07-25 5:47 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
gas/ChangeLog:
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
include/ChangeLog:
* opcode/arc.h: Add PMU to insn_class_t enum.
opcodes/ChangeLog:
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
---
gas/ChangeLog | 5 +++++
gas/testsuite/gas/arc/nps400-8.d | 19 +++++++++++++++++++
gas/testsuite/gas/arc/nps400-8.s | 33 +++++++++++++++++++++++++++++++++
include/ChangeLog | 4 ++++
include/opcode/arc.h | 1 +
opcodes/ChangeLog | 6 ++++++
opcodes/arc-nps400-tbl.h | 31 +++++++++++++++++++++++++++++++
opcodes/arc-opc.c | 7 +++++++
8 files changed, 106 insertions(+)
diff --git a/gas/testsuite/gas/arc/nps400-8.d b/gas/testsuite/gas/arc/nps400-8.d
index f93fd58..9f5344c 100644
--- a/gas/testsuite/gas/arc/nps400-8.d
+++ b/gas/testsuite/gas/arc/nps400-8.d
@@ -50,3 +50,22 @@ Disassembly of section .text:
c0: 3b0d 0f82 ffff ffff efabgt r2,r3,0xffffffff
c8: 380d 0000 efabgt r0,r0,r0
cc: 380d 1247 efabgt r7,r8,r9
+ d0: 3e2f 7020 jobget 0,\[cjid:r0\]
+ d4: 3e2f 71a0 jobget 0,\[cjid:r6\]
+ d8: 3e2f 7021 jobget.cl 0,\[cjid:r0\]
+ dc: 3e2f 71a1 jobget.cl 0,\[cjid:r6\]
+ e0: 3812 003e jobdn 0,\[cjid:r0\],r0,r0
+ e4: 3a12 013e jobdn 0,\[cjid:r2\],r2,r4
+ e8: 3852 003e jobdn 0,\[cjid:r0\],r0,0
+ ec: 3a52 03fe jobdn 0,\[cjid:r2\],r2,0xf
+ f0: 381f 0000 jobalc r0,\[cm:r0\],r0,r0
+ f4: 3a1f 00c1 jobalc r1,\[cm:r2\],r2,r3
+ f8: 385f 0840 jobalc r0,\[cm:r0\],r0,0x1
+ fc: 3a5f 0801 jobalc r1,\[cm:r2\],r2,0x4
+ 100: 385f 0040 sjobalc r0,r0
+ 104: 3d5f 0046 sjobalc r6,r5
+ 108: 381a 0000 jobbgt r0,r0,r0
+ 10c: 3d1a 0182 jobbgt r2,r5,r6
+ 110: 3e6f 70ff cnljob 0
+ 114: 386f 0028 qseq r0,\[r0\]
+ 118: 3a6f 0128 qseq r2,\[r4\]
diff --git a/gas/testsuite/gas/arc/nps400-8.s b/gas/testsuite/gas/arc/nps400-8.s
index ad665fd..1042183 100644
--- a/gas/testsuite/gas/arc/nps400-8.s
+++ b/gas/testsuite/gas/arc/nps400-8.s
@@ -57,3 +57,36 @@
efabgt r2,r3,0xffffffff
efabgt r0,r0,r0
efabgt r7,r8,r9
+
+ ;; jobget
+ jobget 0,[cjid:r0]
+ jobget 0,[cjid:r6]
+ jobget.cl 0,[cjid:r0]
+ jobget.cl 0,[cjid:r6]
+
+ ;; jobdn
+ jobdn 0,[cjid:r0],r0,r0
+ jobdn 0,[cjid:r2],r2,r4
+ jobdn 0,[cjid:r0],r0,0
+ jobdn 0,[cjid:r2],r2,15
+
+ ;; jobalc / sjobalc
+ jobalc r0,[cm:r0],r0,r0
+ jobalc r1,[cm:r2],r2,r3
+ jobalc r0,[cm:r0],r0,1
+ jobalc r1,[cm:r2],r2,4
+ sjobalc r0,r0
+ sjobalc r6,r5
+
+ ;; jobbgt
+
+ jobbgt r0,r0,r0
+ jobbgt r2,r5,r6
+
+ ;; cnljob
+
+ cnljob 0
+
+ ;; qseq
+ qseq r0,[r0]
+ qseq r2,[r4]
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index f5f3331..313fcc1 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -55,6 +55,7 @@ typedef enum
LOGICAL,
MEMORY,
NET,
+ PMU
} insn_class_t;
/* Instruction Subclass. */
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index 4fc337e..4ac038c 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -617,3 +617,34 @@ XLDST_LIKE("xst", 0xe)
/* efabgt dst, src1, src2 */
{ "efabgt", 0x380d0000, 0xf8ff8000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, RC }, { 0 }},
+
+/* PMU Instructions. */
+
+/* jobget<.cl> 0, [cjid:src1] */
+{ "jobget", 0x3e2f7020, 0xfffff03f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RC, BRAKET }, { 0 }},
+
+{ "jobget", 0x3e2f7021, 0xfffff03f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RC, BRAKET }, { C_NPS_CL }},
+
+/* jobdn 0, [cjid:src1], src1, src2 */
+{ "jobdn", 0x3812003e, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* jobdn 0, [cjid:src1], src1, nxt_dst */
+{ "jobdn", 0x3852003e, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RB, BRAKETdup, RBdup, NPS_PMU_NXT_DST }, { 0 }},
+
+/* sjobalc dst, src1 */
+{ "sjobalc", 0x385f0040, 0xf8ff8fc0, ARC_OPCODE_ARC700, PMU, NPS400, { RA, RB }, { 0 }},
+
+/* jobalc dst, [cm:src1], src1, num_job */
+{ "jobalc", 0x385f0800, 0xf8ff8800, ARC_OPCODE_ARC700, PMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_PMU_NUM_JOB }, { 0 }},
+
+/* jobalc dst, [cm:src1], src1, src2 */
+{ "jobalc", 0x381f0000, 0xf8ff8000, ARC_OPCODE_ARC700, PMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* jobbgt dst, src1, src2 */
+{ "jobbgt", 0x381a0000, 0xf8ff0000, ARC_OPCODE_ARC700, PMU, NPS400, { RA, RB, RC }, { 0 }},
+
+/* cnljob 0 */
+{ "cnljob", 0x3e6f70ff, 0xffffffff, ARC_OPCODE_ARC700, PMU, NPS400, { ZA }, { 0 }},
+
+/* qseq dst, [src1] */
+{ "qseq", 0x386f0028, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index beba028..ea4209c 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1139,6 +1139,7 @@ MAKE_1BASED_INSERT_EXTRACT_FUNCS(shift_factor, 9, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bits_to_scramble, 12, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bdlen_max_len, 5, 256, 8)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bd_num_buff, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(pmu_num_job, 6, 4, 2)
static unsigned
insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
@@ -2175,6 +2176,12 @@ const struct arc_operand arc_operands[] =
#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
{ 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
+
+#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
+ { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
+ { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 0/4] Begin implementing NPS-400 Accelerator instructions
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
@ 2016-07-25 5:47 Graham Markall
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
2016-07-25 8:46 ` [PATCH v2 0/4] " Claudiu Zissulescu
7 siblings, 2 replies; 17+ messages in thread
From: Graham Markall @ 2016-07-25 5:47 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
This is a revised series of patches that begin the implementation of
NPS-400 Accelerator instructions by adding support for address types and
implementations of the BMU and PMU Accelerator instructions. Compared
to the original patch set, the following changes are made:
- Additional patch at the beginning to correct the comment format in
opcodes/arc-nps400-tbl.h
- Commas following the last entry of the enums are removed.
- A new macro, ARC_OPERAND_IS_FAKE, used to test if an operand is fake.
Fake operands are those with the fake bit set, excluding brackets and
colons.
- All additional comments follows the GNU style.
- Replace spaces with tabs in debug_exp.
- Add a short description of get_addrtype.
All patches pass `make check` with ARC big- and little-endian.
Graham Markall (4):
[ARC] Change block comments to GNU style
[ARC] Add support for address type syntax
[ARC] Implement NPS-400 BMU instructions
[ARC] Implement NPS-400 PMU Instructions
gas/ChangeLog | 21 ++++++++
gas/config/tc-arc.c | 92 +++++++++++++++++++++++++++++---
gas/testsuite/gas/arc/nps400-8.d | 71 +++++++++++++++++++++++++
gas/testsuite/gas/arc/nps400-8.s | 92 ++++++++++++++++++++++++++++++++
include/ChangeLog | 13 +++++
include/opcode/arc.h | 77 ++++++++++++++++++++++++++-
opcodes/ChangeLog | 26 +++++++++
opcodes/arc-dis.c | 42 +++++++++++++--
opcodes/arc-nps400-tbl.h | 110 ++++++++++++++++++++++++++++++++++++---
opcodes/arc-opc.c | 101 +++++++++++++++++++++++++++++++++++
10 files changed, 627 insertions(+), 18 deletions(-)
create mode 100644 gas/testsuite/gas/arc/nps400-8.d
create mode 100644 gas/testsuite/gas/arc/nps400-8.s
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/4] [ARC] Add support for address type syntax
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
` (3 preceding siblings ...)
2016-07-25 5:47 ` [PATCH 1/4] [ARC] Change block comments to GNU style Graham Markall
@ 2016-07-25 5:47 ` Graham Markall
2016-07-25 5:47 ` [PATCH 4/4] [ARC] Implement NPS-400 PMU Instructions Graham Markall
` (2 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Graham Markall @ 2016-07-25 5:47 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
Some NPS-400 instructions include an address type in an indirect
argument, which includes the name of the address type followed by
a colon, before the usual register or immediate argument. For
example, the syntax of one instruction using an address type is:
bdalc DST, [cm:SRC1], SRC1, SRC2
where the second argument is an offset into the CMEM area given by
SRC1.
In order to add support for address types, there are two main
changes:
1. Addition of the colon operand, which is handled in much the
same way as brackets are already handled.
2. Addition of support for address type operands. There are a
limited number of address types, which are all implemented in this
patch.
- In the assembler, address types are supported in a similar way to
how registers are supported: a token representing an address type
has its X_op field set to O_addrtype, and its X_add_number is an
enum value that represents a particular address type. These values
are added to include/opcode/arc.h in the arc_nps_address_type
enum. In order for X_op and X_add_number to be set correctly,
arc_parse_name is modified to parse address types as well as
registers, using the arc_addrtype_hash to map from address type
names to enum values.
- In the disassembler, colons and address types are printed out
when necessary, as determined by the operands of opcode that has
been matched.
- In libopcodes, the operands for colons and address types are
declared. The insert functions don't actually insert anything
because the address type for an operand is actually determined
by the combination of major opcode and subopcodes of an
instruction. However, they do check that the address type being
inserted matches the specified address type for the operand, in
order to reject opcodes that are invalid for a given address
type.
gas/ChangeLog:
* config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
include/ChangeLog:
* opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
ARC_NUM_ADDRTYPES.
opcodes/ChangeLog:
* arc-dis.c: Add new globals addrtypenames,
addrtypenames_max, and addtypeunknown.
(get_addrtype): New function.
(print_insn_arc): Print colons and address types when
required.
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
define insert and extract functions for all address types.
(arc_operands): Add operands for colon and all address
types.
---
gas/ChangeLog | 11 +++++++
gas/config/tc-arc.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++----
include/ChangeLog | 5 +++
include/opcode/arc.h | 75 +++++++++++++++++++++++++++++++++++++++++-
opcodes/ChangeLog | 10 ++++++
opcodes/arc-dis.c | 42 +++++++++++++++++++++---
opcodes/arc-opc.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++
7 files changed, 311 insertions(+), 11 deletions(-)
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 70886dd..70073f2 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -420,6 +420,9 @@ static struct hash_control *arc_reg_hash;
/* The hash table of aux register symbols. */
static struct hash_control *arc_aux_hash;
+/* The hash table of address types. */
+static struct hash_control *arc_addrtype_hash;
+
/* A table of CPU names and opcode sets. */
static const struct cpu_type
{
@@ -461,6 +464,12 @@ static const struct cpu_type
/* Used to define a bracket as operand in tokens. */
#define O_bracket O_md32
+/* Used to define a colon as an operand in tokens. */
+#define O_colon O_md31
+
+/* Used to define address types in nps400. */
+#define O_addrtype O_md30
+
/* Dummy relocation, to be sorted out. */
#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
@@ -979,6 +988,8 @@ debug_exp (expressionS *t)
case O_logical_or: name = "O_logical_or"; break;
case O_index: name = "O_index"; break;
case O_bracket: name = "O_bracket"; break;
+ case O_colon: name = "O_colon"; break;
+ case O_addrtype: name = "O_addrtype"; break;
}
switch (t->X_md)
@@ -1067,6 +1078,16 @@ tokenize_arguments (char *str,
++num_args;
break;
+ case ':':
+ input_line_pointer++;
+ if (!saw_arg || num_args == ntok)
+ goto err;
+ tok->X_op = O_colon;
+ saw_arg = FALSE;
+ ++tok;
+ ++num_args;
+ break;
+
case '@':
/* We have labels, function names and relocations, all
starting with @ symbol. Sort them out. */
@@ -1693,8 +1714,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
const struct arc_operand *operand = &arc_operands[*opidx];
/* Only take input from real operands. */
- if ((operand->flags & ARC_OPERAND_FAKE)
- && !(operand->flags & ARC_OPERAND_BRAKET))
+ if (ARC_OPERAND_IS_FAKE(operand))
continue;
/* When we expect input, make sure we have it. */
@@ -1704,6 +1724,12 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
/* Match operand type with expression type. */
switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
{
+ case ARC_OPERAND_ADDRTYPE:
+ /* Check to be an address type. */
+ if (tok[tokidx].X_op != O_addrtype)
+ goto match_failed;
+ break;
+
case ARC_OPERAND_IR:
/* Check to be a register. */
if ((tok[tokidx].X_op != O_register
@@ -1755,6 +1781,12 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
goto match_failed;
break;
+ case ARC_OPERAND_COLON:
+ /* Check if colon is also in opcode table as operand. */
+ if (tok[tokidx].X_op != O_colon)
+ goto match_failed;
+ break;
+
case ARC_OPERAND_LIMM:
case ARC_OPERAND_SIGNED:
case ARC_OPERAND_UNSIGNED:
@@ -2461,6 +2493,22 @@ declare_register_set (void)
}
}
+/* Construct a symbol for an address type. */
+
+static void
+declare_addrtype (const char *name, int number)
+{
+ const char *err;
+ symbolS *addrtypeS = symbol_create (name, undefined_section,
+ number, &zero_address_frag);
+
+ err = hash_insert (arc_addrtype_hash, S_GET_NAME(addrtypeS),
+ (void *) addrtypeS);
+ if (err)
+ as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
+ name, err);
+}
+
/* Port-specific assembler initialization. This function is called
once, at assembler startup time. */
@@ -2575,6 +2623,28 @@ md_begin (void)
as_fatal (_("internal error: can't hash aux register '%s': %s"),
auxr->name, retval);
}
+
+ /* Address type declaration. */
+ arc_addrtype_hash = hash_new ();
+ if (arc_addrtype_hash == NULL)
+ as_fatal (_("Virtual memory exhausted"));
+
+ declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
+ declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
+ declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
+ declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
+ declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
+ declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
+ declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
+ declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
+ declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
+ declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
+ declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
+ declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
+ declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
+ declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
+ declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
+ declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
}
/* Write a value out to the object file, using the appropriate
@@ -3254,7 +3324,7 @@ arc_parse_name (const char *name,
if (!assembling_insn)
return FALSE;
- /* Handle only registers. */
+ /* Handle only registers and address types. */
if (e->X_op != O_absent)
return FALSE;
@@ -3265,6 +3335,15 @@ arc_parse_name (const char *name,
e->X_add_number = S_GET_VALUE (sym);
return TRUE;
}
+
+ sym = hash_find (arc_addrtype_hash, name);
+ if (sym)
+ {
+ e->X_op = O_addrtype;
+ e->X_add_number = S_GET_VALUE (sym);
+ return TRUE;
+ }
+
return FALSE;
}
@@ -3726,8 +3805,7 @@ assemble_insn (const struct arc_opcode *opcode,
const struct arc_operand *operand = &arc_operands[*argidx];
const expressionS *t = (const expressionS *) 0;
- if ((operand->flags & ARC_OPERAND_FAKE)
- && !(operand->flags & ARC_OPERAND_BRAKET))
+ if (ARC_OPERAND_IS_FAKE(operand))
continue;
if (operand->flags & ARC_OPERAND_DUPLICATE)
@@ -3764,7 +3842,9 @@ assemble_insn (const struct arc_opcode *opcode,
break;
case O_bracket:
- /* Ignore brackets. */
+ case O_colon:
+ case O_addrtype:
+ /* Ignore brackets, colons, and address types. */
break;
case O_absent:
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index f0fefbb..f3fafe0 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -336,11 +336,24 @@ extern const unsigned arc_NToperand;
/* Mark the braket possition. */
#define ARC_OPERAND_BRAKET 0x1000
+/* Address type operand for NPS400. */
+#define ARC_OPERAND_ADDRTYPE 0x2000
+
+/* Mark the colon position. */
+#define ARC_OPERAND_COLON 0x4000
+
/* Mask for selecting the type for typecheck purposes. */
#define ARC_OPERAND_TYPECHECK_MASK \
(ARC_OPERAND_IR | \
ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \
- ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
+ ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET | \
+ ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
+
+/* Macro to determine if an operand is a fake operand. */
+#define ARC_OPERAND_IS_FAKE(op) \
+ ((operand->flags & ARC_OPERAND_FAKE) \
+ && !((operand->flags & ARC_OPERAND_BRAKET) || \
+ (operand->flags & ARC_OPERAND_COLON)))
/* The flags structure. */
struct arc_flag_operand
@@ -608,6 +621,66 @@ extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
+/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
+ Instruction Set Reference Manual v2.4 for a description of address types. */
+
+typedef enum {
+ /* Addresses in memory. */
+
+ /* Buffer descriptor. */
+ ARC_NPS400_ADDRTYPE_BD,
+
+ /* Job identifier. */
+ ARC_NPS400_ADDRTYPE_JID,
+
+ /* Linked Buffer Descriptor. */
+ ARC_NPS400_ADDRTYPE_LBD,
+
+ /* Multicast Buffer Descriptor. */
+ ARC_NPS400_ADDRTYPE_MBD,
+
+ /* Summarized Address. */
+ ARC_NPS400_ADDRTYPE_SD,
+
+ /* SMEM Security Context Local Memory. */
+ ARC_NPS400_ADDRTYPE_SM,
+
+ /* Extended Address. */
+ ARC_NPS400_ADDRTYPE_XA,
+
+ /* Extended Summarized Address. */
+ ARC_NPS400_ADDRTYPE_XD,
+
+ /* CMEM offset addresses. */
+
+ /* On-demand Counter Descriptor. */
+ ARC_NPS400_ADDRTYPE_CD,
+
+ /* CMEM Buffer Descriptor. */
+ ARC_NPS400_ADDRTYPE_CBD,
+
+ /* CMEM Job Identifier. */
+ ARC_NPS400_ADDRTYPE_CJID,
+
+ /* CMEM Linked Buffer Descriptor. */
+ ARC_NPS400_ADDRTYPE_CLBD,
+
+ /* CMEM Offset. */
+ ARC_NPS400_ADDRTYPE_CM,
+
+ /* CMEM Summarized Address. */
+ ARC_NPS400_ADDRTYPE_CSD,
+
+ /* CMEM Extended Address. */
+ ARC_NPS400_ADDRTYPE_CXA,
+
+ /* CMEM Extended Summarized Address. */
+ ARC_NPS400_ADDRTYPE_CXD
+
+} arc_nps_address_type;
+
+#define ARC_NUM_ADDRTYPES 16
+
#ifdef __cplusplus
}
#endif
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 7b78bdc..a7438fd 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -85,6 +85,16 @@ static const char * const regnames[64] =
"r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
};
+static const char * const addrtypenames[ARC_NUM_ADDRTYPES] =
+{
+ "bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
+ "cd", "cbd", "cjid", "clbd", "cm", "csd", "cxa", "cxd"
+};
+
+static int addrtypenames_max = ARC_NUM_ADDRTYPES - 1;
+
+static const char * const addrtypeunknown = "unknown";
+
/* This structure keeps track which instruction class(es)
should be ignored durring disassembling. */
@@ -653,6 +663,18 @@ get_auxreg (const struct arc_opcode *opcode,
return NULL;
}
+/* Convert a value representing an address type to a string used to refer to
+ the address type in assembly code. */
+
+static const char *
+get_addrtype (int value)
+{
+ if (value < 0 || value > addrtypenames_max)
+ return addrtypeunknown;
+
+ return addrtypenames[value];
+}
+
/* Calculate the instruction length for an instruction starting with MSB
and LSB, the most and least significant byte. The ISA_MASK is used to
filter the instructions considered to only those that are part of the
@@ -1104,8 +1126,7 @@ print_insn_arc (bfd_vma memaddr,
}
/* Only take input from real operands. */
- if ((operand->flags & ARC_OPERAND_FAKE)
- && !(operand->flags & ARC_OPERAND_BRAKET))
+ if (ARC_OPERAND_IS_FAKE(operand))
continue;
if ((operand->flags & ARC_OPERAND_IGNORE)
@@ -1113,6 +1134,12 @@ print_insn_arc (bfd_vma memaddr,
&& value == -1)
continue;
+ if (operand->flags & ARC_OPERAND_COLON)
+ {
+ (*info->fprintf_func) (info->stream, ":");
+ continue;
+ }
+
if (need_comma)
(*info->fprintf_func) (info->stream, ",");
@@ -1124,6 +1151,8 @@ print_insn_arc (bfd_vma memaddr,
continue;
}
+ need_comma = TRUE;
+
/* Print the operand as directed by the flags. */
if (operand->flags & ARC_OPERAND_IR)
{
@@ -1172,6 +1201,13 @@ print_insn_arc (bfd_vma memaddr,
else
(*info->fprintf_func) (info->stream, "%d", value);
}
+ else if (operand->flags & ARC_OPERAND_ADDRTYPE)
+ {
+ const char *addrtype = get_addrtype (value);
+ (*info->fprintf_func) (info->stream, "%s", addrtype);
+ /* A colon follow an address type. */
+ need_comma = FALSE;
+ }
else
{
if (operand->flags & ARC_OPERAND_TRUNCATE
@@ -1189,8 +1225,6 @@ print_insn_arc (bfd_vma memaddr,
(*info->fprintf_func) (info->stream, "%#x", value);
}
}
-
- need_comma = TRUE;
}
return insn_len;
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index ad50ebc..111e01d 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1160,6 +1160,42 @@ extract_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
return value * 16;
}
+#define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \
+static unsigned \
+insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
+ int value ATTRIBUTE_UNUSED, \
+ const char **errmsg ATTRIBUTE_UNUSED) \
+{ \
+ if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
+ *errmsg = _("Invalid address type for operand"); \
+ return insn; \
+} \
+ \
+static int \
+extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ARC_NPS400_ADDRTYPE_##VALUE; \
+}
+
+MAKE_INSERT_NPS_ADDRTYPE(bd, BD)
+MAKE_INSERT_NPS_ADDRTYPE(jid, JID)
+MAKE_INSERT_NPS_ADDRTYPE(lbd, LBD)
+MAKE_INSERT_NPS_ADDRTYPE(mbd, MBD)
+MAKE_INSERT_NPS_ADDRTYPE(sd, SD)
+MAKE_INSERT_NPS_ADDRTYPE(sm, SM)
+MAKE_INSERT_NPS_ADDRTYPE(xa, XA)
+MAKE_INSERT_NPS_ADDRTYPE(xd, XD)
+MAKE_INSERT_NPS_ADDRTYPE(cd, CD)
+MAKE_INSERT_NPS_ADDRTYPE(cbd, CBD)
+MAKE_INSERT_NPS_ADDRTYPE(cjid, CJID)
+MAKE_INSERT_NPS_ADDRTYPE(clbd, CLBD)
+MAKE_INSERT_NPS_ADDRTYPE(cm, CM)
+MAKE_INSERT_NPS_ADDRTYPE(csd, CSD)
+MAKE_INSERT_NPS_ADDRTYPE(cxa, CXA)
+MAKE_INSERT_NPS_ADDRTYPE(cxd, CXD)
+
+
/* Include the generic extract/insert functions. Order is important
as some of the functions present in the .h may be disabled via
defines. */
@@ -2081,6 +2117,57 @@ const struct arc_operand arc_operands[] =
#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
{ 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 },
+
+#define COLON (NPS_E4BY_INDEX3 + 1)
+ { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
+
+#define NPS_BD (COLON + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd },
+
+#define NPS_JID (NPS_BD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid },
+
+#define NPS_LBD (NPS_JID + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd },
+
+#define NPS_MBD (NPS_LBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd },
+
+#define NPS_SD (NPS_MBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd },
+
+#define NPS_SM (NPS_SD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm },
+
+#define NPS_XA (NPS_SM + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa },
+
+#define NPS_XD (NPS_XA + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd },
+
+#define NPS_CD (NPS_XD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd },
+
+#define NPS_CBD (NPS_CD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd },
+
+#define NPS_CJID (NPS_CBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid },
+
+#define NPS_CLBD (NPS_CJID + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd },
+
+#define NPS_CM (NPS_CLBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm },
+
+#define NPS_CSD (NPS_CM + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd },
+
+#define NPS_CXA (NPS_CSD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa },
+
+#define NPS_CXD (NPS_CXA + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/4] [ARC] Implement NPS-400 BMU instructions
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
` (5 preceding siblings ...)
2016-07-25 5:47 ` [PATCH 4/4] [ARC] Implement NPS-400 PMU Instructions Graham Markall
@ 2016-07-25 5:47 ` Graham Markall
2016-07-27 15:11 ` [PATCH 0/3] [ARC] Begin implementing NPS-400 Accelerator instructions Nick Clifton
7 siblings, 0 replies; 17+ messages in thread
From: Graham Markall @ 2016-07-25 5:47 UTC (permalink / raw)
To: binutils; +Cc: claudiu.zissulescu, Graham Markall
gas/ChangeLog:
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
include/ChangeLog:
* opcode/arc.h: Add BMU to insn_class_t enum.
opcodes/ChangeLog:
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
---
gas/ChangeLog | 5 ++++
gas/testsuite/gas/arc/nps400-8.d | 52 ++++++++++++++++++++++++++++++++
gas/testsuite/gas/arc/nps400-8.s | 59 ++++++++++++++++++++++++++++++++++++
include/ChangeLog | 4 +++
include/opcode/arc.h | 1 +
opcodes/ChangeLog | 6 ++++
opcodes/arc-nps400-tbl.h | 65 ++++++++++++++++++++++++++++++++++++++++
opcodes/arc-opc.c | 7 +++++
8 files changed, 199 insertions(+)
create mode 100644 gas/testsuite/gas/arc/nps400-8.d
create mode 100644 gas/testsuite/gas/arc/nps400-8.s
diff --git a/gas/testsuite/gas/arc/nps400-8.d b/gas/testsuite/gas/arc/nps400-8.d
new file mode 100644
index 0000000..f93fd58
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-8.d
@@ -0,0 +1,52 @@
+#as: -mcpu=arc700 -mnps400
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 3810 0000 bdalc r0,\[cm:r0\],r0,r0
+ 4: 3a10 00c1 bdalc r1,\[cm:r2\],r2,r3
+ 8: 3850 0840 bdalc r0,\[cm:r0\],r0,0,0x1
+ c: 3b50 0c42 bdalc r2,\[cm:r3\],r3,0x1,0x1
+ 10: 3c50 0c03 bdalc r3,\[cm:r4\],r4,0x1,0x8
+ 14: 3850 0040 sbdalc r0,r0,0
+ 18: 3c50 0443 sbdalc r3,r4,0x1
+ 1c: 3811 003e bdfre 0,\[cm:r0\],r0,r0
+ 20: 3911 00be bdfre 0,\[cm:r1\],r1,r2
+ 24: 3851 007e bdfre 0,\[cm:r0\],r0,0x1
+ 28: 3a51 003e bdfre 0,\[cm:r2\],r2,0x8
+ 2c: 3851 087e bdfre 0,\[cm:r0\],r0,0,0x1
+ 30: 3e51 083e bdfre 0,\[cm:r6\],r6,0,0x8
+ 34: 3851 0c7e bdfre 0,\[cm:r0\],r0,0x1,0x1
+ 38: 3e51 0c3e bdfre 0,\[cm:r6\],r6,0x1,0x8
+ 3c: 3817 003e sbdfre 0,r0,r0
+ 40: 3917 00be sbdfre 0,r1,r2
+ 44: 3818 003e bdbgt 0,r0,r0
+ 48: 3c18 01be bdbgt 0,r4,r6
+ 4c: 381c 0000 idxalc r0,\[cm:r0\],r0,r0
+ 50: 3a1c 00c1 idxalc r1,\[cm:r2\],r2,r3
+ 54: 3d5c 0884 idxalc r4,\[cm:r5\],r5,0x2
+ 58: 385c 0040 sidxalc r0,r0
+ 5c: 3a5c 0044 sidxalc r4,r2
+ 60: 381e 003e idxfre 0,\[cm:r0\],r0,r0
+ 64: 391e 00be idxfre 0,\[cm:r1\],r1,r2
+ 68: 385e 007e idxfre 0,\[cm:r0\],r0,0x1
+ 6c: 3a5e 003e idxfre 0,\[cm:r2\],r2,0x8
+ 70: 381d 003e sidxfre 0,r0,r0
+ 74: 391d 00be sidxfre 0,r1,r2
+ 78: 3819 003e idxbgt 0,r0,r0
+ 7c: 3f19 023e idxbgt 0,r7,r8
+ 80: 3e0d 703e 0000 0000 efabgt 0,0,r0
+ 88: 3e0d 70fe ffff ffff efabgt 0,0xffffffff,r3
+ 90: 380d 0fbe 0000 0000 efabgt 0,r0,0
+ 98: 3c0d 0fbe ffff ffff efabgt 0,r4,0xffffffff
+ a0: 380d 003e efabgt 0,r0,r0
+ a4: 3f0d 023e efabgt 0,r7,r8
+ a8: 3e0d 7000 0000 0000 efabgt r0,0,r0
+ b0: 3e0d 7184 ffff ffff efabgt r4,0xffffffff,r6
+ b8: 380d 0f80 0000 0000 efabgt r0,r0,0
+ c0: 3b0d 0f82 ffff ffff efabgt r2,r3,0xffffffff
+ c8: 380d 0000 efabgt r0,r0,r0
+ cc: 380d 1247 efabgt r7,r8,r9
diff --git a/gas/testsuite/gas/arc/nps400-8.s b/gas/testsuite/gas/arc/nps400-8.s
new file mode 100644
index 0000000..ad665fd
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-8.s
@@ -0,0 +1,59 @@
+ .text
+
+ ;; bdalc / sbdalc
+ bdalc r0,[cm:r0],r0,r0
+ bdalc r1,[cm:r2],r2,r3
+ bdalc r0,[cm:r0],r0,0,1
+ bdalc r2,[cm:r3],r3,1,1
+ bdalc r3,[cm:r4],r4,1,8
+ sbdalc r0, r0, 0
+ sbdalc r3, r4, 1
+
+ ;; bdfre / sbdfre
+ bdfre 0,[cm:r0],r0,r0
+ bdfre 0,[cm:r1],r1,r2
+ bdfre 0,[cm:r0],r0,1
+ bdfre 0,[cm:r2],r2,8
+ bdfre 0,[cm:r0],r0,0,1
+ bdfre 0,[cm:r6],r6,0,8
+ bdfre 0,[cm:r0],r0,1,1
+ bdfre 0,[cm:r6],r6,1,8
+ sbdfre 0, r0, r0
+ sbdfre 0, r1, r2
+
+ ;; bdbgt
+ bdbgt 0,r0,r0
+ bdbgt 0,r4,r6
+
+ ;; idxalc / sidxalc
+ idxalc r0,[cm:r0],r0,r0
+ idxalc r1,[cm:r2],r2,r3
+ idxalc r4,[cm:r5],r5,2
+ sidxalc r0,r0
+ sidxalc r4,r2
+
+ ;; idxfre / sidxfre
+ idxfre 0,[cm:r0],r0,r0
+ idxfre 0,[cm:r1],r1,r2
+ idxfre 0,[cm:r0],r0,1
+ idxfre 0,[cm:r2],r2,8
+ sidxfre 0, r0, r0
+ sidxfre 0, r1, r2
+
+ ;; idxbgt
+ idxbgt 0,r0,r0
+ idxbgt 0,r7,r8
+
+ ;; efabgt
+ efabgt 0,0x0,r0
+ efabgt 0,0xffffffff,r3
+ efabgt 0,r0,0x0
+ efabgt 0,r4,0xffffffff
+ efabgt 0,r0,r0
+ efabgt 0,r7,r8
+ efabgt r0,0x0,r0
+ efabgt r4,0xffffffff,r6
+ efabgt r0,r0,0x0
+ efabgt r2,r3,0xffffffff
+ efabgt r0,r0,r0
+ efabgt r7,r8,r9
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index f3fafe0..f5f3331 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -43,6 +43,7 @@ typedef enum
ARITH,
AUXREG,
BITOP,
+ BMU,
BRANCH,
CONTROL,
DPI,
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index f3bd81b..4fc337e 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -552,3 +552,68 @@ XLDST_LIKE("xld", 0xa)
XLDST_LIKE("xstb", 0xc)
XLDST_LIKE("xstw", 0xd)
XLDST_LIKE("xst", 0xe)
+
+/* BMU Instructions. */
+
+/* sbdalc dst, src1, type */
+{ "sbdalc", 0x38500040, 0xf8ff09c0, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, NPS_BD_TYPE }, { 0 }},
+
+/* bdalc dst, [cm:src1], src1, src2 */
+{ "bdalc", 0x38100000, 0xf8ff0000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* bdalc dst, [cm:src1], src1, type, num_buff */
+{ "bdalc", 0x38500800, 0xf8ff0800, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BD_TYPE, NPS_BMU_NUM }, { 0 }},
+
+/* sbdfre 0, src1, src2 */
+{ "sbdfre", 0x3817003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* bdfre 0, [cm:src1], src1, src2 */
+{ "bdfre", 0x3811003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* bdfre 0, [cm:src1], src1, type, num_buff */
+{ "bdfre", 0x3851083e, 0xf8ff083f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BD_TYPE, NPS_BMU_NUM }, { 0 }},
+
+/* bdfre 0, [cm:src1], src1, num_buff */
+{ "bdfre", 0x3851003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }},
+
+/* bdbgt 0, src1, src2 */
+{ "bdbgt", 0x3818003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* sidxalc dst, src1 */
+{ "sidxalc", 0x385c0040, 0xf8ff0040, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB }, { 0 }},
+
+/* idxalc dst, [cm:src1], src1, src2 */
+{ "idxalc", 0x381c0000, 0xf8ff0000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* idxalc dst, [cm:src1], src1, num_idx */
+{ "idxalc", 0x385c0800, 0xf8ff0800, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }},
+
+/* sidxfre 0, src1, src2 */
+{ "sidxfre", 0x381d003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* idxfre 0, [cm:src1], src1, src2 */
+{ "idxfre", 0x381e003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }},
+
+/* idxfre 0, [cm:src1], src1, num_buff */
+{ "idxfre", 0x385e003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }},
+
+/* idxbgt 0, src1, src2 */
+{ "idxbgt", 0x3819003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* efabgt 0, limm, src2 */
+{ "efabgt", 0x3e0d703e, 0xfffff03f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, LIMM, RC }, { 0 }},
+
+/* efabgt 0, src1, limm */
+{ "efabgt", 0x380d0fbe, 0xf8ff80ff, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, LIMM }, { 0 }},
+
+/* efabgt 0, src1, src2 */
+{ "efabgt", 0x380d003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }},
+
+/* efabgt dst, limm, src2 */
+{ "efabgt", 0x3e0d7000, 0xfffff000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, LIMM, RC }, { 0 }},
+
+/* efabgt dst, src1, limm */
+{ "efabgt", 0x380d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, LIMM }, { 0 }},
+
+/* efabgt dst, src1, src2 */
+{ "efabgt", 0x380d0000, 0xf8ff8000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, RC }, { 0 }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 111e01d..beba028 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1138,6 +1138,7 @@ MAKE_1BASED_INSERT_EXTRACT_FUNCS(field_size, 6, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(shift_factor, 9, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bits_to_scramble, 12, 8, 3)
MAKE_1BASED_INSERT_EXTRACT_FUNCS(bdlen_max_len, 5, 256, 8)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(bd_num_buff, 6, 8, 3)
static unsigned
insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
@@ -2168,6 +2169,12 @@ const struct arc_operand arc_operands[] =
#define NPS_CXD (NPS_CXA + 1)
{ 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
+
+#define NPS_BD_TYPE (NPS_CXD + 1)
+ { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
+ { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/3] [ARC] Add support for address type syntax
2016-07-22 16:53 ` Claudiu Zissulescu
@ 2016-07-25 5:50 ` Graham Markall
0 siblings, 0 replies; 17+ messages in thread
From: Graham Markall @ 2016-07-25 5:50 UTC (permalink / raw)
To: Claudiu Zissulescu, binutils; +Cc: claudiu.zissulescu
[-- Attachment #1.1: Type: text/plain, Size: 2733 bytes --]
Hi Claudiu,
Many thanks for the review - I have posted a new series of patches in
which I have tried to address your comments on all three patches:
https://sourceware.org/ml/binutils/2016-07/msg00324.html
Best regards,
Graham.
On 22/07/16 17:52, Claudiu Zissulescu wrote:
> Hi,
>>
>> +/* Used to define a colon as an operand in tokens */
>
> Dot space space.
>
>> +#define O_colon O_md31
>> +
>> +/* Used to define address types in nps400 */
>
> Same here.
>
>> +#define O_addrtype O_md30
>> +
>> /* Dummy relocation, to be sorted out. */
>> #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
>>
>> @@ -979,6 +988,8 @@ debug_exp (expressionS *t)
>> case O_logical_or: name = "O_logical_or"; break;
>> case O_index: name = "O_index"; break;
>> case O_bracket: name = "O_bracket"; break;
>> + case O_colon: name = "O_colon"; break;
>> + case O_addrtype: name = "O_addrtype"; break;
>
> Groups of 8 spaces needs to be replaced by tabs.
>> if ((operand->flags & ARC_OPERAND_FAKE)
>> - && !(operand->flags & ARC_OPERAND_BRAKET))
>> + && !((operand->flags & ARC_OPERAND_BRAKET) ||
>> + (operand->flags & ARC_OPERAND_COLON)))
>
> May make sense to craft a macro here, as this construction is used
> multiple time.
>
>> + case ARC_OPERAND_ADDRTYPE:
>> + /* Check to be an address type */
>
> Dot space space.
>
>> + case ARC_OPERAND_COLON:
>> + /* Check if colon is also in opcode table as operand */
>
> Same here.
>
>> - && !(operand->flags & ARC_OPERAND_BRAKET))
>> + && !((operand->flags & ARC_OPERAND_BRAKET) ||
>> + (operand->flags & ARC_OPERAND_COLON)))
>
> Here you can reuse the macro above suggested.
>
>> +/* Address type operand for NPS400 */
>
> Dot space space.
>
>> +#define ARC_OPERAND_ADDRTYPE 0x2000
>> +
>> +/* Mark the colon position */
>
> Same here.
>
>> + /* CMEM Extended Summarized Address. */
>> + ARC_NPS400_ADDRTYPE_CXD,
>
> This last comma may trigger warnings with old compilers.
>
>>
>> +static const char *
>
> Missing a short description of the function.
>
>> +get_addrtype (int value)
>> +{
>> + if (value < 0 || value > addrtypenames_max)
>> + return addrtypeunknown;
>> +
>> + return addrtypenames[value];
>> +}
>> - && !(operand->flags & ARC_OPERAND_BRAKET))
>> + && !((operand->flags & ARC_OPERAND_BRAKET) ||
>> + (operand->flags & ARC_OPERAND_COLON)))
>
> Macro used here.
>
> Thanks,
> Claudiu
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v2 0/4] Begin implementing NPS-400 Accelerator instructions
2016-07-25 5:47 [PATCH v2 0/4] Begin implementing NPS-400 Accelerator instructions Graham Markall
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
@ 2016-07-25 8:46 ` Claudiu Zissulescu
1 sibling, 0 replies; 17+ messages in thread
From: Claudiu Zissulescu @ 2016-07-25 8:46 UTC (permalink / raw)
To: Graham Markall, binutils; +Cc: claudiu.zissulescu
> Graham Markall (4):
> [ARC] Change block comments to GNU style
> [ARC] Add support for address type syntax
> [ARC] Implement NPS-400 BMU instructions
> [ARC] Implement NPS-400 PMU Instructions
>
> gas/ChangeLog | 21 ++++++++
> gas/config/tc-arc.c | 92 +++++++++++++++++++++++++++++---
> gas/testsuite/gas/arc/nps400-8.d | 71 +++++++++++++++++++++++++
> gas/testsuite/gas/arc/nps400-8.s | 92
> ++++++++++++++++++++++++++++++++
> include/ChangeLog | 13 +++++
> include/opcode/arc.h | 77 ++++++++++++++++++++++++++-
> opcodes/ChangeLog | 26 +++++++++
> opcodes/arc-dis.c | 42 +++++++++++++--
> opcodes/arc-nps400-tbl.h | 110
> ++++++++++++++++++++++++++++++++++++---
> opcodes/arc-opc.c | 101
> +++++++++++++++++++++++++++++++++++
> 10 files changed, 627 insertions(+), 18 deletions(-)
> create mode 100644 gas/testsuite/gas/arc/nps400-8.d
> create mode 100644 gas/testsuite/gas/arc/nps400-8.s
It looks good from my side.
Best,
Claudiu
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/3] [ARC] Begin implementing NPS-400 Accelerator instructions
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
` (6 preceding siblings ...)
2016-07-25 5:47 ` [PATCH 3/4] [ARC] Implement NPS-400 BMU instructions Graham Markall
@ 2016-07-27 15:11 ` Nick Clifton
7 siblings, 0 replies; 17+ messages in thread
From: Nick Clifton @ 2016-07-27 15:11 UTC (permalink / raw)
To: Graham Markall, binutils; +Cc: claudiu.zissulescu
Hi Graham,
I have applied the revised version of your patch series. (All 4 of them).
There were a couple of very minor formatting issues which I fixed as I went
through the patches, but in all they were of a very high quality and I had
no problems applying or testing them.
Cheers
Nick
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2016-07-27 15:11 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
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2016-07-25 5:47 [PATCH v2 0/4] Begin implementing NPS-400 Accelerator instructions Graham Markall
2016-07-22 14:02 ` [PATCH 0/3] [ARC] " Graham Markall
2016-07-22 14:02 ` [PATCH 3/3] [ARC] Implement NPS-400 PMU Instructions Graham Markall
2016-07-22 16:41 ` Claudiu Zissulescu
2016-07-22 14:02 ` [PATCH 2/3] [ARC] Implement NPS-400 BMU instructions Graham Markall
2016-07-22 16:43 ` Claudiu Zissulescu
2016-07-22 17:00 ` Graham Markall
2016-07-22 17:14 ` Claudiu Zissulescu
2016-07-22 14:02 ` [PATCH 1/3] [ARC] Add support for address type syntax Graham Markall
2016-07-22 16:53 ` Claudiu Zissulescu
2016-07-25 5:50 ` Graham Markall
2016-07-25 5:47 ` [PATCH 1/4] [ARC] Change block comments to GNU style Graham Markall
2016-07-25 5:47 ` [PATCH 2/4] [ARC] Add support for address type syntax Graham Markall
2016-07-25 5:47 ` [PATCH 4/4] [ARC] Implement NPS-400 PMU Instructions Graham Markall
2016-07-25 5:47 ` [PATCH 3/4] [ARC] Implement NPS-400 BMU instructions Graham Markall
2016-07-27 15:11 ` [PATCH 0/3] [ARC] Begin implementing NPS-400 Accelerator instructions Nick Clifton
2016-07-25 8:46 ` [PATCH v2 0/4] " Claudiu Zissulescu
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