From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 74737 invoked by alias); 1 May 2019 17:15:53 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 74726 invoked by uid 89); 1 May 2019 17:15:53 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:15:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 66BC380D for ; Wed, 1 May 2019 10:15:48 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DFC493F719 for ; Wed, 1 May 2019 10:15:47 -0700 (PDT) Subject: [PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: Date: Wed, 01 May 2019 17:15:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------3D57CC46DF9BCA832504BDAE" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00052.txt.bz2 This is a multi-part message in MIME format. --------------3D57CC46DF9BCA832504BDAE Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1071 Hi, This patch adds support for MVE instructions VMLA, VMUL, VQADD, and VQSUB. gas/ChangeLog: 2019-05-01 Andre Vieira * config/tc-arm.c (enum operand_parse_code): New operand. (parse_operands): Handle new operand. (mve_encode_qqr): Handle new instructions. (do_neon_dyadic_i64_su): Accept MVE variants. (neon_dyadic_misc): Likewise. (do_neon_mac_maybe_scalar): Likewise. (do_neon_mul): Likewise. (insns): Change to accept MVE variants. * testsuite/gas/arm/mve-vmla-bad.d: New test. * testsuite/gas/arm/mve-vmla-bad.l: New test. * testsuite/gas/arm/mve-vmla-bad.s: New test. * testsuite/gas/arm/mve-vmul-bad-1.d: New test. * testsuite/gas/arm/mve-vmul-bad-1.l: New test. * testsuite/gas/arm/mve-vmul-bad-1.s: New test. * testsuite/gas/arm/mve-vmul-bad-2.d: New test. * testsuite/gas/arm/mve-vmul-bad-2.l: New test. * testsuite/gas/arm/mve-vmul-bad-2.s: New test. * testsuite/gas/arm/mve-vqaddsub-bad.d: New test. * testsuite/gas/arm/mve-vqaddsub-bad.l: New test. * testsuite/gas/arm/mve-vqaddsub-bad.s: New test. --------------3D57CC46DF9BCA832504BDAE Content-Type: text/x-patch; name="23.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="23.patch" Content-length: 24543 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 77a68067f95ddcbd4b31b5309ea833dd875d063c..dd02a8e5a790f170d1f87ae1c36dd5e7e5a4827a 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -6954,6 +6954,8 @@ enum operand_parse_code OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register. */ + OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon + scalar, or ARM register. */ OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */ OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ @@ -7328,6 +7330,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) } break; + case OP_RNSDQ_RNSC_MQ_RR: + po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq); + break; + try_rnsdq_rnsc_mq: case OP_RNSDQ_RNSC_MQ: po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc); break; @@ -15902,6 +15908,9 @@ mve_encode_qqr (int size, int U, int fp) /* vsub. */ else if (((unsigned)inst.instruction) == 0x200d00) inst.instruction = 0xee301f40; + /* vmul. */ + else if (((unsigned)inst.instruction) == 0x1000d10) + inst.instruction = 0xee310e60; /* Setting size which is 1 for F16 and 0 for F32. */ inst.instruction |= (size == 16) << 28; @@ -15920,6 +15929,18 @@ mve_encode_qqr (int size, int U, int fp) /* vhsub. */ else if (((unsigned)inst.instruction) == 0x200) inst.instruction = 0xee001f40; + /* vmla. */ + else if (((unsigned)inst.instruction) == 0x900) + inst.instruction = 0xee010e40; + /* vmul. */ + else if (((unsigned)inst.instruction) == 0x910) + inst.instruction = 0xee011e60; + /* vqadd. */ + else if (((unsigned)inst.instruction) == 0x10) + inst.instruction = 0xee000f60; + /* vqsub. */ + else if (((unsigned)inst.instruction) == 0x210) + inst.instruction = 0xee001f60; /* Set U-bit. */ inst.instruction |= U << 28; @@ -16148,10 +16169,24 @@ do_neon_dyadic_i_su (void) static void do_neon_dyadic_i64_su (void) { - enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); - struct neon_type_el et = neon_check_type (3, rs, - N_EQK, N_EQK, N_SU_ALL | N_KEY); - neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); + if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) + return; + enum neon_shape rs; + struct neon_type_el et; + if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) + { + rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); + et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); + } + else + { + rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY); + } + if (rs == NS_QQR) + mve_encode_qqr (et.size, et.type == NT_unsigned, 0); + else + neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); } static void @@ -16445,7 +16480,7 @@ neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, { NEON_ENCODE (INTEGER, inst); if (rs == NS_QQR) - mve_encode_qqr (et.size, 0, 0); + mve_encode_qqr (et.size, et.type == ubit_meaning, 0); else neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); } @@ -16970,19 +17005,30 @@ do_neon_mac_maybe_scalar (void) if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) return; - if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) return; if (inst.operands[2].isscalar) { + constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY); NEON_ENCODE (SCALAR, inst); neon_mul_mac (et, neon_quad (rs)); } + else if (!inst.operands[2].isvec) + { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); + + enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); + neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); + + neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0); + } else { + constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); /* The "untyped" case can't happen. Do this to stop the "U" bit being affected if we specify unsigned args. */ neon_dyadic_misc (NT_untyped, N_IF_32, 0); @@ -17050,13 +17096,34 @@ do_neon_mul (void) if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) return; - if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) return; if (inst.operands[2].isscalar) - do_neon_mac_maybe_scalar (); + { + constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); + do_neon_mac_maybe_scalar (); + } else - neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0); + { + if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) + { + enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY); + if (et.type == NT_float) + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), + BAD_FPU); + + neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0); + } + else + { + constraint (!inst.operands[2].isvec, BAD_FPU); + neon_dyadic_misc (NT_poly, + N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0); + } + } } static void @@ -23779,8 +23846,6 @@ static const struct asm_opcode insns[] = NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), /* Mnemonics shared by Neon and VFP. */ - nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), - nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), @@ -23834,9 +23899,7 @@ static const struct asm_opcode insns[] = NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ - NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), - NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), @@ -24604,6 +24667,8 @@ static const struct asm_opcode insns[] = #define ARM_VARIANT & fpu_vfp_ext_v1 #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v6t2 + mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar), + mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul), mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), @@ -24664,6 +24729,8 @@ static const struct asm_opcode insns[] = MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), + MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su), + MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su), #undef ARM_VARIANT #define ARM_VARIANT & arm_ext_v8_3 diff --git a/gas/testsuite/gas/arm/mve-vmla-bad.d b/gas/testsuite/gas/arm/mve-vmla-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..a5bc0634cffe01d2275318afb9d54ccb19592ff1 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmla-bad.d @@ -0,0 +1,5 @@ +#name: Bad MVE VMLA instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmla-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmla-bad.l b/gas/testsuite/gas/arm/mve-vmla-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..12ed8f17abe0b7a1fc5b0072dd6ff6de08737c66 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmla-bad.l @@ -0,0 +1,17 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmla.f16 q0,q1,r2' +[^:]*:11: Error: bad type in SIMD instruction -- `vmla.s64 q0,q1,r2' +[^:]*:12: Error: selected FPU does not support instruction -- `vmla.s32 q0,q1,q2' +[^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' +[^:]*:18: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' +[^:]*:20: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmlat.u16 q0,q1,r2' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vmla.u16 q0,q1,r2' diff --git a/gas/testsuite/gas/arm/mve-vmla-bad.s b/gas/testsuite/gas/arm/mve-vmla-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..65de902fea4877a31d95b2803c5c7dbad1fe83f3 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmla-bad.s @@ -0,0 +1,23 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vmla.s16 q0, q1, r2 +.endr +.endm + +.syntax unified +.thumb +vmla.f16 q0, q1, r2 +vmla.s64 q0, q1, r2 +vmla.s32 q0, q1, q2 +vmla.s32 q0, q1, sp +vmla.s32 q0, q1, pc +cond +it eq +vmlaeq.u16 q0, q1, r2 +vmlaeq.u16 q0, q1, r2 +vpst +vmlaeq.u16 q0, q1, r2 +vmlat.u16 q0, q1, r2 +vpst +vmla.u16 q0, q1, r2 diff --git a/gas/testsuite/gas/arm/mve-vmul-bad-1.d b/gas/testsuite/gas/arm/mve-vmul-bad-1.d new file mode 100644 index 0000000000000000000000000000000000000000..1e3dc46b8650036990c3dafb53045f0a2c7e9130 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmul-bad-1.d @@ -0,0 +1,5 @@ +#name: bad MVE VMUL instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vmul-bad-1.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmul-bad-1.l b/gas/testsuite/gas/arm/mve-vmul-bad-1.l new file mode 100644 index 0000000000000000000000000000000000000000..88a86caf45feb6f74a09b8be9293c72476acd68f --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmul-bad-1.l @@ -0,0 +1,31 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: selected FPU does not support instruction -- `vmul.f16 q0,q1,q2' +[^:]*:11: Error: selected FPU does not support instruction -- `vmul.f16 q0,q1,r2' +[^:]*:12: Error: selected FPU does not support instruction -- `vmul.f32 q0,q1,q2' +[^:]*:13: Error: selected FPU does not support instruction -- `vmul.f32 q0,q1,r2' +[^:]*:14: Error: bad type in SIMD instruction -- `vmul.i64 q0,q1,q2' +[^:]*:15: Error: bad type in SIMD instruction -- `vmul.i64 q0,q1,r2' +[^:]*:16: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:17: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:21: Error: syntax error -- `vmuleq.i32 q0,q1,q2' +[^:]*:22: Error: syntax error -- `vmuleq.i32 q0,q1,q2' +[^:]*:24: Error: syntax error -- `vmuleq.i32 q0,q1,q2' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vmult.i32 q0,q1,q2' +[^:]*:27: Error: instruction missing MVE vector predication code -- `vmul.i32 q0,q1,q2' +[^:]*:29: Error: syntax error -- `vmuleq.i32 q0,q1,r2' +[^:]*:30: Error: syntax error -- `vmuleq.i32 q0,q1,r2' +[^:]*:32: Error: syntax error -- `vmuleq.i32 q0,q1,r2' +[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vmult.i32 q0,q1,r2' +[^:]*:35: Error: instruction missing MVE vector predication code -- `vmul.i32 q0,q1,r2' diff --git a/gas/testsuite/gas/arm/mve-vmul-bad-1.s b/gas/testsuite/gas/arm/mve-vmul-bad-1.s new file mode 100644 index 0000000000000000000000000000000000000000..7897a1ab1037b28907de6c92f1c451f1eed2dd9f --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmul-bad-1.s @@ -0,0 +1,35 @@ +.macro cond lastreg +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vmul.i16 q0, q1, \lastreg +.endr +.endm + +.syntax unified +.thumb +vmul.f16 q0, q1, q2 +vmul.f16 q0, q1, r2 +vmul.f32 q0, q1, q2 +vmul.f32 q0, q1, r2 +vmul.i64 q0, q1, q2 +vmul.i64 q0, q1, r2 +vmul.i8 q0, q1, pc +vmul.i8 q0, q1, sp +cond q2 +cond r2 +it eq +vmuleq.i32 q0, q1, q2 +vmuleq.i32 q0, q1, q2 +vpst +vmuleq.i32 q0, q1, q2 +vmult.i32 q0, q1, q2 +vpst +vmul.i32 q0, q1, q2 +it eq +vmuleq.i32 q0, q1, r2 +vmuleq.i32 q0, q1, r2 +vpst +vmuleq.i32 q0, q1, r2 +vmult.i32 q0, q1, r2 +vpst +vmul.i32 q0, q1, r2 diff --git a/gas/testsuite/gas/arm/mve-vmul-bad-2.d b/gas/testsuite/gas/arm/mve-vmul-bad-2.d new file mode 100644 index 0000000000000000000000000000000000000000..27e639956e2d969a41691beba523a5f287325d5b --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmul-bad-2.d @@ -0,0 +1,5 @@ +#name: bad MVE FP VMUL instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmul-bad-2.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmul-bad-2.l b/gas/testsuite/gas/arm/mve-vmul-bad-2.l new file mode 100644 index 0000000000000000000000000000000000000000..a804da8be25f5ca508fb1a4b127d3bb0b9950bdc --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmul-bad-2.l @@ -0,0 +1,47 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmul.f64 q0,q1,q2' +[^:]*:11: Error: bad type in SIMD instruction -- `vmul.f64 q0,q1,r2' +[^:]*:12: Error: bad type in SIMD instruction -- `vmul.i64 q0,q1,q2' +[^:]*:13: Error: bad type in SIMD instruction -- `vmul.i64 q0,q1,r2' +[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:15: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:16: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:17: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:18: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:21: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:27: Error: syntax error -- `vmuleq.f16 q0,q1,q2' +[^:]*:28: Error: syntax error -- `vmuleq.f16 q0,q1,q2' +[^:]*:30: Error: syntax error -- `vmuleq.f16 q0,q1,q2' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vmult.f16 q0,q1,q2' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vmul.f16 q0,q1,q2' +[^:]*:35: Error: syntax error -- `vmuleq.f32 q0,q1,r2' +[^:]*:36: Error: syntax error -- `vmuleq.f32 q0,q1,r2' +[^:]*:38: Error: syntax error -- `vmuleq.f32 q0,q1,r2' +[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vmult.f32 q0,q1,r2' +[^:]*:41: Error: instruction missing MVE vector predication code -- `vmul.f32 q0,q1,r2' diff --git a/gas/testsuite/gas/arm/mve-vmul-bad-2.s b/gas/testsuite/gas/arm/mve-vmul-bad-2.s new file mode 100644 index 0000000000000000000000000000000000000000..b5ed4ebff02853ace6030242a413dfe5fd9b0053 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmul-bad-2.s @@ -0,0 +1,41 @@ +.macro cond size, lastreg +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vmul.\size q0, q1, \lastreg +.endr +.endm + +.syntax unified +.thumb +vmul.f64 q0, q1, q2 +vmul.f64 q0, q1, r2 +vmul.i64 q0, q1, q2 +vmul.i64 q0, q1, r2 +vmul.f16 q0, q1, pc +vmul.f16 q0, q1, pc +vmul.f16 q0, q1, sp +vmul.f16 q0, q1, sp +vmul.i32 q0, q1, pc +vmul.i32 q0, q1, pc +vmul.i32 q0, q1, sp +vmul.i32 q0, q1, sp +cond i8 q2 +cond i16 r2 +cond f16 q2 +cond f32 r2 +it eq +vmuleq.f16 q0, q1, q2 +vmuleq.f16 q0, q1, q2 +vpst +vmuleq.f16 q0, q1, q2 +vmult.f16 q0, q1, q2 +vpst +vmul.f16 q0, q1, q2 +it eq +vmuleq.f32 q0, q1, r2 +vmuleq.f32 q0, q1, r2 +vpst +vmuleq.f32 q0, q1, r2 +vmult.f32 q0, q1, r2 +vpst +vmul.f32 q0, q1, r2 diff --git a/gas/testsuite/gas/arm/mve-vqaddsub-bad.d b/gas/testsuite/gas/arm/mve-vqaddsub-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..f37595e49055486c10a5b0f71e8f45e90373b775 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vqaddsub-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VQADD and VQSUB instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vqaddsub-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vqaddsub-bad.l b/gas/testsuite/gas/arm/mve-vqaddsub-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..1869371c0c9bf215496aab815e35e7e66ecf2ac8 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vqaddsub-bad.l @@ -0,0 +1,57 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vqadd.s64 q0,q1,q2' +[^:]*:11: Error: bad type in SIMD instruction -- `vqsub.u64 q0,q1,q2' +[^:]*:12: Error: bad type in SIMD instruction -- `vqadd.s64 q0,q1,r2' +[^:]*:13: Error: bad type in SIMD instruction -- `vqsub.s64 q0,q1,r2' +[^:]*:14: Error: bad type in SIMD instruction -- `vqadd.f32 q0,q1,q2' +[^:]*:15: Error: bad type in SIMD instruction -- `vqsub.f32 q0,q1,q2' +[^:]*:16: Error: bad type in SIMD instruction -- `vqadd.f32 q0,q1,r2' +[^:]*:17: Error: bad type in SIMD instruction -- `vqsub.f32 q0,q1,r2' +[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:27: Error: syntax error -- `vqaddeq.s32 q0,q1,q2' +[^:]*:28: Error: syntax error -- `vqaddeq.s32 q0,q1,q2' +[^:]*:30: Error: syntax error -- `vqaddeq.s32 q0,q1,q2' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vqaddt.s32 q0,q1,q2' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vqadd.s32 q0,q1,q2' +[^:]*:35: Error: syntax error -- `vqsubeq.s32 q0,q1,q2' +[^:]*:36: Error: syntax error -- `vqsubeq.s32 q0,q1,q2' +[^:]*:38: Error: syntax error -- `vqsubeq.s32 q0,q1,q2' +[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vqsubt.s32 q0,q1,q2' +[^:]*:41: Error: instruction missing MVE vector predication code -- `vqsub.s32 q0,q1,q2' +[^:]*:43: Error: syntax error -- `vqaddeq.s32 q0,q1,r2' +[^:]*:44: Error: syntax error -- `vqaddeq.s32 q0,q1,r2' +[^:]*:46: Error: syntax error -- `vqaddeq.s32 q0,q1,r2' +[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vqaddt.s32 q0,q1,r2' +[^:]*:49: Error: instruction missing MVE vector predication code -- `vqadd.s32 q0,q1,r2' +[^:]*:51: Error: syntax error -- `vqsubeq.s32 q0,q1,r2' +[^:]*:52: Error: syntax error -- `vqsubeq.s32 q0,q1,r2' +[^:]*:54: Error: syntax error -- `vqsubeq.s32 q0,q1,r2' +[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vqsubt.s32 q0,q1,r2' +[^:]*:57: Error: instruction missing MVE vector predication code -- `vqsub.s32 q0,q1,r2' diff --git a/gas/testsuite/gas/arm/mve-vqaddsub-bad.s b/gas/testsuite/gas/arm/mve-vqaddsub-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..d5303173c6c940834940206739257c8a08e83965 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vqaddsub-bad.s @@ -0,0 +1,57 @@ +.macro cond op, lastop +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s16 q0, q1, \lastop +.endr +.endm + +.syntax unified +.thumb +vqadd.s64 q0, q1, q2 +vqsub.u64 q0, q1, q2 +vqadd.s64 q0, q1, r2 +vqsub.s64 q0, q1, r2 +vqadd.f32 q0, q1, q2 +vqsub.f32 q0, q1, q2 +vqadd.f32 q0, q1, r2 +vqsub.f32 q0, q1, r2 +vqadd.s16 q0, q1, sp +vqadd.s16 q0, q1, pc +vqsub.s16 q0, q1, sp +vqsub.s16 q0, q1, pc +cond vqadd q2 +cond vqadd r2 +cond vqsub q2 +cond vqsub r2 +it eq +vqaddeq.s32 q0, q1, q2 +vqaddeq.s32 q0, q1, q2 +vpst +vqaddeq.s32 q0, q1, q2 +vqaddt.s32 q0, q1, q2 +vpst +vqadd.s32 q0, q1, q2 +it eq +vqsubeq.s32 q0, q1, q2 +vqsubeq.s32 q0, q1, q2 +vpst +vqsubeq.s32 q0, q1, q2 +vqsubt.s32 q0, q1, q2 +vpst +vqsub.s32 q0, q1, q2 +it eq +vqaddeq.s32 q0, q1, r2 +vqaddeq.s32 q0, q1, r2 +vpst +vqaddeq.s32 q0, q1, r2 +vqaddt.s32 q0, q1, r2 +vpst +vqadd.s32 q0, q1, r2 +it eq +vqsubeq.s32 q0, q1, r2 +vqsubeq.s32 q0, q1, r2 +vpst +vqsubeq.s32 q0, q1, r2 +vqsubt.s32 q0, q1, r2 +vpst +vqsub.s32 q0, q1, r2 --------------3D57CC46DF9BCA832504BDAE--