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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id fd20-20020a056402389400b0056be0d1cd83sm3876865edb.97.2024.03.26.02.30.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Mar 2024 02:30:01 -0700 (PDT) Message-ID: Date: Tue, 26 Mar 2024 10:30:00 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 6/9] Support APX NDD Content-Language: en-US To: "Cui, Lili" Cc: "Lu, Hongjiu" , "Kong, Lingling" , "binutils@sourceware.org" References: <20231124070213.3886483-1-lili.cui@intel.com> <20231124070213.3886483-6-lili.cui@intel.com> <8077dbe0-4519-4438-a943-5a310ff5f523@suse.com> <2d45e9ae-5376-4d05-94d4-e1104ba59a11@suse.com> From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3025.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 26.03.2024 09:22, Cui, Lili wrote: >> On 22.03.2024 11:02, Jan Beulich wrote: >>> On 08.12.2023 15:12, Jan Beulich wrote: >>>> On 24.11.2023 08:02, Cui, Lili wrote: >>>>> +rol, 0xd0/0, APX_F, >>>>> >> +W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVex128|EVexMap4|NF, { >>>>> +Imm1, >>>>> >> +Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseInd >> ex, >>>>> +Reg8|Reg16|Reg32|Reg64 } >>>>> rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, >>>>> >> Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex >> } >>>>> +rol, 0xc0/0, APX_F, >>>>> >> +W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVex128|EVexMap4|NF, { >>>>> +Imm8|Imm8S, >>>>> >> +Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseInd >> ex, >>>>> +Reg8|Reg16|Reg32|Reg64 } >>>>> rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, >>>>> >> Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex >> } >>>>> +rol, 0xd2/0, APX_F, >>>>> >> +W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVex128|EVexMap4|NF, { >>>>> +ShiftCount, >>>>> >> +Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseInd >> ex, >>>>> +Reg8|Reg16|Reg32|Reg64 } >>>>> rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, >>>>> >> Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex >> } >>>>> +rol, 0xd0/0, APX_F, >>>>> >> +W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVex128|EVexMap4|NF, { >>>>> >> +Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseInd >> ex, >>>>> +Reg8|Reg16|Reg32|Reg64 } >>>> >>>> Didn't we agree to avoid adding this (and its sibling) template, for >>>> the omitted shift count being ambiguous? Consider >>>> >>>> rol %cl, %al >>>> >>>> Is this a rotate by %cl, or a 1-bit NDD rotate? >>> >>> Btw, while this comment was taken into account for the "normal" shifts >>> and rotates, SHLD / SHRD still have this odd extra form. >> >> I have to correct myself here: RCL and RCR had such an odd form retained, too >> (as, perhaps, a side effect of prematurely adding the non-NDD forms there). >> > > For RCL/RCR, we dropped the format of omitting $1. > rcl, 0xd0/2, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } That's my point: This was supposed to be dropped, but is still there. Only rol/ror and the four shifts are where it was properly dropped. The rcl/rcr ones disappear in "x86: templatize shift/rotate insns" now. > For example, when the register is %rcx, it will conflict with the following template. > > rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } > > I'm confused if we really want to omit the %cl case. I'll confirm it later. I'm confused by this. What are you talking about? Hmm, perhaps there was some confusion from me originally saying "had such an odd form retained". That wasn't specifically about it being %cl or $1 omitted, but more generally about insn forms with no explicit shift count (of whatever shape). Jan