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From: "dongbo (E)" <dongbo4@huawei.com>
To: Shaokun Zhang via Binutils <binutils@sourceware.org>,
	Shaokun Zhang <zhangshaokun@hisilicon.com>,
	Jingtao Cai <caijingtao@huawei.com>,
	"Richard Earnshaw" <rearnsha@arm.com>,
	Marcus Shawcroft <marcus.shawcroft@arm.com>,
	"Jan Beulich" <jbeulich@suse.com>, <richard.sandiford@arm.com>
Subject: Re: [PATCH RESEND v2] Aarch64: Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}
Date: Sun, 9 Oct 2022 09:31:43 +0800	[thread overview]
Message-ID: <fedb06b4-5a76-49a4-bdb3-027844e168cf@huawei.com> (raw)
In-Reply-To: <mptbkqwoquj.fsf@arm.com>

[-- Attachment #1: Type: text/plain, Size: 2362 bytes --]

Hi, Richard.

On 2022/9/30 22:54, Richard Sandiford wrote:
> "dongbo (E)" <dongbo4@huawei.com> writes:
>>
>> We tried to put `S_H` in front of `NIL`:
>>
>> ```
>>
>>       #define OP_SVE_Vv_HSD                        \
>> {                                                               \
>>         QLF2(S_H,S_H),                                      \
>>         QLF2(S_S,S_S),                                       \
>>         QLF2(S_D,S_D),                                      \
>>         QLF2(S_H,NIL),                                       \
>>         QLF2(S_S,NIL),                                       \
>>         QLF2(S_D,NIL),                                       \
>>       }
>>
>> ```
> Yeah, good point.  It should be in this order, like you say.
>
> The fixes you mention look correct to me.
>
>> But assembler will fail in `match_operands_qualifier` :(.
>>
>> ```
>>
>>       match_operands_qualifier (aarch64_inst *inst, bool update_p)
>>       {
>>           ...
>>           if (!aarch64_find_best_match (...))
>>           ...
>>           if (inst->opcode->flags & F_STRICT)
>>           {
>>               /* Require an exact qualifier match, even for NIL
>> qualifiers.  */
>>               nops = aarch64_num_of_operands (inst->opcode);
>>               for (i = 0; i < nops; ++i)
>>                   if (inst->operands[i].qualifier != qualifiers[i])
>>                       return false;
>>           }
>>       }
>>
>> ```
> I think that's a misfeature of the F_STRICT handling.  Does it work
> with the patch below?

We cannot find the `tree-data-ref.cc` in binutils, it is a file in GCC?

Is `0001-data-ref-Fix-ranges_maybe_overlap_p-test.patch` the patch you 
meant to send?


We also found a way to fix the F_STRICT matching failure. See patch 
below. :)

The main point is to give another `find_best_match` try when we get a 
qualifier mismatch for HSD operands.


Thanks,

Dong Bo


[-- Attachment #2: [PATCH]Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}.patch --]
[-- Type: text/plain, Size: 47870 bytes --]

From 5a36af8912d954e1f4a3bc4742be86a29b62cfb2 Mon Sep 17 00:00:00 2001
From: CaiJingtao <caijingtao@huawei.com>
Date: Sat, 8 Oct 2022 18:05:01 +0800
Subject: [PATCH] Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}

Omitting predicate size specifier in vector form of {sq, uq, }{decp, incp} is deprecated and will be prohibited in a future release of the aarch64,
see https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements-.

This allows explicit size specifier, e.g. `decp z0.h, p0.h`, for predicate operand of these SVE instructions.
The exsiting behaviour of not requiring the specifier is preserved.
And the disasembly is with the specifier with this patch.

The GAS tests passed under our local tests.

opcodes/

* aarch64-asm.c: modify `sve_size_hsd` encoding.
* aarch64-opc.h: add param `start_position`  for function `aarch64_find_best_match`.
* aarch64-opc.c: when iclass `sve_size_hsd` mismatch F_STRICT, match again.
* aarch64-dis.c: update function `aarch64_find_best_match`.
* aarch64-tbl.h (aarch64_opcode_table): add QUALS's type OP_SVE_VV_HSD for decp, incp, sqdecp, sqincp, uqdecp and uqincp.

gas/testsuite/gas/aarch64/

* sve-movprfx_23.s: update movprfx_23 testcase's test_sametwo macro, where take the predicate size specifier.
* sve-movprfx_23.d: update movprfx_23 testcase's expected disassembly.
* sve-movprfx_23.l: update movprfx_23 testcase's expected assembler messages.
* sve.s: add sve testcase's instructions for decp, incp, sqdecp, sqincp, uqdecp and uqincp, which take the predicate size specifier.
* sve.d: update sve testcase's expected disassembly.

Signed-off-by: CaiJingtao <caijingtao@huawei.com>
---
 gas/testsuite/gas/aarch64/sve-movprfx_23.d |  24 +-
 gas/testsuite/gas/aarch64/sve-movprfx_23.l |  24 +-
 gas/testsuite/gas/aarch64/sve-movprfx_23.s |   2 +-
 gas/testsuite/gas/aarch64/sve.d            | 542 ++++++++++++++-------
 gas/testsuite/gas/aarch64/sve.s            | 181 +++++++
 opcodes/aarch64-asm.c                      |   2 +-
 opcodes/aarch64-dis.c                      |   2 +-
 opcodes/aarch64-opc.c                      |  37 +-
 opcodes/aarch64-opc.h                      |   3 +-
 opcodes/aarch64-tbl.h                      |  21 +-
 10 files changed, 613 insertions(+), 225 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.d b/gas/testsuite/gas/aarch64/sve-movprfx_23.d
index 60448704174..e1c6c2c2cce 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_23.d
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.d
@@ -9,29 +9,29 @@ Disassembly of section .*:
 
 0+ <.*>:
 [^:]+:	04512461 	movprfx	z1.h, p1/m, z3.h
-[^:]+:	256c8021 	incp	z1.h, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	256c8021 	incp	z1.h, p1.h  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04912461 	movprfx	z1.s, p1/m, z3.s
-[^:]+:	25ac8021 	incp	z1.s, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25ac8021 	incp	z1.s, p1.s  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04d12461 	movprfx	z1.d, p1/m, z3.d
-[^:]+:	25ec8021 	incp	z1.d, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25ec8021 	incp	z1.d, p1.d  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04512461 	movprfx	z1.h, p1/m, z3.h
-[^:]+:	256d8021 	decp	z1.h, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	256d8021 	decp	z1.h, p1.h  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04912461 	movprfx	z1.s, p1/m, z3.s
-[^:]+:	25ad8021 	decp	z1.s, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25ad8021 	decp	z1.s, p1.s  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04d12461 	movprfx	z1.d, p1/m, z3.d
-[^:]+:	25ed8021 	decp	z1.d, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25ed8021 	decp	z1.d, p1.d  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04512461 	movprfx	z1.h, p1/m, z3.h
-[^:]+:	25688021 	sqincp	z1.h, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25688021 	sqincp	z1.h, p1.h  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04912461 	movprfx	z1.s, p1/m, z3.s
-[^:]+:	25a88021 	sqincp	z1.s, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25a88021 	sqincp	z1.s, p1.s  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04d12461 	movprfx	z1.d, p1/m, z3.d
-[^:]+:	25e88021 	sqincp	z1.d, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25e88021 	sqincp	z1.d, p1.d  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04512461 	movprfx	z1.h, p1/m, z3.h
-[^:]+:	256a8021 	sqdecp	z1.h, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	256a8021 	sqdecp	z1.h, p1.h  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04912461 	movprfx	z1.s, p1/m, z3.s
-[^:]+:	25aa8021 	sqdecp	z1.s, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25aa8021 	sqdecp	z1.s, p1.s  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04d12461 	movprfx	z1.d, p1/m, z3.d
-[^:]+:	25ea8021 	sqdecp	z1.d, p1  // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+:	25ea8021 	sqdecp	z1.d, p1.d  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04112461 	movprfx	z1.b, p1/m, z3.b
 [^:]+:	05288421 	clasta	z1.b, p1, z1.b, z1.b  // note: merging predicate expected due to preceding `movprfx' at operand 2
 [^:]+:	04512461 	movprfx	z1.h, p1/m, z3.h
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.l b/gas/testsuite/gas/aarch64/sve-movprfx_23.l
index ff25ee712ed..ac491df6189 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_23.l
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.l
@@ -1,16 +1,16 @@
 [^:]*: Assembler messages:
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.h,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.s,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.d,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.h,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.s,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.d,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.h,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.s,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.d,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.h,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.s,p1'
-.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.d,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.h,p1.h'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.s,p1.s'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.d,p1.d'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.h,p1.h'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.s,p1.s'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.d,p1.d'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.h,p1.h'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.s,p1.s'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.d,p1.d'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.h,p1.h'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.s,p1.s'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.d,p1.d'
 .*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.b,p1,z1.b,z1.b'
 .*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.h,p1,z1.h,z1.h'
 .*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.s,p1,z1.s,z1.s'
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.s b/gas/testsuite/gas/aarch64/sve-movprfx_23.s
index 709d81aa8a0..22697b37cf5 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_23.s
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.s
@@ -9,7 +9,7 @@
    .macro test_sametwo inst
    .irp sz, h,s,d
    movprfx z1.\sz, p1/m, z3.\sz
-   \inst z1.\sz, p1
+   \inst z1.\sz, p1.\sz
    .endr
    .endm
 
diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d
index 5d6d7562646..c99ded24f07 100644
--- a/gas/testsuite/gas/aarch64/sve.d
+++ b/gas/testsuite/gas/aarch64/sve.d
@@ -1,6 +1,8 @@
+#source: sve.s
 #as: -march=armv8-a+sve -I$srcdir/$subdir
 #objdump: -dr
 
+
 .* file format .*
 
 Disassembly of section .*:
@@ -7205,36 +7207,66 @@ Disassembly of section .*:
 [^:]+:	0479e400 	dech	x0, pow2, mul #10
 [^:]+:	047fe400 	dech	x0, pow2, mul #16
 [^:]+:	047fe400 	dech	x0, pow2, mul #16
-[^:]+:	256d8000 	decp	z0.h, p0
-[^:]+:	256d8000 	decp	z0.h, p0
-[^:]+:	256d8001 	decp	z1.h, p0
-[^:]+:	256d8001 	decp	z1.h, p0
-[^:]+:	256d801f 	decp	z31.h, p0
-[^:]+:	256d801f 	decp	z31.h, p0
-[^:]+:	256d8040 	decp	z0.h, p2
-[^:]+:	256d8040 	decp	z0.h, p2
-[^:]+:	256d81e0 	decp	z0.h, p15
-[^:]+:	256d81e0 	decp	z0.h, p15
-[^:]+:	25ad8000 	decp	z0.s, p0
-[^:]+:	25ad8000 	decp	z0.s, p0
-[^:]+:	25ad8001 	decp	z1.s, p0
-[^:]+:	25ad8001 	decp	z1.s, p0
-[^:]+:	25ad801f 	decp	z31.s, p0
-[^:]+:	25ad801f 	decp	z31.s, p0
-[^:]+:	25ad8040 	decp	z0.s, p2
-[^:]+:	25ad8040 	decp	z0.s, p2
-[^:]+:	25ad81e0 	decp	z0.s, p15
-[^:]+:	25ad81e0 	decp	z0.s, p15
-[^:]+:	25ed8000 	decp	z0.d, p0
-[^:]+:	25ed8000 	decp	z0.d, p0
-[^:]+:	25ed8001 	decp	z1.d, p0
-[^:]+:	25ed8001 	decp	z1.d, p0
-[^:]+:	25ed801f 	decp	z31.d, p0
-[^:]+:	25ed801f 	decp	z31.d, p0
-[^:]+:	25ed8040 	decp	z0.d, p2
-[^:]+:	25ed8040 	decp	z0.d, p2
-[^:]+:	25ed81e0 	decp	z0.d, p15
-[^:]+:	25ed81e0 	decp	z0.d, p15
+[^:]+:	256d8000 	decp	z0.h, p0.h
+[^:]+:	256d8000 	decp	z0.h, p0.h
+[^:]+:	256d8001 	decp	z1.h, p0.h
+[^:]+:	256d8001 	decp	z1.h, p0.h
+[^:]+:	256d801f 	decp	z31.h, p0.h
+[^:]+:	256d801f 	decp	z31.h, p0.h
+[^:]+:	256d8040 	decp	z0.h, p2.h
+[^:]+:	256d8040 	decp	z0.h, p2.h
+[^:]+:	256d81e0 	decp	z0.h, p15.h
+[^:]+:	256d81e0 	decp	z0.h, p15.h
+[^:]+:	25ad8000 	decp	z0.s, p0.s
+[^:]+:	25ad8000 	decp	z0.s, p0.s
+[^:]+:	25ad8001 	decp	z1.s, p0.s
+[^:]+:	25ad8001 	decp	z1.s, p0.s
+[^:]+:	25ad801f 	decp	z31.s, p0.s
+[^:]+:	25ad801f 	decp	z31.s, p0.s
+[^:]+:	25ad8040 	decp	z0.s, p2.s
+[^:]+:	25ad8040 	decp	z0.s, p2.s
+[^:]+:	25ad81e0 	decp	z0.s, p15.s
+[^:]+:	25ad81e0 	decp	z0.s, p15.s
+[^:]+:	25ed8000 	decp	z0.d, p0.d
+[^:]+:	25ed8000 	decp	z0.d, p0.d
+[^:]+:	25ed8001 	decp	z1.d, p0.d
+[^:]+:	25ed8001 	decp	z1.d, p0.d
+[^:]+:	25ed801f 	decp	z31.d, p0.d
+[^:]+:	25ed801f 	decp	z31.d, p0.d
+[^:]+:	25ed8040 	decp	z0.d, p2.d
+[^:]+:	25ed8040 	decp	z0.d, p2.d
+[^:]+:	25ed81e0 	decp	z0.d, p15.d
+[^:]+:	25ed81e0 	decp	z0.d, p15.d
+[^:]+:	256d8000 	decp	z0.h, p0.h
+[^:]+:	256d8000 	decp	z0.h, p0.h
+[^:]+:	256d8001 	decp	z1.h, p0.h
+[^:]+:	256d8001 	decp	z1.h, p0.h
+[^:]+:	256d801f 	decp	z31.h, p0.h
+[^:]+:	256d801f 	decp	z31.h, p0.h
+[^:]+:	256d8040 	decp	z0.h, p2.h
+[^:]+:	256d8040 	decp	z0.h, p2.h
+[^:]+:	256d81e0 	decp	z0.h, p15.h
+[^:]+:	256d81e0 	decp	z0.h, p15.h
+[^:]+:	25ad8000 	decp	z0.s, p0.s
+[^:]+:	25ad8000 	decp	z0.s, p0.s
+[^:]+:	25ad8001 	decp	z1.s, p0.s
+[^:]+:	25ad8001 	decp	z1.s, p0.s
+[^:]+:	25ad801f 	decp	z31.s, p0.s
+[^:]+:	25ad801f 	decp	z31.s, p0.s
+[^:]+:	25ad8040 	decp	z0.s, p2.s
+[^:]+:	25ad8040 	decp	z0.s, p2.s
+[^:]+:	25ad81e0 	decp	z0.s, p15.s
+[^:]+:	25ad81e0 	decp	z0.s, p15.s
+[^:]+:	25ed8000 	decp	z0.d, p0.d
+[^:]+:	25ed8000 	decp	z0.d, p0.d
+[^:]+:	25ed8001 	decp	z1.d, p0.d
+[^:]+:	25ed8001 	decp	z1.d, p0.d
+[^:]+:	25ed801f 	decp	z31.d, p0.d
+[^:]+:	25ed801f 	decp	z31.d, p0.d
+[^:]+:	25ed8040 	decp	z0.d, p2.d
+[^:]+:	25ed8040 	decp	z0.d, p2.d
+[^:]+:	25ed81e0 	decp	z0.d, p15.d
+[^:]+:	25ed81e0 	decp	z0.d, p15.d
 [^:]+:	252d8800 	decp	x0, p0.b
 [^:]+:	252d8800 	decp	x0, p0.b
 [^:]+:	252d8801 	decp	x1, p0.b
@@ -13031,36 +13063,66 @@ Disassembly of section .*:
 [^:]+:	0479e000 	inch	x0, pow2, mul #10
 [^:]+:	047fe000 	inch	x0, pow2, mul #16
 [^:]+:	047fe000 	inch	x0, pow2, mul #16
-[^:]+:	256c8000 	incp	z0.h, p0
-[^:]+:	256c8000 	incp	z0.h, p0
-[^:]+:	256c8001 	incp	z1.h, p0
-[^:]+:	256c8001 	incp	z1.h, p0
-[^:]+:	256c801f 	incp	z31.h, p0
-[^:]+:	256c801f 	incp	z31.h, p0
-[^:]+:	256c8040 	incp	z0.h, p2
-[^:]+:	256c8040 	incp	z0.h, p2
-[^:]+:	256c81e0 	incp	z0.h, p15
-[^:]+:	256c81e0 	incp	z0.h, p15
-[^:]+:	25ac8000 	incp	z0.s, p0
-[^:]+:	25ac8000 	incp	z0.s, p0
-[^:]+:	25ac8001 	incp	z1.s, p0
-[^:]+:	25ac8001 	incp	z1.s, p0
-[^:]+:	25ac801f 	incp	z31.s, p0
-[^:]+:	25ac801f 	incp	z31.s, p0
-[^:]+:	25ac8040 	incp	z0.s, p2
-[^:]+:	25ac8040 	incp	z0.s, p2
-[^:]+:	25ac81e0 	incp	z0.s, p15
-[^:]+:	25ac81e0 	incp	z0.s, p15
-[^:]+:	25ec8000 	incp	z0.d, p0
-[^:]+:	25ec8000 	incp	z0.d, p0
-[^:]+:	25ec8001 	incp	z1.d, p0
-[^:]+:	25ec8001 	incp	z1.d, p0
-[^:]+:	25ec801f 	incp	z31.d, p0
-[^:]+:	25ec801f 	incp	z31.d, p0
-[^:]+:	25ec8040 	incp	z0.d, p2
-[^:]+:	25ec8040 	incp	z0.d, p2
-[^:]+:	25ec81e0 	incp	z0.d, p15
-[^:]+:	25ec81e0 	incp	z0.d, p15
+[^:]+:	256c8000 	incp	z0.h, p0.h
+[^:]+:	256c8000 	incp	z0.h, p0.h
+[^:]+:	256c8001 	incp	z1.h, p0.h
+[^:]+:	256c8001 	incp	z1.h, p0.h
+[^:]+:	256c801f 	incp	z31.h, p0.h
+[^:]+:	256c801f 	incp	z31.h, p0.h
+[^:]+:	256c8040 	incp	z0.h, p2.h
+[^:]+:	256c8040 	incp	z0.h, p2.h
+[^:]+:	256c81e0 	incp	z0.h, p15.h
+[^:]+:	256c81e0 	incp	z0.h, p15.h
+[^:]+:	25ac8000 	incp	z0.s, p0.s
+[^:]+:	25ac8000 	incp	z0.s, p0.s
+[^:]+:	25ac8001 	incp	z1.s, p0.s
+[^:]+:	25ac8001 	incp	z1.s, p0.s
+[^:]+:	25ac801f 	incp	z31.s, p0.s
+[^:]+:	25ac801f 	incp	z31.s, p0.s
+[^:]+:	25ac8040 	incp	z0.s, p2.s
+[^:]+:	25ac8040 	incp	z0.s, p2.s
+[^:]+:	25ac81e0 	incp	z0.s, p15.s
+[^:]+:	25ac81e0 	incp	z0.s, p15.s
+[^:]+:	25ec8000 	incp	z0.d, p0.d
+[^:]+:	25ec8000 	incp	z0.d, p0.d
+[^:]+:	25ec8001 	incp	z1.d, p0.d
+[^:]+:	25ec8001 	incp	z1.d, p0.d
+[^:]+:	25ec801f 	incp	z31.d, p0.d
+[^:]+:	25ec801f 	incp	z31.d, p0.d
+[^:]+:	25ec8040 	incp	z0.d, p2.d
+[^:]+:	25ec8040 	incp	z0.d, p2.d
+[^:]+:	25ec81e0 	incp	z0.d, p15.d
+[^:]+:	25ec81e0 	incp	z0.d, p15.d
+[^:]+:	256c8000 	incp	z0.h, p0.h
+[^:]+:	256c8000 	incp	z0.h, p0.h
+[^:]+:	256c8001 	incp	z1.h, p0.h
+[^:]+:	256c8001 	incp	z1.h, p0.h
+[^:]+:	256c801f 	incp	z31.h, p0.h
+[^:]+:	256c801f 	incp	z31.h, p0.h
+[^:]+:	256c8040 	incp	z0.h, p2.h
+[^:]+:	256c8040 	incp	z0.h, p2.h
+[^:]+:	256c81e0 	incp	z0.h, p15.h
+[^:]+:	256c81e0 	incp	z0.h, p15.h
+[^:]+:	25ac8000 	incp	z0.s, p0.s
+[^:]+:	25ac8000 	incp	z0.s, p0.s
+[^:]+:	25ac8001 	incp	z1.s, p0.s
+[^:]+:	25ac8001 	incp	z1.s, p0.s
+[^:]+:	25ac801f 	incp	z31.s, p0.s
+[^:]+:	25ac801f 	incp	z31.s, p0.s
+[^:]+:	25ac8040 	incp	z0.s, p2.s
+[^:]+:	25ac8040 	incp	z0.s, p2.s
+[^:]+:	25ac81e0 	incp	z0.s, p15.s
+[^:]+:	25ac81e0 	incp	z0.s, p15.s
+[^:]+:	25ec8000 	incp	z0.d, p0.d
+[^:]+:	25ec8000 	incp	z0.d, p0.d
+[^:]+:	25ec8001 	incp	z1.d, p0.d
+[^:]+:	25ec8001 	incp	z1.d, p0.d
+[^:]+:	25ec801f 	incp	z31.d, p0.d
+[^:]+:	25ec801f 	incp	z31.d, p0.d
+[^:]+:	25ec8040 	incp	z0.d, p2.d
+[^:]+:	25ec8040 	incp	z0.d, p2.d
+[^:]+:	25ec81e0 	incp	z0.d, p15.d
+[^:]+:	25ec81e0 	incp	z0.d, p15.d
 [^:]+:	252c8800 	incp	x0, p0.b
 [^:]+:	252c8800 	incp	x0, p0.b
 [^:]+:	252c8801 	incp	x1, p0.b
@@ -28800,36 +28862,66 @@ Disassembly of section .*:
 [^:]+:	0469f800 	sqdech	x0, w0, pow2, mul #10
 [^:]+:	046ff800 	sqdech	x0, w0, pow2, mul #16
 [^:]+:	046ff800 	sqdech	x0, w0, pow2, mul #16
-[^:]+:	256a8000 	sqdecp	z0.h, p0
-[^:]+:	256a8000 	sqdecp	z0.h, p0
-[^:]+:	256a8001 	sqdecp	z1.h, p0
-[^:]+:	256a8001 	sqdecp	z1.h, p0
-[^:]+:	256a801f 	sqdecp	z31.h, p0
-[^:]+:	256a801f 	sqdecp	z31.h, p0
-[^:]+:	256a8040 	sqdecp	z0.h, p2
-[^:]+:	256a8040 	sqdecp	z0.h, p2
-[^:]+:	256a81e0 	sqdecp	z0.h, p15
-[^:]+:	256a81e0 	sqdecp	z0.h, p15
-[^:]+:	25aa8000 	sqdecp	z0.s, p0
-[^:]+:	25aa8000 	sqdecp	z0.s, p0
-[^:]+:	25aa8001 	sqdecp	z1.s, p0
-[^:]+:	25aa8001 	sqdecp	z1.s, p0
-[^:]+:	25aa801f 	sqdecp	z31.s, p0
-[^:]+:	25aa801f 	sqdecp	z31.s, p0
-[^:]+:	25aa8040 	sqdecp	z0.s, p2
-[^:]+:	25aa8040 	sqdecp	z0.s, p2
-[^:]+:	25aa81e0 	sqdecp	z0.s, p15
-[^:]+:	25aa81e0 	sqdecp	z0.s, p15
-[^:]+:	25ea8000 	sqdecp	z0.d, p0
-[^:]+:	25ea8000 	sqdecp	z0.d, p0
-[^:]+:	25ea8001 	sqdecp	z1.d, p0
-[^:]+:	25ea8001 	sqdecp	z1.d, p0
-[^:]+:	25ea801f 	sqdecp	z31.d, p0
-[^:]+:	25ea801f 	sqdecp	z31.d, p0
-[^:]+:	25ea8040 	sqdecp	z0.d, p2
-[^:]+:	25ea8040 	sqdecp	z0.d, p2
-[^:]+:	25ea81e0 	sqdecp	z0.d, p15
-[^:]+:	25ea81e0 	sqdecp	z0.d, p15
+[^:]+:	256a8000 	sqdecp	z0.h, p0.h
+[^:]+:	256a8000 	sqdecp	z0.h, p0.h
+[^:]+:	256a8001 	sqdecp	z1.h, p0.h
+[^:]+:	256a8001 	sqdecp	z1.h, p0.h
+[^:]+:	256a801f 	sqdecp	z31.h, p0.h
+[^:]+:	256a801f 	sqdecp	z31.h, p0.h
+[^:]+:	256a8040 	sqdecp	z0.h, p2.h
+[^:]+:	256a8040 	sqdecp	z0.h, p2.h
+[^:]+:	256a81e0 	sqdecp	z0.h, p15.h
+[^:]+:	256a81e0 	sqdecp	z0.h, p15.h
+[^:]+:	25aa8000 	sqdecp	z0.s, p0.s
+[^:]+:	25aa8000 	sqdecp	z0.s, p0.s
+[^:]+:	25aa8001 	sqdecp	z1.s, p0.s
+[^:]+:	25aa8001 	sqdecp	z1.s, p0.s
+[^:]+:	25aa801f 	sqdecp	z31.s, p0.s
+[^:]+:	25aa801f 	sqdecp	z31.s, p0.s
+[^:]+:	25aa8040 	sqdecp	z0.s, p2.s
+[^:]+:	25aa8040 	sqdecp	z0.s, p2.s
+[^:]+:	25aa81e0 	sqdecp	z0.s, p15.s
+[^:]+:	25aa81e0 	sqdecp	z0.s, p15.s
+[^:]+:	25ea8000 	sqdecp	z0.d, p0.d
+[^:]+:	25ea8000 	sqdecp	z0.d, p0.d
+[^:]+:	25ea8001 	sqdecp	z1.d, p0.d
+[^:]+:	25ea8001 	sqdecp	z1.d, p0.d
+[^:]+:	25ea801f 	sqdecp	z31.d, p0.d
+[^:]+:	25ea801f 	sqdecp	z31.d, p0.d
+[^:]+:	25ea8040 	sqdecp	z0.d, p2.d
+[^:]+:	25ea8040 	sqdecp	z0.d, p2.d
+[^:]+:	25ea81e0 	sqdecp	z0.d, p15.d
+[^:]+:	25ea81e0 	sqdecp	z0.d, p15.d
+[^:]+:	256a8000 	sqdecp	z0.h, p0.h
+[^:]+:	256a8000 	sqdecp	z0.h, p0.h
+[^:]+:	256a8001 	sqdecp	z1.h, p0.h
+[^:]+:	256a8001 	sqdecp	z1.h, p0.h
+[^:]+:	256a801f 	sqdecp	z31.h, p0.h
+[^:]+:	256a801f 	sqdecp	z31.h, p0.h
+[^:]+:	256a8040 	sqdecp	z0.h, p2.h
+[^:]+:	256a8040 	sqdecp	z0.h, p2.h
+[^:]+:	256a81e0 	sqdecp	z0.h, p15.h
+[^:]+:	256a81e0 	sqdecp	z0.h, p15.h
+[^:]+:	25aa8000 	sqdecp	z0.s, p0.s
+[^:]+:	25aa8000 	sqdecp	z0.s, p0.s
+[^:]+:	25aa8001 	sqdecp	z1.s, p0.s
+[^:]+:	25aa8001 	sqdecp	z1.s, p0.s
+[^:]+:	25aa801f 	sqdecp	z31.s, p0.s
+[^:]+:	25aa801f 	sqdecp	z31.s, p0.s
+[^:]+:	25aa8040 	sqdecp	z0.s, p2.s
+[^:]+:	25aa8040 	sqdecp	z0.s, p2.s
+[^:]+:	25aa81e0 	sqdecp	z0.s, p15.s
+[^:]+:	25aa81e0 	sqdecp	z0.s, p15.s
+[^:]+:	25ea8000 	sqdecp	z0.d, p0.d
+[^:]+:	25ea8000 	sqdecp	z0.d, p0.d
+[^:]+:	25ea8001 	sqdecp	z1.d, p0.d
+[^:]+:	25ea8001 	sqdecp	z1.d, p0.d
+[^:]+:	25ea801f 	sqdecp	z31.d, p0.d
+[^:]+:	25ea801f 	sqdecp	z31.d, p0.d
+[^:]+:	25ea8040 	sqdecp	z0.d, p2.d
+[^:]+:	25ea8040 	sqdecp	z0.d, p2.d
+[^:]+:	25ea81e0 	sqdecp	z0.d, p15.d
+[^:]+:	25ea81e0 	sqdecp	z0.d, p15.d
 [^:]+:	252a8c00 	sqdecp	x0, p0.b
 [^:]+:	252a8c00 	sqdecp	x0, p0.b
 [^:]+:	252a8c01 	sqdecp	x1, p0.b
@@ -30151,36 +30243,66 @@ Disassembly of section .*:
 [^:]+:	0469f000 	sqinch	x0, w0, pow2, mul #10
 [^:]+:	046ff000 	sqinch	x0, w0, pow2, mul #16
 [^:]+:	046ff000 	sqinch	x0, w0, pow2, mul #16
-[^:]+:	25688000 	sqincp	z0.h, p0
-[^:]+:	25688000 	sqincp	z0.h, p0
-[^:]+:	25688001 	sqincp	z1.h, p0
-[^:]+:	25688001 	sqincp	z1.h, p0
-[^:]+:	2568801f 	sqincp	z31.h, p0
-[^:]+:	2568801f 	sqincp	z31.h, p0
-[^:]+:	25688040 	sqincp	z0.h, p2
-[^:]+:	25688040 	sqincp	z0.h, p2
-[^:]+:	256881e0 	sqincp	z0.h, p15
-[^:]+:	256881e0 	sqincp	z0.h, p15
-[^:]+:	25a88000 	sqincp	z0.s, p0
-[^:]+:	25a88000 	sqincp	z0.s, p0
-[^:]+:	25a88001 	sqincp	z1.s, p0
-[^:]+:	25a88001 	sqincp	z1.s, p0
-[^:]+:	25a8801f 	sqincp	z31.s, p0
-[^:]+:	25a8801f 	sqincp	z31.s, p0
-[^:]+:	25a88040 	sqincp	z0.s, p2
-[^:]+:	25a88040 	sqincp	z0.s, p2
-[^:]+:	25a881e0 	sqincp	z0.s, p15
-[^:]+:	25a881e0 	sqincp	z0.s, p15
-[^:]+:	25e88000 	sqincp	z0.d, p0
-[^:]+:	25e88000 	sqincp	z0.d, p0
-[^:]+:	25e88001 	sqincp	z1.d, p0
-[^:]+:	25e88001 	sqincp	z1.d, p0
-[^:]+:	25e8801f 	sqincp	z31.d, p0
-[^:]+:	25e8801f 	sqincp	z31.d, p0
-[^:]+:	25e88040 	sqincp	z0.d, p2
-[^:]+:	25e88040 	sqincp	z0.d, p2
-[^:]+:	25e881e0 	sqincp	z0.d, p15
-[^:]+:	25e881e0 	sqincp	z0.d, p15
+[^:]+:	25688000 	sqincp	z0.h, p0.h
+[^:]+:	25688000 	sqincp	z0.h, p0.h
+[^:]+:	25688001 	sqincp	z1.h, p0.h
+[^:]+:	25688001 	sqincp	z1.h, p0.h
+[^:]+:	2568801f 	sqincp	z31.h, p0.h
+[^:]+:	2568801f 	sqincp	z31.h, p0.h
+[^:]+:	25688040 	sqincp	z0.h, p2.h
+[^:]+:	25688040 	sqincp	z0.h, p2.h
+[^:]+:	256881e0 	sqincp	z0.h, p15.h
+[^:]+:	256881e0 	sqincp	z0.h, p15.h
+[^:]+:	25a88000 	sqincp	z0.s, p0.s
+[^:]+:	25a88000 	sqincp	z0.s, p0.s
+[^:]+:	25a88001 	sqincp	z1.s, p0.s
+[^:]+:	25a88001 	sqincp	z1.s, p0.s
+[^:]+:	25a8801f 	sqincp	z31.s, p0.s
+[^:]+:	25a8801f 	sqincp	z31.s, p0.s
+[^:]+:	25a88040 	sqincp	z0.s, p2.s
+[^:]+:	25a88040 	sqincp	z0.s, p2.s
+[^:]+:	25a881e0 	sqincp	z0.s, p15.s
+[^:]+:	25a881e0 	sqincp	z0.s, p15.s
+[^:]+:	25e88000 	sqincp	z0.d, p0.d
+[^:]+:	25e88000 	sqincp	z0.d, p0.d
+[^:]+:	25e88001 	sqincp	z1.d, p0.d
+[^:]+:	25e88001 	sqincp	z1.d, p0.d
+[^:]+:	25e8801f 	sqincp	z31.d, p0.d
+[^:]+:	25e8801f 	sqincp	z31.d, p0.d
+[^:]+:	25e88040 	sqincp	z0.d, p2.d
+[^:]+:	25e88040 	sqincp	z0.d, p2.d
+[^:]+:	25e881e0 	sqincp	z0.d, p15.d
+[^:]+:	25e881e0 	sqincp	z0.d, p15.d
+[^:]+:	25688000 	sqincp	z0.h, p0.h
+[^:]+:	25688000 	sqincp	z0.h, p0.h
+[^:]+:	25688001 	sqincp	z1.h, p0.h
+[^:]+:	25688001 	sqincp	z1.h, p0.h
+[^:]+:	2568801f 	sqincp	z31.h, p0.h
+[^:]+:	2568801f 	sqincp	z31.h, p0.h
+[^:]+:	25688040 	sqincp	z0.h, p2.h
+[^:]+:	25688040 	sqincp	z0.h, p2.h
+[^:]+:	256881e0 	sqincp	z0.h, p15.h
+[^:]+:	256881e0 	sqincp	z0.h, p15.h
+[^:]+:	25a88000 	sqincp	z0.s, p0.s
+[^:]+:	25a88000 	sqincp	z0.s, p0.s
+[^:]+:	25a88001 	sqincp	z1.s, p0.s
+[^:]+:	25a88001 	sqincp	z1.s, p0.s
+[^:]+:	25a8801f 	sqincp	z31.s, p0.s
+[^:]+:	25a8801f 	sqincp	z31.s, p0.s
+[^:]+:	25a88040 	sqincp	z0.s, p2.s
+[^:]+:	25a88040 	sqincp	z0.s, p2.s
+[^:]+:	25a881e0 	sqincp	z0.s, p15.s
+[^:]+:	25a881e0 	sqincp	z0.s, p15.s
+[^:]+:	25e88000 	sqincp	z0.d, p0.d
+[^:]+:	25e88000 	sqincp	z0.d, p0.d
+[^:]+:	25e88001 	sqincp	z1.d, p0.d
+[^:]+:	25e88001 	sqincp	z1.d, p0.d
+[^:]+:	25e8801f 	sqincp	z31.d, p0.d
+[^:]+:	25e8801f 	sqincp	z31.d, p0.d
+[^:]+:	25e88040 	sqincp	z0.d, p2.d
+[^:]+:	25e88040 	sqincp	z0.d, p2.d
+[^:]+:	25e881e0 	sqincp	z0.d, p15.d
+[^:]+:	25e881e0 	sqincp	z0.d, p15.d
 [^:]+:	25288c00 	sqincp	x0, p0.b
 [^:]+:	25288c00 	sqincp	x0, p0.b
 [^:]+:	25288c01 	sqincp	x1, p0.b
@@ -36646,36 +36768,66 @@ Disassembly of section .*:
 [^:]+:	0479fc00 	uqdech	x0, pow2, mul #10
 [^:]+:	047ffc00 	uqdech	x0, pow2, mul #16
 [^:]+:	047ffc00 	uqdech	x0, pow2, mul #16
-[^:]+:	256b8000 	uqdecp	z0.h, p0
-[^:]+:	256b8000 	uqdecp	z0.h, p0
-[^:]+:	256b8001 	uqdecp	z1.h, p0
-[^:]+:	256b8001 	uqdecp	z1.h, p0
-[^:]+:	256b801f 	uqdecp	z31.h, p0
-[^:]+:	256b801f 	uqdecp	z31.h, p0
-[^:]+:	256b8040 	uqdecp	z0.h, p2
-[^:]+:	256b8040 	uqdecp	z0.h, p2
-[^:]+:	256b81e0 	uqdecp	z0.h, p15
-[^:]+:	256b81e0 	uqdecp	z0.h, p15
-[^:]+:	25ab8000 	uqdecp	z0.s, p0
-[^:]+:	25ab8000 	uqdecp	z0.s, p0
-[^:]+:	25ab8001 	uqdecp	z1.s, p0
-[^:]+:	25ab8001 	uqdecp	z1.s, p0
-[^:]+:	25ab801f 	uqdecp	z31.s, p0
-[^:]+:	25ab801f 	uqdecp	z31.s, p0
-[^:]+:	25ab8040 	uqdecp	z0.s, p2
-[^:]+:	25ab8040 	uqdecp	z0.s, p2
-[^:]+:	25ab81e0 	uqdecp	z0.s, p15
-[^:]+:	25ab81e0 	uqdecp	z0.s, p15
-[^:]+:	25eb8000 	uqdecp	z0.d, p0
-[^:]+:	25eb8000 	uqdecp	z0.d, p0
-[^:]+:	25eb8001 	uqdecp	z1.d, p0
-[^:]+:	25eb8001 	uqdecp	z1.d, p0
-[^:]+:	25eb801f 	uqdecp	z31.d, p0
-[^:]+:	25eb801f 	uqdecp	z31.d, p0
-[^:]+:	25eb8040 	uqdecp	z0.d, p2
-[^:]+:	25eb8040 	uqdecp	z0.d, p2
-[^:]+:	25eb81e0 	uqdecp	z0.d, p15
-[^:]+:	25eb81e0 	uqdecp	z0.d, p15
+[^:]+:	256b8000 	uqdecp	z0.h, p0.h
+[^:]+:	256b8000 	uqdecp	z0.h, p0.h
+[^:]+:	256b8001 	uqdecp	z1.h, p0.h
+[^:]+:	256b8001 	uqdecp	z1.h, p0.h
+[^:]+:	256b801f 	uqdecp	z31.h, p0.h
+[^:]+:	256b801f 	uqdecp	z31.h, p0.h
+[^:]+:	256b8040 	uqdecp	z0.h, p2.h
+[^:]+:	256b8040 	uqdecp	z0.h, p2.h
+[^:]+:	256b81e0 	uqdecp	z0.h, p15.h
+[^:]+:	256b81e0 	uqdecp	z0.h, p15.h
+[^:]+:	25ab8000 	uqdecp	z0.s, p0.s
+[^:]+:	25ab8000 	uqdecp	z0.s, p0.s
+[^:]+:	25ab8001 	uqdecp	z1.s, p0.s
+[^:]+:	25ab8001 	uqdecp	z1.s, p0.s
+[^:]+:	25ab801f 	uqdecp	z31.s, p0.s
+[^:]+:	25ab801f 	uqdecp	z31.s, p0.s
+[^:]+:	25ab8040 	uqdecp	z0.s, p2.s
+[^:]+:	25ab8040 	uqdecp	z0.s, p2.s
+[^:]+:	25ab81e0 	uqdecp	z0.s, p15.s
+[^:]+:	25ab81e0 	uqdecp	z0.s, p15.s
+[^:]+:	25eb8000 	uqdecp	z0.d, p0.d
+[^:]+:	25eb8000 	uqdecp	z0.d, p0.d
+[^:]+:	25eb8001 	uqdecp	z1.d, p0.d
+[^:]+:	25eb8001 	uqdecp	z1.d, p0.d
+[^:]+:	25eb801f 	uqdecp	z31.d, p0.d
+[^:]+:	25eb801f 	uqdecp	z31.d, p0.d
+[^:]+:	25eb8040 	uqdecp	z0.d, p2.d
+[^:]+:	25eb8040 	uqdecp	z0.d, p2.d
+[^:]+:	25eb81e0 	uqdecp	z0.d, p15.d
+[^:]+:	25eb81e0 	uqdecp	z0.d, p15.d
+[^:]+:	256b8000 	uqdecp	z0.h, p0.h
+[^:]+:	256b8000 	uqdecp	z0.h, p0.h
+[^:]+:	256b8001 	uqdecp	z1.h, p0.h
+[^:]+:	256b8001 	uqdecp	z1.h, p0.h
+[^:]+:	256b801f 	uqdecp	z31.h, p0.h
+[^:]+:	256b801f 	uqdecp	z31.h, p0.h
+[^:]+:	256b8040 	uqdecp	z0.h, p2.h
+[^:]+:	256b8040 	uqdecp	z0.h, p2.h
+[^:]+:	256b81e0 	uqdecp	z0.h, p15.h
+[^:]+:	256b81e0 	uqdecp	z0.h, p15.h
+[^:]+:	25ab8000 	uqdecp	z0.s, p0.s
+[^:]+:	25ab8000 	uqdecp	z0.s, p0.s
+[^:]+:	25ab8001 	uqdecp	z1.s, p0.s
+[^:]+:	25ab8001 	uqdecp	z1.s, p0.s
+[^:]+:	25ab801f 	uqdecp	z31.s, p0.s
+[^:]+:	25ab801f 	uqdecp	z31.s, p0.s
+[^:]+:	25ab8040 	uqdecp	z0.s, p2.s
+[^:]+:	25ab8040 	uqdecp	z0.s, p2.s
+[^:]+:	25ab81e0 	uqdecp	z0.s, p15.s
+[^:]+:	25ab81e0 	uqdecp	z0.s, p15.s
+[^:]+:	25eb8000 	uqdecp	z0.d, p0.d
+[^:]+:	25eb8000 	uqdecp	z0.d, p0.d
+[^:]+:	25eb8001 	uqdecp	z1.d, p0.d
+[^:]+:	25eb8001 	uqdecp	z1.d, p0.d
+[^:]+:	25eb801f 	uqdecp	z31.d, p0.d
+[^:]+:	25eb801f 	uqdecp	z31.d, p0.d
+[^:]+:	25eb8040 	uqdecp	z0.d, p2.d
+[^:]+:	25eb8040 	uqdecp	z0.d, p2.d
+[^:]+:	25eb81e0 	uqdecp	z0.d, p15.d
+[^:]+:	25eb81e0 	uqdecp	z0.d, p15.d
 [^:]+:	252b8800 	uqdecp	w0, p0.b
 [^:]+:	252b8800 	uqdecp	w0, p0.b
 [^:]+:	252b8801 	uqdecp	w1, p0.b
@@ -37977,36 +38129,66 @@ Disassembly of section .*:
 [^:]+:	0479f400 	uqinch	x0, pow2, mul #10
 [^:]+:	047ff400 	uqinch	x0, pow2, mul #16
 [^:]+:	047ff400 	uqinch	x0, pow2, mul #16
-[^:]+:	25698000 	uqincp	z0.h, p0
-[^:]+:	25698000 	uqincp	z0.h, p0
-[^:]+:	25698001 	uqincp	z1.h, p0
-[^:]+:	25698001 	uqincp	z1.h, p0
-[^:]+:	2569801f 	uqincp	z31.h, p0
-[^:]+:	2569801f 	uqincp	z31.h, p0
-[^:]+:	25698040 	uqincp	z0.h, p2
-[^:]+:	25698040 	uqincp	z0.h, p2
-[^:]+:	256981e0 	uqincp	z0.h, p15
-[^:]+:	256981e0 	uqincp	z0.h, p15
-[^:]+:	25a98000 	uqincp	z0.s, p0
-[^:]+:	25a98000 	uqincp	z0.s, p0
-[^:]+:	25a98001 	uqincp	z1.s, p0
-[^:]+:	25a98001 	uqincp	z1.s, p0
-[^:]+:	25a9801f 	uqincp	z31.s, p0
-[^:]+:	25a9801f 	uqincp	z31.s, p0
-[^:]+:	25a98040 	uqincp	z0.s, p2
-[^:]+:	25a98040 	uqincp	z0.s, p2
-[^:]+:	25a981e0 	uqincp	z0.s, p15
-[^:]+:	25a981e0 	uqincp	z0.s, p15
-[^:]+:	25e98000 	uqincp	z0.d, p0
-[^:]+:	25e98000 	uqincp	z0.d, p0
-[^:]+:	25e98001 	uqincp	z1.d, p0
-[^:]+:	25e98001 	uqincp	z1.d, p0
-[^:]+:	25e9801f 	uqincp	z31.d, p0
-[^:]+:	25e9801f 	uqincp	z31.d, p0
-[^:]+:	25e98040 	uqincp	z0.d, p2
-[^:]+:	25e98040 	uqincp	z0.d, p2
-[^:]+:	25e981e0 	uqincp	z0.d, p15
-[^:]+:	25e981e0 	uqincp	z0.d, p15
+[^:]+:	25698000 	uqincp	z0.h, p0.h
+[^:]+:	25698000 	uqincp	z0.h, p0.h
+[^:]+:	25698001 	uqincp	z1.h, p0.h
+[^:]+:	25698001 	uqincp	z1.h, p0.h
+[^:]+:	2569801f 	uqincp	z31.h, p0.h
+[^:]+:	2569801f 	uqincp	z31.h, p0.h
+[^:]+:	25698040 	uqincp	z0.h, p2.h
+[^:]+:	25698040 	uqincp	z0.h, p2.h
+[^:]+:	256981e0 	uqincp	z0.h, p15.h
+[^:]+:	256981e0 	uqincp	z0.h, p15.h
+[^:]+:	25a98000 	uqincp	z0.s, p0.s
+[^:]+:	25a98000 	uqincp	z0.s, p0.s
+[^:]+:	25a98001 	uqincp	z1.s, p0.s
+[^:]+:	25a98001 	uqincp	z1.s, p0.s
+[^:]+:	25a9801f 	uqincp	z31.s, p0.s
+[^:]+:	25a9801f 	uqincp	z31.s, p0.s
+[^:]+:	25a98040 	uqincp	z0.s, p2.s
+[^:]+:	25a98040 	uqincp	z0.s, p2.s
+[^:]+:	25a981e0 	uqincp	z0.s, p15.s
+[^:]+:	25a981e0 	uqincp	z0.s, p15.s
+[^:]+:	25e98000 	uqincp	z0.d, p0.d
+[^:]+:	25e98000 	uqincp	z0.d, p0.d
+[^:]+:	25e98001 	uqincp	z1.d, p0.d
+[^:]+:	25e98001 	uqincp	z1.d, p0.d
+[^:]+:	25e9801f 	uqincp	z31.d, p0.d
+[^:]+:	25e9801f 	uqincp	z31.d, p0.d
+[^:]+:	25e98040 	uqincp	z0.d, p2.d
+[^:]+:	25e98040 	uqincp	z0.d, p2.d
+[^:]+:	25e981e0 	uqincp	z0.d, p15.d
+[^:]+:	25e981e0 	uqincp	z0.d, p15.d
+[^:]+:	25698000 	uqincp	z0.h, p0.h
+[^:]+:	25698000 	uqincp	z0.h, p0.h
+[^:]+:	25698001 	uqincp	z1.h, p0.h
+[^:]+:	25698001 	uqincp	z1.h, p0.h
+[^:]+:	2569801f 	uqincp	z31.h, p0.h
+[^:]+:	2569801f 	uqincp	z31.h, p0.h
+[^:]+:	25698040 	uqincp	z0.h, p2.h
+[^:]+:	25698040 	uqincp	z0.h, p2.h
+[^:]+:	256981e0 	uqincp	z0.h, p15.h
+[^:]+:	256981e0 	uqincp	z0.h, p15.h
+[^:]+:	25a98000 	uqincp	z0.s, p0.s
+[^:]+:	25a98000 	uqincp	z0.s, p0.s
+[^:]+:	25a98001 	uqincp	z1.s, p0.s
+[^:]+:	25a98001 	uqincp	z1.s, p0.s
+[^:]+:	25a9801f 	uqincp	z31.s, p0.s
+[^:]+:	25a9801f 	uqincp	z31.s, p0.s
+[^:]+:	25a98040 	uqincp	z0.s, p2.s
+[^:]+:	25a98040 	uqincp	z0.s, p2.s
+[^:]+:	25a981e0 	uqincp	z0.s, p15.s
+[^:]+:	25a981e0 	uqincp	z0.s, p15.s
+[^:]+:	25e98000 	uqincp	z0.d, p0.d
+[^:]+:	25e98000 	uqincp	z0.d, p0.d
+[^:]+:	25e98001 	uqincp	z1.d, p0.d
+[^:]+:	25e98001 	uqincp	z1.d, p0.d
+[^:]+:	25e9801f 	uqincp	z31.d, p0.d
+[^:]+:	25e9801f 	uqincp	z31.d, p0.d
+[^:]+:	25e98040 	uqincp	z0.d, p2.d
+[^:]+:	25e98040 	uqincp	z0.d, p2.d
+[^:]+:	25e981e0 	uqincp	z0.d, p15.d
+[^:]+:	25e981e0 	uqincp	z0.d, p15.d
 [^:]+:	25298800 	uqincp	w0, p0.b
 [^:]+:	25298800 	uqincp	w0, p0.b
 [^:]+:	25298801 	uqincp	w1, p0.b
diff --git a/gas/testsuite/gas/aarch64/sve.s b/gas/testsuite/gas/aarch64/sve.s
index f3ca5e88673..11cf4cc7fc0 100644
--- a/gas/testsuite/gas/aarch64/sve.s
+++ b/gas/testsuite/gas/aarch64/sve.s
@@ -7244,6 +7244,36 @@
 	DECP      Z0.D, P2
 	decp      z0.d, p15
 	DECP      Z0.D, P15
+	decp      z0.h, p0.h
+	DECP      Z0.H, P0.H
+	decp      z1.h, p0.h
+	DECP      Z1.H, P0.H
+	decp      z31.h, p0.h
+	DECP      Z31.H, P0.H
+	decp      z0.h, p2.h
+	DECP      Z0.H, P2.H
+	decp      z0.h, p15.h
+	DECP      Z0.H, P15.H
+	decp      z0.s, p0.s
+	DECP      Z0.S, P0.S
+	decp      z1.s, p0.s
+	DECP      Z1.S, P0.S
+	decp      z31.s, p0.s
+	DECP      Z31.S, P0.S
+	decp      z0.s, p2.s
+	DECP      Z0.S, P2.S
+	decp      z0.s, p15.s
+	DECP      Z0.S, P15.S
+	decp      z0.d, p0.d
+	DECP      Z0.D, P0.D
+	decp      z1.d, p0.d
+	DECP      Z1.D, P0.D
+	decp      z31.d, p0.d
+	DECP      Z31.D, P0.D
+	decp      z0.d, p2.d
+	DECP      Z0.D, P2.D
+	decp      z0.d, p15.d
+	DECP      Z0.D, P15.D
 	decp      x0, p0.b
 	DECP      X0, P0.B
 	decp      x1, p0.b
@@ -13070,6 +13100,36 @@
 	INCP      Z0.D, P2
 	incp      z0.d, p15
 	INCP      Z0.D, P15
+	incp      z0.h, p0.h
+	INCP      Z0.H, P0.H
+	incp      z1.h, p0.h
+	INCP      Z1.H, P0.H
+	incp      z31.h, p0.h
+	INCP      Z31.H, P0.H
+	incp      z0.h, p2.h
+	INCP      Z0.H, P2.H
+	incp      z0.h, p15.h
+	INCP      Z0.H, P15.H
+	incp      z0.s, p0.s
+	INCP      Z0.S, P0.S
+	incp      z1.s, p0.s
+	INCP      Z1.S, P0.S
+	incp      z31.s, p0.s
+	INCP      Z31.S, P0.S
+	incp      z0.s, p2.s
+	INCP      Z0.S, P2.S
+	incp      z0.s, p15.s
+	INCP      Z0.S, P15.S
+	incp      z0.d, p0.d
+	INCP      Z0.D, P0.D
+	incp      z1.d, p0.d
+	INCP      Z1.D, P0.D
+	incp      z31.d, p0.d
+	INCP      Z31.D, P0.D
+	incp      z0.d, p2.d
+	INCP      Z0.D, P2.D
+	incp      z0.d, p15.d
+	INCP      Z0.D, P15.D
 	incp      x0, p0.b
 	INCP      X0, P0.B
 	incp      x1, p0.b
@@ -28839,6 +28899,36 @@
 	SQDECP    Z0.D, P2
 	sqdecp    z0.d, p15
 	SQDECP    Z0.D, P15
+	sqdecp    z0.h, p0.h
+	SQDECP    Z0.H, P0.H
+	sqdecp    z1.h, p0.h
+	SQDECP    Z1.H, P0.H
+	sqdecp    z31.h, p0.h
+	SQDECP    Z31.H, P0.H
+	sqdecp    z0.h, p2.h
+	SQDECP    Z0.H, P2.H
+	sqdecp    z0.h, p15.h
+	SQDECP    Z0.H, P15.H
+	sqdecp    z0.s, p0.s
+	SQDECP    Z0.S, P0.S
+	sqdecp    z1.s, p0.s
+	SQDECP    Z1.S, P0.S
+	sqdecp    z31.s, p0.s
+	SQDECP    Z31.S, P0.S
+	sqdecp    z0.s, p2.s
+	SQDECP    Z0.S, P2.S
+	sqdecp    z0.s, p15.s
+	SQDECP    Z0.S, P15.S
+	sqdecp    z0.d, p0.d
+	SQDECP    Z0.D, P0.D
+	sqdecp    z1.d, p0.d
+	SQDECP    Z1.D, P0.D
+	sqdecp    z31.d, p0.d
+	SQDECP    Z31.D, P0.D
+	sqdecp    z0.d, p2.d
+	SQDECP    Z0.D, P2.D
+	sqdecp    z0.d, p15.d
+	SQDECP    Z0.D, P15.D
 	sqdecp    x0, p0.b
 	SQDECP    X0, P0.B
 	sqdecp    x1, p0.b
@@ -30190,6 +30280,37 @@
 	SQINCP    Z0.D, P2
 	sqincp    z0.d, p15
 	SQINCP    Z0.D, P15
+	sqincp    z0.h, p0.h
+	SQINCP    Z0.H, P0.H
+	sqincp    z1.h, p0.h
+	SQINCP    Z1.H, P0.H
+	sqincp    z31.h, p0.h
+	SQINCP    Z31.H, P0.H
+	sqincp    z0.h, p2.h
+	SQINCP    Z0.H, P2.H
+	sqincp    z0.h, p15.h
+	SQINCP    Z0.H, P15.H
+	sqincp    z0.s, p0.s
+	SQINCP    Z0.S, P0.S
+	sqincp    z1.s, p0.s
+	SQINCP    Z1.S, P0.S
+	sqincp    z31.s, p0.s
+	SQINCP    Z31.S, P0.S
+	sqincp    z0.s, p2.s
+	SQINCP    Z0.S, P2.S
+	sqincp    z0.s, p15.s
+	SQINCP    Z0.S, P15.S
+	sqincp    z0.d, p0.d
+	SQINCP    Z0.D, P0.D
+	sqincp    z1.d, p0.d
+	SQINCP    Z1.D, P0.D
+	sqincp    z31.d, p0.d
+	SQINCP    Z31.D, P0.D
+	sqincp    z0.d, p2.d
+	SQINCP    Z0.D, P2.D
+	sqincp    z0.d, p15.d
+	SQINCP    Z0.D, P15.D
+
 	sqincp    x0, p0.b
 	SQINCP    X0, P0.B
 	sqincp    x1, p0.b
@@ -36685,6 +36806,36 @@
 	UQDECP    Z0.D, P2
 	uqdecp    z0.d, p15
 	UQDECP    Z0.D, P15
+	uqdecp    z0.h, p0.h
+	UQDECP    Z0.H, P0.H
+	uqdecp    z1.h, p0.h
+	UQDECP    Z1.H, P0.H
+	uqdecp    z31.h, p0.h
+	UQDECP    Z31.H, P0.H
+	uqdecp    z0.h, p2.h
+	UQDECP    Z0.H, P2.H
+	uqdecp    z0.h, p15.h
+	UQDECP    Z0.H, P15.H
+	uqdecp    z0.s, p0.s
+	UQDECP    Z0.S, P0.S
+	uqdecp    z1.s, p0.s
+	UQDECP    Z1.S, P0.S
+	uqdecp    z31.s, p0.s
+	UQDECP    Z31.S, P0.S
+	uqdecp    z0.s, p2.s
+	UQDECP    Z0.S, P2.S
+	uqdecp    z0.s, p15.s
+	UQDECP    Z0.S, P15.S
+	uqdecp    z0.d, p0.d
+	UQDECP    Z0.D, P0.D
+	uqdecp    z1.d, p0.d
+	UQDECP    Z1.D, P0.D
+	uqdecp    z31.d, p0.d
+	UQDECP    Z31.D, P0.D
+	uqdecp    z0.d, p2.d
+	UQDECP    Z0.D, P2.D
+	uqdecp    z0.d, p15.d
+	UQDECP    Z0.D, P15.D
 	uqdecp    w0, p0.b
 	UQDECP    W0, P0.B
 	uqdecp    w1, p0.b
@@ -38016,6 +38167,36 @@
 	UQINCP    Z0.D, P2
 	uqincp    z0.d, p15
 	UQINCP    Z0.D, P15
+	uqincp    z0.h, p0.h
+	UQINCP    Z0.H, P0.H
+	uqincp    z1.h, p0.h
+	UQINCP    Z1.H, P0.H
+	uqincp    z31.h, p0.h
+	UQINCP    Z31.H, P0.H
+	uqincp    z0.h, p2.h
+	UQINCP    Z0.H, P2.H
+	uqincp    z0.h, p15.h
+	UQINCP    Z0.H, P15.H
+	uqincp    z0.s, p0.s
+	UQINCP    Z0.S, P0.S
+	uqincp    z1.s, p0.s
+	UQINCP    Z1.S, P0.S
+	uqincp    z31.s, p0.s
+	UQINCP    Z31.S, P0.S
+	uqincp    z0.s, p2.s
+	UQINCP    Z0.S, P2.S
+	uqincp    z0.s, p15.s
+	UQINCP    Z0.S, P15.S
+	uqincp    z0.d, p0.d
+	UQINCP    Z0.D, P0.D
+	uqincp    z1.d, p0.d
+	UQINCP    Z1.D, P0.D
+	uqincp    z31.d, p0.d
+	UQINCP    Z31.D, P0.D
+	uqincp    z0.d, p2.d
+	UQINCP    Z0.D, P2.D
+	uqincp    z0.d, p15.d
+	UQINCP    Z0.D, P15.D
 	uqincp    w0, p0.b
 	UQINCP    W0, P0.B
 	uqincp    w1, p0.b
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index de4c452ff04..66c8c0d3560 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1891,7 +1891,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
       break;
 
     case sve_size_hsd:
-      insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
+      insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) % 3 + 1, 0);
       break;
 
     case sve_size_bh:
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 9e98f0d2f20..735baec2f01 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -254,7 +254,7 @@ get_expected_qualifier (const aarch64_inst *inst, int i)
   /* Should not be called if the qualifier is known.  */
   assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL);
   if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
-			       i, qualifiers))
+			       i, qualifiers, 0))
     return qualifiers[i];
   else
     return AARCH64_OPND_QLF_NIL;
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 1d4668a3fbd..db321a58288 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -923,11 +923,10 @@ aarch64_num_of_operands (const aarch64_opcode *opcode)
 
    Apart from serving the main encoding routine, this can also be called
    during or after the operand decoding.  */
-
 int
 aarch64_find_best_match (const aarch64_inst *inst,
 			 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
-			 int stop_at, aarch64_opnd_qualifier_t *ret)
+			 int stop_at, aarch64_opnd_qualifier_t *ret, int start_at)
 {
   int found = 0;
   int i, num_opnds;
@@ -944,7 +943,7 @@ aarch64_find_best_match (const aarch64_inst *inst,
     stop_at = num_opnds - 1;
 
   /* For each pattern.  */
-  for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
+  for (i = start_at, qualifiers_list += start_at; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
     {
       int j;
       qualifiers = *qualifiers_list;
@@ -1027,6 +1026,16 @@ aarch64_find_best_match (const aarch64_inst *inst,
   return 0;
 }
 
+static int
+match_f_strict_qualifier(aarch64_inst *inst, aarch64_opnd_qualifier_seq_t qualifiers){
+  int i, nops;
+  nops = aarch64_num_of_operands (inst->opcode);
+  for (i = 0; i < nops; ++i)
+    if (inst->operands[i].qualifier != qualifiers[i])
+      return false;
+  return true;
+}
+
 /* Operand qualifier matching and resolving.
 
    Return 1 if the operand qualifier(s) in *INST match one of the qualifier
@@ -1038,24 +1047,30 @@ aarch64_find_best_match (const aarch64_inst *inst,
 static int
 match_operands_qualifier (aarch64_inst *inst, bool update_p)
 {
-  int i, nops;
+  int i;
   aarch64_opnd_qualifier_seq_t qualifiers;
 
   if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
-			       qualifiers))
+			       qualifiers, 0))
     {
       DEBUG_TRACE ("matching FAIL");
       return 0;
     }
 
   if (inst->opcode->flags & F_STRICT)
-    {
+  {
       /* Require an exact qualifier match, even for NIL qualifiers.  */
-      nops = aarch64_num_of_operands (inst->opcode);
-      for (i = 0; i < nops; ++i)
-	if (inst->operands[i].qualifier != qualifiers[i])
-	  return false;
-    }
+      if (!match_f_strict_qualifier(inst, qualifiers)){
+        if (inst->opcode->iclass == sve_size_hsd &&
+          aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
+                                   qualifiers, 3))
+        {
+          if (!match_f_strict_qualifier(inst, qualifiers))
+            return false;
+        }
+        else return false;
+      }
+  }
 
   /* Update the qualifiers.  */
   if (update_p)
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 126565dca14..77af455d98f 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -365,7 +365,8 @@ unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 int aarch64_find_best_match (const aarch64_inst *,
 			     const aarch64_opnd_qualifier_seq_t *,
-			     int, aarch64_opnd_qualifier_t *);
+			     int, aarch64_opnd_qualifier_t *,
+			     int);
 
 static inline void
 reset_operand_qualifier (aarch64_inst *inst, int idx)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index cb039d63eba..d36c5850072 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1923,6 +1923,15 @@
   QLF2(S_S,NIL),                                        \
   QLF2(S_D,NIL),                                        \
 }
+#define OP_SVE_Vv_HSD                                   \
+{                                                       \
+  QLF2(S_H,S_H),                                        \
+  QLF2(S_S,S_S),                                        \
+  QLF2(S_D,S_D),                                        \
+  QLF2(S_H,NIL),                                        \
+  QLF2(S_S,NIL),                                        \
+  QLF2(S_D,NIL),                                        \
+}
 #define OP_SVE_VVD_BHS                                  \
 {                                                       \
   QLF3(S_B,S_B,S_D),                                    \
@@ -4200,7 +4209,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("decd", 0x04f0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
   _SVE_INSNC ("dech", 0x0470c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("dech", 0x0470e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-  _SVE_INSNC ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("decp", 0x252d8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
   _SVE_INSNC ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("decw", 0x04b0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
@@ -4325,7 +4334,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("incd", 0x04f0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
   _SVE_INSNC ("inch", 0x0470c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("inch", 0x0470e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-  _SVE_INSNC ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("incp", 0x252c8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
   _SVE_INSNC ("incw", 0x04b0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("incw", 0x04b0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
@@ -4688,7 +4697,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSNC ("sqdech", 0x0460c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("sqdech", 0x0470f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
   _SVE_INSN ("sqdech", 0x0460f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
-  _SVE_INSNC ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("sqdecp", 0x252a8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
   _SVE_INSN ("sqdecp", 0x252a8800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2),
   _SVE_INSNC ("sqdecw", 0x04a0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
@@ -4702,7 +4711,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSNC ("sqinch", 0x0460c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("sqinch", 0x0470f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
   _SVE_INSN ("sqinch", 0x0460f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
-  _SVE_INSNC ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("sqincp", 0x25288c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
   _SVE_INSN ("sqincp", 0x25288800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2),
   _SVE_INSNC ("sqincw", 0x04a0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
@@ -4836,7 +4845,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSNC ("uqdech", 0x0460cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("uqdech", 0x0460fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
   _SVE_INSN ("uqdech", 0x0470fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-  _SVE_INSNC ("uqdecp", 0x252b8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("uqdecp", 0x252b8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("uqdecp", 0x252b8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0),
   _SVE_INSN ("uqdecp", 0x252b8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
   _SVE_INSNC ("uqdecw", 0x04a0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
@@ -4850,7 +4859,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSNC ("uqinch", 0x0460c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("uqinch", 0x0460f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
   _SVE_INSN ("uqinch", 0x0470f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-  _SVE_INSNC ("uqincp", 0x25298000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("uqincp", 0x25298000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("uqincp", 0x25298800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0),
   _SVE_INSN ("uqincp", 0x25298c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
   _SVE_INSNC ("uqincw", 0x04a0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
-- 
2.30.0


  reply	other threads:[~2022-10-09  1:31 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-16  0:53 Shaokun Zhang
2022-02-21 13:13 ` Jan Beulich
2022-03-02  7:36   ` Shaokun Zhang
2022-03-10  9:38     ` Shaokun Zhang
2022-03-10 10:38       ` Jan Beulich
2022-03-10 11:33         ` Shaokun Zhang
2022-03-10 11:50           ` Jan Beulich
2022-03-10 12:24             ` Shaokun Zhang
2022-03-10 12:27 ` Shaokun Zhang
2022-09-12  8:17 ` Richard Sandiford
2022-09-12  8:27   ` Jan Beulich
2022-09-12  9:38     ` Richard Sandiford
2022-09-28  2:19   ` dongbo (E)
2022-09-30 14:54     ` Richard Sandiford
2022-10-09  1:31       ` dongbo (E) [this message]
2022-10-10 10:25         ` Richard Sandiford
2022-10-11  2:19           ` dongbo (E)
2022-10-17  9:33             ` Richard Sandiford
2022-10-18  5:57               ` dongbo (E)

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