From: Gavin Romig-Koch <gavin@cygnus.com>
To: binutils@sourceware.cygnus.com
Subject: tc-mips.c patch
Date: Tue, 19 Oct 1999 11:08:00 -0000 [thread overview]
Message-ID: <m11ddev-000s9uC@cetus.cygnus.com> (raw)
OK to commit?
This is in preparation of the new ISA's, which don't follow the
existing pattern where each ISA is a superset of all the old ones.
-gavin...
* config/tc-mips.c (ISA_HAS_COPROC_DELAYS) : New.
(ISA_HAS_64_BIT_REGS) New.
(gpr_interlocks,md_begin,reg_needs_delay,append_insn,
mips_emit_delays,macro_build,load_register,load_addresss,
macro,macro2,mips_ip,s_cprestore,s_cpadd): Simplify
and/or use new ISA_xxx macros in expressions involving
ISA, particularly mips_opts.isa.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/binutils/binutils/gas/config/tc-mips.c,v
retrieving revision 1.6
diff -c -p -r1.6 tc-mips.c
*** gas/config/tc-mips.c 1999/09/28 04:13:25 1.6
--- gas/config/tc-mips.c 1999/10/19 13:51:51
*************** static int mips_eabi64 = 0;
*** 203,208 ****
--- 203,228 ----
mips3 or greater, then mark the object file 32BITMODE. */
static int mips_32bitmode = 0;
+ /* Some ISA's have delay slots for instructions which read or write
+ from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
+ Return true if instructions marked INSN_LOAD_COPROC_DELAY,
+ INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
+ delay slot in this ISA. The uses of this macro assume that any
+ ISA that has delay slots for one of these, has them for all. They
+ also assume that ISAs which don't have delays for these insns, don't
+ have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
+ #define ISA_HAS_COPROC_DELAYS(ISA) ( \
+ (ISA) == 1 \
+ || (ISA) == 2 \
+ || (ISA) == 3 \
+ )
+
+ /* Return true if ISA supports 64 bit gp register instructions. */
+ #define ISA_HAS_64BIT_REGS(ISA) ( \
+ (ISA) == 3 \
+ || (ISA) == 4 \
+ )
+
/* Whether the processor uses hardware interlocks to protect
reads from the HI and LO registers, and thus does not
require nops to be inserted.
*************** static int mips_32bitmode = 0;
*** 236,242 ****
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs, and thus does not require nops to be inserted. */
#define gpr_interlocks \
! (mips_opts.isa >= 2 \
|| mips_cpu == 3900)
/* As with other "interlocks" this is used by hardware that has FP
--- 256,262 ----
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs, and thus does not require nops to be inserted. */
#define gpr_interlocks \
! (mips_opts.isa != 1 \
|| mips_cpu == 3900)
/* As with other "interlocks" this is used by hardware that has FP
*************** md_begin ()
*** 834,843 ****
if (strcmp (cpu, "mips") == 0)
{
! if (mips_opts.isa < 0)
! mips_cpu = 3000;
! else if (mips_opts.isa == 2)
mips_cpu = 6000;
else if (mips_opts.isa == 3)
--- 854,863 ----
if (strcmp (cpu, "mips") == 0)
{
! if (mips_opts.isa < 0)
! mips_cpu = 3000;
! else if (mips_opts.isa == 2)
mips_cpu = 6000;
else if (mips_opts.isa == 3)
*************** md_begin ()
*** 957,969 ****
a = NULL;
}
! if (mips_opts.isa < 2 && mips_trap)
as_bad (_("trap exception not supported at ISA 1"));
/* Set the EABI kind based on the ISA before the user gets
to change the ISA with directives. This isn't really
the best, but then neither is basing the abi on the isa. */
! if (mips_opts.isa > 2
&& mips_abi_string
&& 0 == strcmp (mips_abi_string,"eabi"))
mips_eabi64 = 1;
--- 977,989 ----
a = NULL;
}
! if (mips_opts.isa == 1 && mips_trap)
as_bad (_("trap exception not supported at ISA 1"));
/* Set the EABI kind based on the ISA before the user gets
to change the ISA with directives. This isn't really
the best, but then neither is basing the abi on the isa. */
! if (ISA_HAS_64BIT_REGS (mips_opts.isa)
&& mips_abi_string
&& 0 == strcmp (mips_abi_string,"eabi"))
mips_eabi64 = 1;
*************** md_begin ()
*** 971,981 ****
if (mips_cpu != 0 && mips_cpu != -1)
{
ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu);
!
/* If they asked for mips1 or mips2 and a cpu that is
mips3 or greater, then mark the object file 32BITMODE. */
if (mips_isa_from_cpu != -1
! && mips_opts.isa <= 2 && mips_isa_from_cpu > 2)
mips_32bitmode = 1;
}
else
--- 991,1002 ----
if (mips_cpu != 0 && mips_cpu != -1)
{
ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu);
!
/* If they asked for mips1 or mips2 and a cpu that is
mips3 or greater, then mark the object file 32BITMODE. */
if (mips_isa_from_cpu != -1
! && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
! && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
mips_32bitmode = 1;
}
else
*************** reg_needs_delay (reg)
*** 1334,1340 ****
prev_pinfo = prev_insn.insn_mo->pinfo;
if (! mips_opts.noreorder
! && mips_opts.isa < 4
&& ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
|| (! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
--- 1355,1361 ----
prev_pinfo = prev_insn.insn_mo->pinfo;
if (! mips_opts.noreorder
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
|| (! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
*************** append_insn (place, ip, address_expr, re
*** 1437,1443 ****
/* The previous insn might require a delay slot, depending upon
the contents of the current insn. */
if (! mips_opts.mips16
! && mips_opts.isa < 4
&& (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
&& ! cop_interlocks)
|| (! gpr_interlocks
--- 1458,1464 ----
/* The previous insn might require a delay slot, depending upon
the contents of the current insn. */
if (! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
&& ! cop_interlocks)
|| (! gpr_interlocks
*************** append_insn (place, ip, address_expr, re
*** 1457,1466 ****
++nops;
}
else if (! mips_opts.mips16
! && mips_opts.isa < 4
&& (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
&& ! cop_interlocks)
! || (mips_opts.isa < 2
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
{
/* A generic coprocessor delay. The previous instruction
--- 1478,1487 ----
++nops;
}
else if (! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
&& ! cop_interlocks)
! || (mips_opts.isa == 1
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
{
/* A generic coprocessor delay. The previous instruction
*************** append_insn (place, ip, address_expr, re
*** 1516,1522 ****
}
}
else if (! mips_opts.mips16
! && mips_opts.isa < 4
&& (prev_pinfo & INSN_WRITE_COND_CODE)
&& ! cop_interlocks)
{
--- 1537,1543 ----
}
}
else if (! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (prev_pinfo & INSN_WRITE_COND_CODE)
&& ! cop_interlocks)
{
*************** append_insn (place, ip, address_expr, re
*** 1593,1599 ****
instruction, we must check for these cases compared to the
instruction previous to the previous instruction. */
if ((! mips_opts.mips16
! && mips_opts.isa < 4
&& (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
&& (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
&& (pinfo & INSN_READ_COND_CODE)
--- 1614,1620 ----
instruction, we must check for these cases compared to the
instruction previous to the previous instruction. */
if ((! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
&& (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
&& (pinfo & INSN_READ_COND_CODE)
*************** append_insn (place, ip, address_expr, re
*** 1943,1955 ****
we can not swap, and I don't feel like handling that
case. */
|| (! mips_opts.mips16
! && mips_opts.isa < 4
&& (pinfo & INSN_READ_COND_CODE))
/* We can not swap with an instruction that requires a
delay slot, becase the target of the branch might
interfere with that instruction. */
|| (! mips_opts.mips16
! && mips_opts.isa < 4
&& (prev_pinfo
/* Itbl support may require additional care here. */
& (INSN_LOAD_COPROC_DELAY
--- 1964,1976 ----
we can not swap, and I don't feel like handling that
case. */
|| (! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (pinfo & INSN_READ_COND_CODE))
/* We can not swap with an instruction that requires a
delay slot, becase the target of the branch might
interfere with that instruction. */
|| (! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (prev_pinfo
/* Itbl support may require additional care here. */
& (INSN_LOAD_COPROC_DELAY
*************** append_insn (place, ip, address_expr, re
*** 1964,1970 ****
&& ! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
! && mips_opts.isa < 2
/* Itbl support may require additional care here. */
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
/* We can not swap with a branch instruction. */
--- 1985,1991 ----
&& ! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
! && mips_opts.isa == 1
/* Itbl support may require additional care here. */
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
/* We can not swap with a branch instruction. */
*************** append_insn (place, ip, address_expr, re
*** 2069,2075 ****
delay, and sets a register that the branch reads, we
can not swap. */
|| (! mips_opts.mips16
! && mips_opts.isa < 4
/* Itbl support may require additional care here. */
&& ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
|| (! gpr_interlocks
--- 2090,2096 ----
delay, and sets a register that the branch reads, we
can not swap. */
|| (! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
/* Itbl support may require additional care here. */
&& ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
|| (! gpr_interlocks
*************** mips_emit_delays (insns)
*** 2285,2291 ****
nops = 0;
if ((! mips_opts.mips16
! && mips_opts.isa < 4
&& (! cop_interlocks
&& (prev_insn.insn_mo->pinfo
& (INSN_LOAD_COPROC_DELAY
--- 2306,2312 ----
nops = 0;
if ((! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& (prev_insn.insn_mo->pinfo
& (INSN_LOAD_COPROC_DELAY
*************** mips_emit_delays (insns)
*** 2300,2313 ****
&& (prev_insn.insn_mo->pinfo
& INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
! && mips_opts.isa < 2
&& (prev_insn.insn_mo->pinfo
& INSN_COPROC_MEMORY_DELAY)))
{
/* Itbl support may require additional care here. */
++nops;
if ((! mips_opts.mips16
! && mips_opts.isa < 4
&& (! cop_interlocks
&& prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
|| (! hilo_interlocks
--- 2321,2334 ----
&& (prev_insn.insn_mo->pinfo
& INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
! && mips_opts.isa == 1
&& (prev_insn.insn_mo->pinfo
& INSN_COPROC_MEMORY_DELAY)))
{
/* Itbl support may require additional care here. */
++nops;
if ((! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
|| (! hilo_interlocks
*************** mips_emit_delays (insns)
*** 2319,2325 ****
nops = 0;
}
else if ((! mips_opts.mips16
! && mips_opts.isa < 4
&& (! cop_interlocks
&& prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
|| (! hilo_interlocks
--- 2340,2346 ----
nops = 0;
}
else if ((! mips_opts.mips16
! && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
|| (! hilo_interlocks
*************** macro_build (place, counter, ep, name, f
*** 2437,2442 ****
--- 2458,2465 ----
/* Search until we get a match for NAME. */
while (1)
{
+ insn_isa = 0;
+
if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1)
insn_isa = 1;
else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2)
*************** macro_build (place, counter, ep, name, f
*** 2445,2456 ****
insn_isa = 3;
else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4)
insn_isa = 4;
- else
- insn_isa = 15;
if (strcmp (fmt, insn.insn_mo->args) == 0
&& insn.insn_mo->pinfo != INSN_MACRO
! && (insn_isa <= mips_opts.isa
|| (mips_cpu == 4650
&& (insn.insn_mo->membership & INSN_4650) != 0)
|| (mips_cpu == 4010
--- 2468,2478 ----
insn_isa = 3;
else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4)
insn_isa = 4;
if (strcmp (fmt, insn.insn_mo->args) == 0
&& insn.insn_mo->pinfo != INSN_MACRO
! && ((insn_isa != 0
! && insn_isa <= mips_opts.isa)
|| (mips_cpu == 4650
&& (insn.insn_mo->membership & INSN_4650) != 0)
|| (mips_cpu == 4010
*************** load_register (counter, reg, ep, dbl)
*** 2960,2968 ****
|| ! ep->X_unsigned
|| sizeof (ep->X_add_number) > 4
|| (ep->X_add_number & 0x80000000) == 0))
! || ((mips_opts.isa < 3 || ! dbl)
&& (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
! || (mips_opts.isa < 3
&& ! dbl
&& ((ep->X_add_number &~ (offsetT) 0xffffffff)
== ~ (offsetT) 0xffffffff)))
--- 2982,2990 ----
|| ! ep->X_unsigned
|| sizeof (ep->X_add_number) > 4
|| (ep->X_add_number & 0x80000000) == 0))
! || ((! ISA_HAS_64BIT_REGS (mips_opts.isa) || ! dbl)
&& (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
! || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
&& ! dbl
&& ((ep->X_add_number &~ (offsetT) 0xffffffff)
== ~ (offsetT) 0xffffffff)))
*************** load_register (counter, reg, ep, dbl)
*** 2979,2985 ****
/* The value is larger than 32 bits. */
! if (mips_opts.isa < 3)
{
as_bad (_("Number larger than 32 bits"));
macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
--- 3001,3007 ----
/* The value is larger than 32 bits. */
! if (! ISA_HAS_64BIT_REGS (mips_opts.isa))
{
as_bad (_("Number larger than 32 bits"));
macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
*************** load_address (counter, reg, ep)
*** 3220,3226 ****
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
--- 3242,3248 ----
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
*************** load_address (counter, reg, ep)
*** 3233,3239 ****
p += 4;
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
--- 3255,3261 ----
p += 4;
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
*************** load_address (counter, reg, ep)
*** 3253,3259 ****
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
--- 3275,3281 ----
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
*************** load_address (counter, reg, ep)
*** 3262,3268 ****
ep->X_add_symbol, (offsetT) 0, (char *) NULL);
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
--- 3284,3290 ----
ep->X_add_symbol, (offsetT) 0, (char *) NULL);
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
*************** load_address (counter, reg, ep)
*** 3272,3278 ****
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
--- 3294,3300 ----
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
*************** load_address (counter, reg, ep)
*** 3303,3314 ****
(int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, counter, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", reg, reg, GP);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
p = frag_var (rs_machine_dependent, 12 + off, 0,
--- 3325,3336 ----
(int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, counter, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", reg, reg, GP);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
p = frag_var (rs_machine_dependent, 12 + off, 0,
*************** load_address (counter, reg, ep)
*** 3326,3332 ****
}
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
--- 3348,3354 ----
}
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
*************** load_address (counter, reg, ep)
*** 3334,3340 ****
p += 4;
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
--- 3356,3362 ----
p += 4;
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
*************** load_address (counter, reg, ep)
*** 3344,3350 ****
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
--- 3366,3372 ----
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
*************** load_address (counter, reg, ep)
*** 3356,3362 ****
*/
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
--- 3378,3384 ----
*/
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
*************** macro (ip)
*** 3564,3570 ****
case M_BGT_I:
/* check for > max integer */
maxnum = 0x7fffffff;
! if (mips_opts.isa >= 3 && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
--- 3586,3592 ----
case M_BGT_I:
/* check for > max integer */
maxnum = 0x7fffffff;
! if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
*************** macro (ip)
*** 3573,3579 ****
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
! && (mips_opts.isa < 3 || sizeof (maxnum) > 4))
{
do_false:
/* result is always false */
--- 3595,3601 ----
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
! && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
{
do_false:
/* result is always false */
*************** macro (ip)
*** 3613,3619 ****
return;
}
maxnum = 0x7fffffff;
! if (mips_opts.isa >= 3 && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
--- 3635,3641 ----
return;
}
maxnum = 0x7fffffff;
! if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
*************** macro (ip)
*** 3623,3629 ****
maxnum = - maxnum - 1;
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number <= maxnum
! && (mips_opts.isa < 3 || sizeof (maxnum) > 4))
{
do_true:
/* result is always true */
--- 3645,3651 ----
maxnum = - maxnum - 1;
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number <= maxnum
! && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
{
do_true:
/* result is always true */
*************** macro (ip)
*** 3660,3666 ****
likely = 1;
case M_BGTU_I:
if (sreg == 0
! || (mips_opts.isa < 3
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_false;
--- 3682,3688 ----
likely = 1;
case M_BGTU_I:
if (sreg == 0
! || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_false;
*************** macro (ip)
*** 3756,3762 ****
likely = 1;
case M_BLE_I:
maxnum = 0x7fffffff;
! if (mips_opts.isa >= 3 && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
--- 3778,3784 ----
likely = 1;
case M_BLE_I:
maxnum = 0x7fffffff;
! if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
*************** macro (ip)
*** 3765,3771 ****
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
! && (mips_opts.isa < 3 || sizeof (maxnum) > 4))
goto do_true;
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
--- 3787,3793 ----
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
! && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
goto do_true;
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
*************** macro (ip)
*** 3818,3824 ****
likely = 1;
case M_BLEU_I:
if (sreg == 0
! || (mips_opts.isa < 3
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_true;
--- 3840,3846 ----
likely = 1;
case M_BLEU_I:
if (sreg == 0
! || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_true;
*************** macro (ip)
*** 4117,4123 ****
treg, (int) BFD_RELOC_PCREL_HI16_S);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
return;
--- 4139,4145 ----
treg, (int) BFD_RELOC_PCREL_HI16_S);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
return;
*************** macro (ip)
*** 4160,4166 ****
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
--- 4182,4188 ----
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
*************** macro (ip)
*** 4174,4180 ****
p += 4;
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
}
--- 4196,4202 ----
p += 4;
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
}
*************** macro (ip)
*** 4241,4247 ****
}
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If breg == 0, and the next instruction uses
--- 4263,4269 ----
}
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If breg == 0, and the next instruction uses
*************** macro (ip)
*** 4255,4261 ****
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
(void) frag_var (rs_machine_dependent, 0, 0,
--- 4277,4283 ----
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
(void) frag_var (rs_machine_dependent, 0, 0,
*************** macro (ip)
*** 4282,4288 ****
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
breg = 0;
--- 4304,4310 ----
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
breg = 0;
*************** macro (ip)
*** 4299,4310 ****
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, AT);
(void) frag_var (rs_machine_dependent, 0, 0,
--- 4321,4332 ----
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, AT);
(void) frag_var (rs_machine_dependent, 0, 0,
*************** macro (ip)
*** 4365,4371 ****
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
--- 4387,4393 ----
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
*************** macro (ip)
*** 4404,4410 ****
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
--- 4426,4432 ----
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
*************** macro (ip)
*** 4439,4445 ****
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
dreg = treg;
--- 4461,4467 ----
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
dreg = treg;
*************** macro (ip)
*** 4455,4466 ****
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", dreg, dreg, AT);
--- 4477,4488 ----
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", dreg, dreg, AT);
*************** macro (ip)
*** 4494,4500 ****
p += 4;
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If add_number is 0, and there was no base
--- 4516,4522 ----
p += 4;
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If add_number is 0, and there was no base
*************** macro (ip)
*** 4514,4520 ****
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
p += 4;
--- 4536,4542 ----
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
p += 4;
*************** macro (ip)
*** 4528,4540 ****
p += 4;
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, AT);
p += 4;
--- 4550,4562 ----
p += 4;
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, AT);
p += 4;
*************** macro (ip)
*** 4547,4553 ****
*/
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
--- 4569,4575 ----
*/
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
*************** macro (ip)
*** 4557,4563 ****
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", treg, tempreg, breg);
--- 4579,4585 ----
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", treg, tempreg, breg);
*************** macro (ip)
*** 4601,4607 ****
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg);
}
--- 4623,4629 ----
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg);
}
*************** macro (ip)
*** 4644,4650 ****
{
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL16, GP);
--- 4666,4672 ----
{
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL16, GP);
*************** macro (ip)
*** 4667,4678 ****
PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
--- 4689,4700 ----
PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
*************** macro (ip)
*** 4690,4696 ****
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_GOT16, GP);
--- 4712,4718 ----
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_GOT16, GP);
*************** macro (ip)
*** 4700,4706 ****
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
(int) BFD_RELOC_LO16);
--- 4722,4728 ----
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
(int) BFD_RELOC_LO16);
*************** macro (ip)
*** 4716,4722 ****
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", GP, (int) BFD_RELOC_LO16,
mips_frame_reg);
--- 4738,4744 ----
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", GP, (int) BFD_RELOC_LO16,
mips_frame_reg);
*************** macro (ip)
*** 4973,4979 ****
frag_grow (28);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
--- 4995,5001 ----
frag_grow (28);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
*************** macro (ip)
*** 4988,4994 ****
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
if (p != NULL)
--- 5010,5016 ----
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
if (p != NULL)
*************** macro (ip)
*** 5023,5029 ****
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
--- 5045,5051 ----
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
*************** macro (ip)
*** 5033,5045 ****
(char *) NULL);
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
--- 5055,5067 ----
(char *) NULL);
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
*************** macro (ip)
*** 5080,5091 ****
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
tempreg);
--- 5102,5113 ----
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
tempreg);
*************** macro (ip)
*** 5099,5105 ****
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
--- 5121,5127 ----
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
*************** macro (ip)
*** 5107,5119 ****
p += 4;
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
--- 5129,5141 ----
p += 4;
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
*************** macro (ip)
*** 5138,5144 ****
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
--- 5160,5166 ----
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
*************** macro (ip)
*** 5189,5195 ****
or in offset_expr. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
! if (mips_opts.isa >= 3)
load_register (&icnt, treg, &imm_expr, 1);
else
{
--- 5211,5217 ----
or in offset_expr. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
! if (ISA_HAS_64BIT_REGS (mips_opts.isa))
load_register (&icnt, treg, &imm_expr, 1);
else
{
*************** macro (ip)
*** 5234,5240 ****
{
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
}
--- 5256,5262 ----
{
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
}
*************** macro (ip)
*** 5244,5250 ****
a single instruction. */
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL);
offset_expr.X_op = O_constant;
--- 5266,5272 ----
a single instruction. */
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL);
offset_expr.X_op = O_constant;
*************** macro (ip)
*** 5254,5260 ****
abort ();
/* Now we load the register(s). */
! if (mips_opts.isa >= 3)
macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
treg, (int) BFD_RELOC_LO16, AT);
else
--- 5276,5282 ----
abort ();
/* Now we load the register(s). */
! if (ISA_HAS_64BIT_REGS (mips_opts.isa))
macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
treg, (int) BFD_RELOC_LO16, AT);
else
*************** macro (ip)
*** 5285,5292 ****
or in offset_expr. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
! load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3);
! if (mips_opts.isa >= 3)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"dmtc1", "t,S", AT, treg);
else
--- 5307,5314 ----
or in offset_expr. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
! load_register (&icnt, AT, &imm_expr, ISA_HAS_64BIT_REGS (mips_opts.isa));
! if (ISA_HAS_64BIT_REGS (mips_opts.isa))
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"dmtc1", "t,S", AT, treg);
else
*************** macro (ip)
*** 5312,5318 ****
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
! if (mips_opts.isa >= 2)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
--- 5334,5340 ----
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
! if (mips_opts.isa != 1)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
*************** macro (ip)
*** 5328,5334 ****
if (mips_pic == SVR4_PIC)
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
else
--- 5350,5356 ----
if (mips_pic == SVR4_PIC)
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
else
*************** macro (ip)
*** 5337,5343 ****
macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
}
! if (mips_opts.isa >= 2)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
--- 5359,5365 ----
macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
}
! if (mips_opts.isa != 1)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
*************** macro (ip)
*** 5364,5370 ****
to adjust when loading from memory. */
r = BFD_RELOC_LO16;
dob:
! assert (mips_opts.isa < 2);
macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg,
(int) r, breg);
--- 5386,5392 ----
to adjust when loading from memory. */
r = BFD_RELOC_LO16;
dob:
! assert (mips_opts.isa == 1);
macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg,
(int) r, breg);
*************** macro (ip)
*** 5403,5409 ****
}
/* Itbl support may require additional care here. */
coproc = 1;
! if (mips_opts.isa >= 2)
{
s = "ldc1";
goto ld;
--- 5425,5431 ----
}
/* Itbl support may require additional care here. */
coproc = 1;
! if (mips_opts.isa != 1)
{
s = "ldc1";
goto ld;
*************** macro (ip)
*** 5420,5426 ****
return;
}
! if (mips_opts.isa >= 2)
{
s = "sdc1";
goto st;
--- 5442,5448 ----
return;
}
! if (mips_opts.isa != 1)
{
s = "sdc1";
goto st;
*************** macro (ip)
*** 5433,5439 ****
goto ldd_std;
case M_LD_AB:
! if (mips_opts.isa >= 3)
{
s = "ld";
goto ld;
--- 5455,5461 ----
goto ldd_std;
case M_LD_AB:
! if (ISA_HAS_64BIT_REGS (mips_opts.isa))
{
s = "ld";
goto ld;
*************** macro (ip)
*** 5444,5450 ****
goto ldd_std;
case M_SD_AB:
! if (mips_opts.isa >= 3)
{
s = "sd";
goto st;
--- 5466,5472 ----
goto ldd_std;
case M_SD_AB:
! if (ISA_HAS_64BIT_REGS (mips_opts.isa))
{
s = "sd";
goto st;
*************** macro (ip)
*** 5507,5513 ****
frag_grow (36);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, breg, GP);
tempreg = AT;
--- 5529,5535 ----
frag_grow (36);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, GP);
tempreg = AT;
*************** macro (ip)
*** 5565,5571 ****
{
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
if (p != NULL)
--- 5587,5593 ----
{
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
if (p != NULL)
*************** macro (ip)
*** 5614,5627 ****
frag_grow (24 + off);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
--- 5636,5649 ----
frag_grow (24 + off);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
*************** macro (ip)
*** 5683,5701 ****
AT, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, AT, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
--- 5705,5723 ----
AT, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
*************** macro (ip)
*** 5727,5733 ****
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
--- 5749,5755 ----
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
*************** macro (ip)
*** 5737,5743 ****
{
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
p += 4;
--- 5759,5765 ----
{
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
p += 4;
*************** macro (ip)
*** 5778,5784 ****
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, breg, GP);
tempreg = AT;
--- 5800,5806 ----
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, GP);
tempreg = AT;
*************** macro (ip)
*** 5809,5815 ****
case M_SD_OB:
s = "sw";
sd_ob:
! assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3);
macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
(int) BFD_RELOC_LO16, breg);
offset_expr.X_add_number += 4;
--- 5831,5838 ----
case M_SD_OB:
s = "sw";
sd_ob:
! assert (bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa));
macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
(int) BFD_RELOC_LO16, breg);
offset_expr.X_add_number += 4;
*************** macro2 (ip)
*** 6047,6053 ****
as_bad (_("opcode not supported on this processor"));
return;
}
! assert (mips_opts.isa < 2);
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when storing to memory. */
macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
--- 6070,6076 ----
as_bad (_("opcode not supported on this processor"));
return;
}
! assert (mips_opts.isa == 1);
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when storing to memory. */
macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
*************** macro2 (ip)
*** 6104,6110 ****
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", dreg, sreg,
(int) BFD_RELOC_LO16);
--- 6127,6133 ----
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", dreg, sreg,
(int) BFD_RELOC_LO16);
*************** macro2 (ip)
*** 6257,6263 ****
ip->insn_mo->name);
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
return;
--- 6280,6286 ----
ip->insn_mo->name);
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
return;
*************** macro2 (ip)
*** 6277,6283 ****
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addiu" : "daddiu"),
"t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
used_at = 0;
--- 6300,6306 ----
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
used_at = 0;
*************** macro2 (ip)
*** 6356,6362 ****
case M_TRUNCWD:
case M_TRUNCWS:
! assert (mips_opts.isa < 2);
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
--- 6379,6385 ----
case M_TRUNCWD:
case M_TRUNCWS:
! assert (mips_opts.isa == 1);
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
*************** macro2 (ip)
*** 6446,6452 ****
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
--- 6469,6475 ----
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
*************** macro2 (ip)
*** 6469,6475 ****
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (target_big_endian)
--- 6492,6498 ----
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (target_big_endian)
*************** macro2 (ip)
*** 6543,6549 ****
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
--- 6566,6572 ----
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
*************** macro2 (ip)
*** 6565,6571 ****
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
--- 6588,6594 ----
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
*************** mips_ip (str, ip)
*** 7010,7015 ****
--- 7033,7039 ----
assert (strcmp (insn->name, str) == 0);
+ insn_isa = 0;
if ((insn->membership & INSN_ISA) == INSN_ISA1)
insn_isa = 1;
else if ((insn->membership & INSN_ISA) == INSN_ISA2)
*************** mips_ip (str, ip)
*** 7018,7027 ****
insn_isa = 3;
else if ((insn->membership & INSN_ISA) == INSN_ISA4)
insn_isa = 4;
- else
- insn_isa = 15;
! if (insn_isa <= mips_opts.isa)
ok = true;
else if (insn->pinfo == INSN_MACRO)
ok = false;
--- 7042,7050 ----
insn_isa = 3;
else if ((insn->membership & INSN_ISA) == INSN_ISA4)
insn_isa = 4;
! if (insn_isa != 0
! && insn_isa <= mips_opts.isa)
ok = true;
else if (insn->pinfo == INSN_MACRO)
ok = false;
*************** mips_ip (str, ip)
*** 7050,7056 ****
++insn;
continue;
}
! if (insn_isa == 15
|| insn_isa <= mips_opts.isa)
insn_error = _("opcode not supported on this processor");
else
--- 7073,7080 ----
++insn;
continue;
}
!
! if (insn_isa == 0
|| insn_isa <= mips_opts.isa)
insn_error = _("opcode not supported on this processor");
else
*************** mips_ip (str, ip)
*** 7422,7428 ****
as_bad (_("Invalid float register number (%d)"), regno);
if ((regno & 1) != 0
! && mips_opts.isa < 3
&& ! (strcmp (str, "mtc1") == 0
|| strcmp (str, "mfc1") == 0
|| strcmp (str, "lwc1") == 0
--- 7446,7452 ----
as_bad (_("Invalid float register number (%d)"), regno);
if ((regno & 1) != 0
! && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
&& ! (strcmp (str, "mtc1") == 0
|| strcmp (str, "mfc1") == 0
|| strcmp (str, "lwc1") == 0
*************** mips_ip (str, ip)
*** 7575,7581 ****
offset_expr to the low order 32 bits.
Otherwise, set imm_expr to the entire 64 bit
constant. */
! if (mips_opts.isa < 3)
{
imm_expr.X_op = O_constant;
offset_expr.X_op = O_constant;
--- 7599,7605 ----
offset_expr to the low order 32 bits.
Otherwise, set imm_expr to the entire 64 bit
constant. */
! if (! ISA_HAS_64BIT_REGS (mips_opts.isa))
{
imm_expr.X_op = O_constant;
offset_expr.X_op = O_constant;
*************** mips_ip (str, ip)
*** 7744,7750 ****
&& imm_expr.X_op == O_constant)
|| (more
&& imm_expr.X_add_number < 0
! && mips_opts.isa >= 3
&& imm_expr.X_unsigned
&& sizeof (imm_expr.X_add_number) <= 4))
{
--- 7768,7774 ----
&& imm_expr.X_op == O_constant)
|| (more
&& imm_expr.X_add_number < 0
! && ISA_HAS_64BIT_REGS (mips_opts.isa)
&& imm_expr.X_unsigned
&& sizeof (imm_expr.X_add_number) <= 4))
{
*************** s_cprestore (ignore)
*** 10338,10344 ****
macro_build ((char *) NULL, &icnt, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "sw" : "sd"),
"t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
--- 10362,10368 ----
macro_build ((char *) NULL, &icnt, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "sw" : "sd"),
"t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
*************** s_cpadd (ignore)
*** 10406,10412 ****
reg = tc_get_register (0);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || mips_opts.isa < 3)
? "addu" : "daddu"),
"d,v,t", reg, reg, GP);
--- 10430,10436 ----
reg = tc_get_register (0);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
! || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", reg, reg, GP);
next reply other threads:[~1999-10-19 11:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
1999-10-19 11:08 Gavin Romig-Koch [this message]
1999-10-19 22:41 ` Ian Lance Taylor
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