Re: [Patch] TX49xx support

Re: [Patch] TX49xx support

[Nick Clifton]

Hi Shane,

> The following adds support for two special features within the TX49,
 
> Please let me know what changes need to be made for acceptance, and
> whether these types of changes are being accepted at this time.  This
> is my first submission to binutils, so if I've done something
> completely wrong please let me know ;-).

Thank you very much for submitting this patch.  The patch itself is
fine, and we are certainly accepting such submission - but - before we
can actually apply it we need you sign over the copyright of the patch
to the FSF.  This is the only way that the FSF can publish the sources
with your patch applied, and thus put it in the public domain.

Please could complete a copyright assignment request form (attached)
and send it off to the FSF.  This will start the ball rolling.  Once
the paperwork has been completed we will be able to accept your patch.

Cheers
        Nick

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---------------------------------------------------------------------------

[Patch] TX49xx support

[Shane Nay]

The following adds support for two special features within the TX49,
which are similar to the TX39.  They are tri-operand mult(u), and
multiply-accumulate instructions (madd(u)).  The difference between
the 39 and the 49 is that the 49 is a MIPS3 processor core with 64bit
registers, whereas the 39 is solely 32bit.  (tx49 also has a single
and double precision FPU, so it's not exactly the same as 4650)

There are also some pipeline enhancements that could be made, but
they have not been implemented in this patch.

I have a matching patch to gcc, which will be submitted after this
one.  It has been tested together on a TX4926, and produced ~50%
reduction in CPU overhead for the mp3 decoder "mad", due primarily to
Robs' hand optimizations for the madd instruction.  (Gcc does emit
them as well, but very infrequently does it find a match for the use
of these instructions)

Please let me know what changes need to be made for acceptance, and
whether these types of changes are being accepted at this time.  This
is my first submission to binutils, so if I've done something
completely wrong please let me know ;-).

The architecture manual is at-
http://pdf.toshiba.com/taec/components/Generic/TX49.pdf

2002-07-29  Shane Nay  <shane@minirl.com>

	* bfd/aoutx.h:  Add support for TX49's extended multiply and
		multiply-accumulate instructions.
	* bfd/archures.c: Likewise
	* bfd/cpu-mips.c: Likewise
	* bfd/elfxx-mips.c: Likewise
	* binutils/readelf.c: Likewise
	* gas/config/tc-mips.c: Likewise
	* include/elf/mips.h: Likewise
	* include/opcode/mips.h: Likewise
	* opcodes/mips-dis.c: Likewise
	* opcodes/mips-opc.c: Likewise

Index: bfd/aoutx.h
===================================================================
RCS file: /cvs/src/src/bfd/aoutx.h,v
retrieving revision 1.30
diff -u -p -r1.30 aoutx.h
--- bfd/aoutx.h	25 Jun 2002 06:21:47 -0000	1.30
+++ bfd/aoutx.h	29 Jul 2002 10:14:34 -0000
@@ -778,6 +778,7 @@ NAME(aout,machine_type) (arch, machine, 
 	case bfd_mach_mips6000:
 	  arch_flags = M_MIPS2;
 	  break;
+	case bfd_mach_mipstx4900:
 	case bfd_mach_mips4000:
 	case bfd_mach_mips4010:
 	case bfd_mach_mips4100:
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.52
diff -u -p -r1.52 archures.c
--- bfd/archures.c	17 Jul 2002 14:15:49 -0000	1.52
+++ bfd/archures.c	29 Jul 2002 10:14:35 -0000
@@ -125,6 +125,7 @@ DESCRIPTION
 .  bfd_arch_mips,      {* MIPS Rxxxx *}
 .#define bfd_mach_mips3000		3000
 .#define bfd_mach_mips3900		3900
+.#define bfd_mach_mipstx4900            4900
 .#define bfd_mach_mips4000		4000
 .#define bfd_mach_mips4010		4010
 .#define bfd_mach_mips4100		4100
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.14
diff -u -p -r1.14 cpu-mips.c
--- bfd/cpu-mips.c	19 May 2002 21:06:34 -0000	1.14
+++ bfd/cpu-mips.c	29 Jul 2002 10:14:40 -0000
@@ -63,6 +63,7 @@ enum
 {
   I_mips3000,
   I_mips3900,
+  I_mipstx4900,
   I_mips4000,
   I_mips4010,
   I_mips4100,
@@ -89,6 +90,7 @@ static const bfd_arch_info_type arch_inf
 {
   N (32, 32, bfd_mach_mips3000, "mips:3000",      false, NN(I_mips3000)),
   N (32, 32, bfd_mach_mips3900, "mips:3900",      false, NN(I_mips3900)),
+  N (64, 64, bfd_mach_mipstx4900, "mips:tx4900",  false, NN(I_mipstx4900)),
   N (64, 64, bfd_mach_mips4000, "mips:4000",      false, NN(I_mips4000)),
   N (64, 64, bfd_mach_mips4010, "mips:4010",      false, NN(I_mips4010)),
   N (64, 64, bfd_mach_mips4100, "mips:4100",      false, NN(I_mips4100)),
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.16
diff -u -p -r1.16 elfxx-mips.c
--- bfd/elfxx-mips.c	26 Jul 2002 18:56:24 -0000	1.16
+++ bfd/elfxx-mips.c	29 Jul 2002 10:14:48 -0000
@@ -3045,6 +3045,9 @@ _bfd_elf_mips_mach (flags)
     case E_MIPS_MACH_3900:
       return bfd_mach_mips3900;
 
+    case E_MIPS_MACH_TX4900:
+      return bfd_mach_mipstx4900;
+      
     case E_MIPS_MACH_4010:
       return bfd_mach_mips4010;
 
@@ -5908,6 +5911,10 @@ _bfd_mips_elf_final_write_processing (ab
       val = E_MIPS_ARCH_1 | E_MIPS_MACH_3900;
       break;
 
+    case bfd_mach_mipstx4900:
+      val = E_MIPS_ARCH_3 | E_MIPS_MACH_TX4900;
+      break;
+      
     case bfd_mach_mips6000:
       val = E_MIPS_ARCH_2;
       break;
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.167
diff -u -p -r1.167 readelf.c
--- binutils/readelf.c	18 Jul 2002 11:11:13 -0000	1.167
+++ binutils/readelf.c	29 Jul 2002 10:14:58 -0000
@@ -1816,12 +1816,13 @@ get_machine_flags (e_flags, e_machine)
 
 	  switch ((e_flags & EF_MIPS_MACH))
 	    {
-	    case E_MIPS_MACH_3900: strcat (buf, ", 3900"); break;
-	    case E_MIPS_MACH_4010: strcat (buf, ", 4010"); break;
-	    case E_MIPS_MACH_4100: strcat (buf, ", 4100"); break;
-	    case E_MIPS_MACH_4650: strcat (buf, ", 4650"); break;
-	    case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
-	    case E_MIPS_MACH_SB1:  strcat (buf, ", sb1");  break;
+	    case E_MIPS_MACH_3900:   strcat (buf, ", 3900"); break;
+	    case E_MIPS_MACH_4010:   strcat (buf, ", 4010"); break;
+	    case E_MIPS_MACH_4100:   strcat (buf, ", 4100"); break;
+	    case E_MIPS_MACH_4650:   strcat (buf, ", 4650"); break;
+	    case E_MIPS_MACH_4111:   strcat (buf, ", 4111"); break;
+	    case E_MIPS_MACH_SB1:    strcat (buf, ", sb1");  break;
+	    case E_MIPS_MACH_TX4900: strcat (buf, ", tx49"); break;
 	    case 0:
 	    /* We simply ignore the field in this case to avoid confusion:
 	       MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.151
diff -u -p -r1.151 tc-mips.c
--- gas/config/tc-mips.c	25 Jul 2002 11:07:47 -0000	1.151
+++ gas/config/tc-mips.c	29 Jul 2002 10:15:12 -0000
@@ -13458,7 +13458,8 @@ static const struct mips_cpu_info mips_c
   { "r4600",          0,      ISA_MIPS3,      CPU_R4600 },
   { "orion",          0,      ISA_MIPS3,      CPU_R4600 },
   { "r4650",          0,      ISA_MIPS3,      CPU_R4650 },
-
+  { "tx49",           0,      ISA_MIPS3,      CPU_TX4900 },
+  
   /* MIPS IV */
   { "r8000",          0,      ISA_MIPS4,      CPU_R8000 },
   { "r10000",         0,      ISA_MIPS4,      CPU_R10000 },
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.16
diff -u -p -r1.16 mips.h
--- include/elf/mips.h	31 Aug 2001 21:21:54 -0000	1.16
+++ include/elf/mips.h	29 Jul 2002 10:15:16 -0000
@@ -177,6 +177,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_4650	0x00850000
 #define E_MIPS_MACH_4111	0x00880000
 #define E_MIPS_MACH_SB1         0x008a0000
+#define E_MIPS_MACH_TX4900      0x008c0000
  
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.28
diff -u -p -r1.28 mips.h
--- include/opcode/mips.h	25 Jul 2002 09:44:39 -0000	1.28
+++ include/opcode/mips.h	29 Jul 2002 10:15:17 -0000
@@ -362,6 +362,8 @@ struct mips_opcode
 #define INSN_10000                0x00100000
 /* Broadcom SB-1 instruction.  */
 #define INSN_SB1                  0x00200000
+/* Toshiba TX49 instruction. */
+#define INSN_TX4900               0x00400000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -387,6 +389,7 @@ struct mips_opcode
 #define CPU_R4400	4400
 #define CPU_R4600	4600
 #define CPU_R4650	4650
+#define CPU_TX4900      4900
 #define CPU_R5000	5000
 #define CPU_R6000	6000
 #define CPU_R8000	8000
@@ -406,6 +409,7 @@ struct mips_opcode
 #define OPCODE_IS_MEMBER(insn, isa, cpu)				\
     (((insn)->membership & isa) != 0					\
      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)	\
+     || (cpu == CPU_TX4900 && ((insn)->membership & INSN_TX4900) != 0)  \
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)	\
      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)			\
 	 && ((insn)->membership & INSN_4100) != 0)			\
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.31
diff -u -p -r1.31 mips-dis.c
--- opcodes/mips-dis.c	9 Jul 2002 14:21:40 -0000	1.31
+++ opcodes/mips-dis.c	29 Jul 2002 10:15:21 -0000
@@ -358,6 +358,10 @@ mips_isa_type (mach, isa, cputype)
       *cputype = CPU_R3900;
       *isa = ISA_MIPS1;
       break;
+    case bfd_mach_mipstx4900:
+      *cputype = CPU_TX4900;
+      *isa = ISA_MIPS3;
+      break;
     case bfd_mach_mips4000:
       *cputype = CPU_R4000;
       *isa = ISA_MIPS3;
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.37
diff -u -p -r1.37 mips-opc.c
--- opcodes/mips-opc.c	9 Jul 2002 14:21:40 -0000	1.37
+++ opcodes/mips-opc.c	29 Jul 2002 10:15:23 -0000
@@ -99,10 +99,11 @@ Software Foundation, 59 Temple Place - S
 #define L1	INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
+#define T4      INSN_TX4900
 #define M1	INSN_10000
 #define SB1     INSN_SB1
 
-#define G1      (T3             \
+#define G1      (T3 | T4        \
                  )
 
 #define G2      (T3             \