[PATCH] Performance counter opcodes for MIPS R1[02]000

[PATCH] Performance counter opcodes for MIPS R1[02]000

[Thiemo Seufer]

Hi All,

this patch adds the performance counter opcodes for R1[02]000
(mtpc, mfpc mtps, mfps) and fixes the naming of coprocessor
registers.


Thiemo


2001-05-30  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>

	/gas/testsuite/ChangeLog
	* gas/mips/mips32.d: Update to use hardware names for coprocessor
	registers.
	* gas/mips/mips64.d: Likewise.

	/include/opcode/ChangeLog
	* mips.h (INSN_10000): Define.
	(OPCODE_IS_MEMBER): Add check for R1[02]000.

	/opcodes/ChangeLog
	* mips-dis.c (print_insn_arg): Don't use (wrong) symbolic names for
	coprocessor registers.
	* mips-opc.c (M1): Define.
	(mips_builtin_opcodes): Add performance counter insns. Typo.


diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips32.d src/gas/testsuite/gas/mips/mips32.d
--- src-orig/gas/testsuite/gas/mips/mips32.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips32.d	Wed May 30 03:28:03 2001
@@ -26,15 +26,15 @@
 0+0040 <[^>]*> 00000000 	nop
 0+0044 <[^>]*> 4903ffee 	bc2tl	0+0000 <text_label>
 0+0048 <[^>]*> 00000000 	nop
-0+004c <[^>]*> 48411000 	cfc2	at,v0
+0+004c <[^>]*> 48411000 	cfc2	at,$2
 0+0050 <[^>]*> 4b234567 	c2	0x1234567
-0+0054 <[^>]*> 48c21800 	ctc2	v0,v1
-0+0058 <[^>]*> 48032000 	mfc2	v1,a0
-0+005c <[^>]*> 48042800 	mfc2	a0,a1
-0+0060 <[^>]*> 48053007 	mfc2	a1,a2,7
-0+0064 <[^>]*> 48863800 	mtc2	a2,a3
-0+0068 <[^>]*> 48874000 	mtc2	a3,t0
-0+006c <[^>]*> 48884807 	mtc2	t0,t1,7
+0+0054 <[^>]*> 48c21800 	ctc2	v0,$3
+0+0058 <[^>]*> 48032000 	mfc2	v1,$4
+0+005c <[^>]*> 48042800 	mfc2	a0,$5
+0+0060 <[^>]*> 48053007 	mfc2	a1,$6,7
+0+0064 <[^>]*> 48863800 	mtc2	a2,$7
+0+0068 <[^>]*> 48874000 	mtc2	a3,$8
+0+006c <[^>]*> 48884807 	mtc2	t0,$9,7
 0+0070 <[^>]*> bc250000 	cache	0x5,0\(at\)
 0+0074 <[^>]*> bc457fff 	cache	0x5,32767\(v0\)
 0+0078 <[^>]*> bc658000 	cache	0x5,-32768\(v1\)
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips64.d src/gas/testsuite/gas/mips/mips64.d
--- src-orig/gas/testsuite/gas/mips/mips64.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips64.d	Wed May 30 03:30:07 2001
@@ -9,9 +9,9 @@
 Disassembly of section .text:
 0+0000 <[^>]*> 70410825 	dclo	at,v0
 0+0004 <[^>]*> 70831824 	dclz	v1,a0
-0+0008 <[^>]*> 48232000 	dmfc2	v1,a0
-0+000c <[^>]*> 48242800 	dmfc2	a0,a1
-0+0010 <[^>]*> 48253007 	dmfc2	a1,a2,7
-0+0014 <[^>]*> 48a63800 	dmtc2	a2,a3
-0+0018 <[^>]*> 48a74000 	dmtc2	a3,t0
-0+001c <[^>]*> 48a84807 	dmtc2	t0,t1,7
+0+0008 <[^>]*> 48232000 	dmfc2	v1,$4
+0+000c <[^>]*> 48242800 	dmfc2	a0,$5
+0+0010 <[^>]*> 48253007 	dmfc2	a1,$6,7
+0+0014 <[^>]*> 48a63800 	dmtc2	a2,$7
+0+0018 <[^>]*> 48a74000 	dmtc2	a3,$8
+0+001c <[^>]*> 48a84807 	dmtc2	t0,$9,7
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/include/opcode/mips.h src/include/opcode/mips.h
--- src-orig/include/opcode/mips.h	Wed May 23 21:09:08 2001
+++ src/include/opcode/mips.h	Tue May 29 23:32:43 2001
@@ -326,8 +326,10 @@
 #define INSN_4100                 0x00040000
 /* Toshiba R3900 instruction.  */
 #define INSN_3900                 0x00080000
+/* MIPS R1[02]000 instruction.  */
+#define INSN_10000                0x00100000
 /* 32-bit code running on a ISA3+ CPU.  */
-#define INSN_GP32                 0x00100000
+#define INSN_GP32                 0x00200000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -382,7 +384,9 @@
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)	\
      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)			\
 	 && ((insn)->membership & INSN_4100) != 0)			\
-     || (cpu == CPU_R3900  && ((insn)->membership & INSN_3900) != 0))
+     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)	\
+     || ((cpu == CPU_R10000 || cpu == CPU_R12000)			\
+	 && ((insn)->membership & INSN_10000) != 0))
 
 /* This is a list of macro expanded instructions.
 
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/opcodes/mips-dis.c src/opcodes/mips-dis.c
--- src-orig/opcodes/mips-dis.c	Wed May 23 21:09:17 2001
+++ src/opcodes/mips-dis.c	Tue May 29 23:32:43 2001
@@ -256,13 +256,13 @@
       break;
 
     case 'E':
-      (*info->fprintf_func) (info->stream, "%s",
-			     reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+      (*info->fprintf_func) (info->stream, "$%d",
+			     (l >> OP_SH_RT) & OP_MASK_RT);
       break;
 
     case 'G':
-      (*info->fprintf_func) (info->stream, "%s",
-			     reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+      (*info->fprintf_func) (info->stream, "$%d",
+			     (l >> OP_SH_RD) & OP_MASK_RD);
       break;
 
     case 'N':
@@ -276,7 +276,7 @@
       break;
 
     case 'P':
-      (*info->fprintf_func) (info->stream, "%d",
+      (*info->fprintf_func) (info->stream, "$%d",
 			     (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
       break;
 
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/opcodes/mips-opc.c src/opcodes/mips-opc.c
--- src-orig/opcodes/mips-opc.c	Wed Apr  4 18:37:02 2001
+++ src/opcodes/mips-opc.c	Tue May 29 23:32:43 2001
@@ -86,15 +86,16 @@
 #define L1	INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
+#define M1	INSN_10000
 
 #define G1      (T3             \
                  )
 
-#define G2      (T3                   \
+#define G2      (T3             \
                  )
 
-#define G3 (I4             \
-            )
+#define G3      (I4             \
+                 )
 
 #define G6      INSN_GP32
 
@@ -568,6 +569,8 @@
 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 	I32     },
 {"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,		I1	},
 {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,		I1	},
+{"mfpc",    "t,P",	0x4000c801, 0xffe0ffc1,	LCD|WR_t|RD_C0,		M1	},
+{"mfps",    "t,P",	0x4000c800, 0xffe0ffc1,	LCD|WR_t|RD_C0,		M1	},
 {"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,		I1	},
 {"mov.s",   "D,S",	0x46000006, 0xffff003f,	WR_D|RD_S|FP_S,		I1	},
 {"mov.ps",  "D,S",	0x46c00006, 0xffff003f,	WR_D|RD_S|FP_D,		I5	},
@@ -605,6 +608,8 @@
 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I32     },
 {"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,		I1	},
 {"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,		I1	},
+{"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		M1	},
+{"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		M1	},
 {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
 {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
 {"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
@@ -838,7 +843,7 @@
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
-   disasembler recognizes more specific versions first.  */
+   disassembler recognizes more specific versions first.  */
 {"c0",      "C",	0x42000000, 0xfe000000,	0,			I1	},
 {"c1",      "C",	0x46000000, 0xfe000000,	0,			I1	},
 {"c2",      "C",	0x4a000000, 0xfe000000,	0,			I1	},

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[Nick Clifton]

Hi Thiemo,

> this patch adds the performance counter opcodes for R1[02]000
> (mtpc, mfpc mtps, mfps) and fixes the naming of coprocessor
> registers.

After applying this patch, I am seeing new failures in the GAS
testsuite for a "mips-elf" toolchain:

  FAIL: MIPS lb
  FAIL: MIPS sb
  FAIL: MIPS trunc
  FAIL: MIPS MIPS32 instructions
  FAIL: MIPS MIPS64 instructions

I do not want to accept that patch whilst these problems remain, so
please can you investigate and determine the cause and the correct
solution.

Cheers
        Nick

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[Thiemo Seufer]

Nick Clifton wrote:
[snip]
>After applying this patch, I am seeing new failures in the GAS
>testsuite for a "mips-elf" toolchain:
>
>  FAIL: MIPS lb
>  FAIL: MIPS sb
>  FAIL: MIPS trunc
>  FAIL: MIPS MIPS32 instructions
>  FAIL: MIPS MIPS64 instructions
>
>I do not want to accept that patch whilst these problems remain, so
>please can you investigate and determine the cause and the correct
>solution.

After the situation with mips has settled a bit (and too late for
this release :-( ), here is an updated and fixed patch which
should go well. Performance Counter opcodes aren't in any more
(for now), it only fixes objdump and the according testcases.


Thiemo


2001-06-19  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>

	/gas/testsuite/ChangeLog
	* mips/lb.d: Reflect disassembler output fixes.
	* mips/mips32.d: Likewise.
	* mips/mips4650.d: Likewise.
	* mips/mips64.d: Likewise.
	* mips/sb.d: Likewise.
	* mips/trunc.d: Likewise.

	/opcodes/ChangeLog
	* mips-dis.c (print_insn_arg): Don't use software integer registers
	for coprocessor registers.
	(_print_insn_mips): Get distinction between old ABI and new ABI right.


diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/lb.d src/gas/testsuite/gas/mips/lb.d
--- src-orig/gas/testsuite/gas/mips/lb.d	Tue May 15 16:33:52 2001
+++ src/gas/testsuite/gas/mips/lb.d	Sat Jun 16 19:54:48 2001
@@ -388,8 +388,8 @@
 0+0378 <[^>]*> lw	a0,0\(zero\)
 0+037c <[^>]*> lwl	a0,0\(zero\)
 0+0380 <[^>]*> lwr	a0,0\(zero\)
-0+0384 <[^>]*> lwc0	a0,0\(zero\)
+0+0384 <[^>]*> lwc0	\$4,0\(zero\)
 0+0388 <[^>]*> lwc1	\$f4,0\(zero\)
-0+038c <[^>]*> lwc2	a0,0\(zero\)
-0+0390 <[^>]*> lwc3	a0,0\(zero\)
+0+038c <[^>]*> lwc2	\$4,0\(zero\)
+0+0390 <[^>]*> lwc3	\$4,0\(zero\)
 	...
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips32.d src/gas/testsuite/gas/mips/mips32.d
--- src-orig/gas/testsuite/gas/mips/mips32.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips32.d	Sat Jun 16 20:14:15 2001
@@ -26,15 +26,15 @@
 0+0040 <[^>]*> 00000000 	nop
 0+0044 <[^>]*> 4903ffee 	bc2tl	0+0000 <text_label>
 0+0048 <[^>]*> 00000000 	nop
-0+004c <[^>]*> 48411000 	cfc2	at,v0
+0+004c <[^>]*> 48411000 	cfc2	at,\$2
 0+0050 <[^>]*> 4b234567 	c2	0x1234567
-0+0054 <[^>]*> 48c21800 	ctc2	v0,v1
-0+0058 <[^>]*> 48032000 	mfc2	v1,a0
-0+005c <[^>]*> 48042800 	mfc2	a0,a1
-0+0060 <[^>]*> 48053007 	mfc2	a1,a2,7
-0+0064 <[^>]*> 48863800 	mtc2	a2,a3
-0+0068 <[^>]*> 48874000 	mtc2	a3,t0
-0+006c <[^>]*> 48884807 	mtc2	t0,t1,7
+0+0054 <[^>]*> 48c21800 	ctc2	v0,\$3
+0+0058 <[^>]*> 48032000 	mfc2	v1,\$4
+0+005c <[^>]*> 48042800 	mfc2	a0,\$5
+0+0060 <[^>]*> 48053007 	mfc2	a1,\$6,7
+0+0064 <[^>]*> 48863800 	mtc2	a2,\$7
+0+0068 <[^>]*> 48874000 	mtc2	a3,\$8
+0+006c <[^>]*> 48884807 	mtc2	t0,\$9,7
 0+0070 <[^>]*> bc250000 	cache	0x5,0\(at\)
 0+0074 <[^>]*> bc457fff 	cache	0x5,32767\(v0\)
 0+0078 <[^>]*> bc658000 	cache	0x5,-32768\(v1\)
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips4650.d src/gas/testsuite/gas/mips/mips4650.d
--- src-orig/gas/testsuite/gas/mips/mips4650.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips4650.d	Sat Jun 16 20:08:15 2001
@@ -10,5 +10,5 @@
 	...
 0+000c <stuff\+0xc> madu	a1,a2
 	...
-0+0018 <stuff\+0x18> mul	a2,a3,t0
+0+0018 <stuff\+0x18> mul	a2,a3,a4
 0+001c <stuff\+0x1c> nop
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips64.d src/gas/testsuite/gas/mips/mips64.d
--- src-orig/gas/testsuite/gas/mips/mips64.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips64.d	Sat Jun 16 20:14:49 2001
@@ -9,9 +9,9 @@
 Disassembly of section .text:
 0+0000 <[^>]*> 70410825 	dclo	at,v0
 0+0004 <[^>]*> 70831824 	dclz	v1,a0
-0+0008 <[^>]*> 48232000 	dmfc2	v1,a0
-0+000c <[^>]*> 48242800 	dmfc2	a0,a1
-0+0010 <[^>]*> 48253007 	dmfc2	a1,a2,7
-0+0014 <[^>]*> 48a63800 	dmtc2	a2,a3
-0+0018 <[^>]*> 48a74000 	dmtc2	a3,t0
-0+001c <[^>]*> 48a84807 	dmtc2	t0,t1,7
+0+0008 <[^>]*> 48232000 	dmfc2	v1,\$4
+0+000c <[^>]*> 48242800 	dmfc2	a0,\$5
+0+0010 <[^>]*> 48253007 	dmfc2	a1,\$6,7
+0+0014 <[^>]*> 48a63800 	dmtc2	a2,\$7
+0+0018 <[^>]*> 48a74000 	dmtc2	a3,\$8
+0+001c <[^>]*> 48a84807 	dmtc2	a4,\$9,7
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/sb.d src/gas/testsuite/gas/mips/sb.d
--- src-orig/gas/testsuite/gas/mips/sb.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/sb.d	Sat Jun 16 19:53:41 2001
@@ -386,10 +386,10 @@
 0+0370 <[^>]*> sw	a1,4\(zero\)
 0+0374 <[^>]*> sh	a0,0\(zero\)
 0+0378 <[^>]*> sw	a0,0\(zero\)
-0+037c <[^>]*> swc0	a0,0\(zero\)
+0+037c <[^>]*> swc0	\$4,0\(zero\)
 0+0380 <[^>]*> swc1	\$f4,0\(zero\)
-0+0384 <[^>]*> swc2	a0,0\(zero\)
-0+0388 <[^>]*> swc3	a0,0\(zero\)
+0+0384 <[^>]*> swc2	\$4,0\(zero\)
+0+0388 <[^>]*> swc3	\$4,0\(zero\)
 0+038c <[^>]*> swc1	\$f4,0\(zero\)
 0+0390 <[^>]*> swl	a0,0\(zero\)
 0+0394 <[^>]*> swr	a0,0\(zero\)
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/trunc.d src/gas/testsuite/gas/mips/trunc.d
--- src-orig/gas/testsuite/gas/mips/trunc.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/trunc.d	Sat Jun 16 20:17:40 2001
@@ -7,23 +7,23 @@
 .*: +file format .*mips.*
 
 Disassembly of section .text:
-0+0000 <[^>]*> cfc1	a0,ra
-0+0004 <[^>]*> cfc1	a0,ra
+0+0000 <[^>]*> cfc1	a0,\$31
+0+0004 <[^>]*> cfc1	a0,\$31
 0+0008 <[^>]*> nop
 0+000c <[^>]*> ori	at,a0,0x3
 0+0010 <[^>]*> xori	at,at,0x2
-0+0014 <[^>]*> ctc1	at,ra
+0+0014 <[^>]*> ctc1	at,\$31
 0+0018 <[^>]*> nop
 0+001c <[^>]*> cvt.w.d	\$f4,\$f6
-0+0020 <[^>]*> ctc1	a0,ra
+0+0020 <[^>]*> ctc1	a0,\$31
 0+0024 <[^>]*> nop
-0+0028 <[^>]*> cfc1	a0,ra
-0+002c <[^>]*> cfc1	a0,ra
+0+0028 <[^>]*> cfc1	a0,\$31
+0+002c <[^>]*> cfc1	a0,\$31
 0+0030 <[^>]*> nop
 0+0034 <[^>]*> ori	at,a0,0x3
 0+0038 <[^>]*> xori	at,at,0x2
-0+003c <[^>]*> ctc1	at,ra
+0+003c <[^>]*> ctc1	at,\$31
 0+0040 <[^>]*> nop
 0+0044 <[^>]*> cvt.w.s	\$f4,\$f6
-0+0048 <[^>]*> ctc1	a0,ra
+0+0048 <[^>]*> ctc1	a0,\$31
 0+004c <[^>]*> nop
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/opcodes/mips-dis.c src/opcodes/mips-dis.c
--- src-orig/opcodes/mips-dis.c	Wed May 23 21:09:17 2001
+++ src/opcodes/mips-dis.c	Sat Jun 16 16:27:19 2001
@@ -256,13 +256,13 @@
       break;
 
     case 'E':
-      (*info->fprintf_func) (info->stream, "%s",
-			     reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+      (*info->fprintf_func) (info->stream, "$%d",
+			     (l >> OP_SH_RT) & OP_MASK_RT);
       break;
 
     case 'G':
-      (*info->fprintf_func) (info->stream, "%s",
-			     reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+      (*info->fprintf_func) (info->stream, "$%d",
+			     (l >> OP_SH_RD) & OP_MASK_RD);
       break;
 
     case 'N':
@@ -524,9 +524,9 @@
   /* Use mips64_reg_names for new ABI.  */
   if (info->flavour == bfd_target_elf_flavour
       && info->symbols != NULL
-      && (((get_mips_isa(info) | INSN_ISA_MASK) & ISA_MIPS2) != 0)
+      && ((get_mips_isa(info) & INSN_ISA3) != 0)
       && ((elf_elfheader (bfd_asymbol_bfd(*(info->symbols)))->e_flags
-	   & EF_MIPS_ABI2) != 0))
+	   & (E_MIPS_ABI_O32 | E_MIPS_ABI_O64)) == 0))
     reg_names = mips64_reg_names;
   else
     reg_names = mips32_reg_names;

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[cgd]

I looked over your patch, and found it sensible enough with the
exception of the change:

> 	/opcodes/ChangeLog
> 	(_print_insn_mips): Get distinction between old ABI and new ABI right.

and the related changes in the testsuite (mips4650.d, and mips64.d).


> diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/opcodes/mips-dis.c src/opcodes/mips-dis.c
> --- src-orig/opcodes/mips-dis.c	Wed May 23 21:09:17 2001
> +++ src/opcodes/mips-dis.c	Sat Jun 16 16:27:19 2001
> [ ... ]
> @@ -524,9 +524,9 @@
>    /* Use mips64_reg_names for new ABI.  */
>    if (info->flavour == bfd_target_elf_flavour
>        && info->symbols != NULL
> -      && (((get_mips_isa(info) | INSN_ISA_MASK) & ISA_MIPS2) != 0)
> +      && ((get_mips_isa(info) & INSN_ISA3) != 0)
>        && ((elf_elfheader (bfd_asymbol_bfd(*(info->symbols)))->e_flags
> -	   & EF_MIPS_ABI2) != 0))
> +	   & (E_MIPS_ABI_O32 | E_MIPS_ABI_O64)) == 0))
>      reg_names = mips64_reg_names;
>    else
>      reg_names = mips32_reg_names;

The notion here is that binaries which ELF and are MIPS3 (or better),
and which don't have O32 or O64 indicated are interpreted as using the
'new' (n32/n64) register names?

I'll admit that I've not been following closely for the last month or
so, but I don't understand why this is "Right."  (If there's another
post on the topic that explains, please just point me to it.  8-)


It's certainly a change from existing behaviour, and given that by
default there are no ABI markings on binaries (that I can see;
certainly e.g. the m4650 test just compiled with a clean binutils
build says "[no abi set]"), this may break a bunch of peoples'
expectations w.r.t. disassembly output...



chris

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[Thiemo Seufer]

cgd@sibyte.com wrote:
>I looked over your patch, and found it sensible enough with the
>exception of the change:
>
>> 	/opcodes/ChangeLog
>> 	(_print_insn_mips): Get distinction between old ABI and new ABI right.
>
>and the related changes in the testsuite (mips4650.d, and mips64.d).
>
>
>> diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/opcodes/mips-dis.c src/opcodes/mips-dis.c
>> --- src-orig/opcodes/mips-dis.c	Wed May 23 21:09:17 2001
>> +++ src/opcodes/mips-dis.c	Sat Jun 16 16:27:19 2001
>> [ ... ]
>> @@ -524,9 +524,9 @@
>>    /* Use mips64_reg_names for new ABI.  */
>>    if (info->flavour == bfd_target_elf_flavour
>>        && info->symbols != NULL
>> -      && (((get_mips_isa(info) | INSN_ISA_MASK) & ISA_MIPS2) != 0)
>> +      && ((get_mips_isa(info) & INSN_ISA3) != 0)
>>        && ((elf_elfheader (bfd_asymbol_bfd(*(info->symbols)))->e_flags
>> -	   & EF_MIPS_ABI2) != 0))
>> +	   & (E_MIPS_ABI_O32 | E_MIPS_ABI_O64)) == 0))
>>      reg_names = mips64_reg_names;
>>    else
>>      reg_names = mips32_reg_names;
>
>The notion here is that binaries which ELF and are MIPS3 (or better),
>and which don't have O32 or O64 indicated are interpreted as using the
>'new' (n32/n64) register names?

Yes, thats the intention.

>I'll admit that I've not been following closely for the last month or
>so, but I don't understand why this is "Right."  (If there's another
>post on the topic that explains, please just point me to it.  8-)

For 64bit-capable MIPS, there are following ABI's supported by the
disasembler:

o32, o64, n32, n64, eabi32, eabi64.

Eabi is wrt a New ABI, so everything else than o{32,64} should
use new register names.

>It's certainly a change from existing behaviour,

Yes, it's a fix for that. The existing behaviour was introduced
by me, too. :-)

>and given that by
>default there are no ABI markings on binaries (that I can see;
>certainly e.g. the m4650 test just compiled with a clean binutils
>build says "[no abi set]"),

MIPS ELF surely has ABI markings in it's header. It hasn't
_processor_ specific flags by default, which are luckily not
needed to check here.

>this may break a bunch of peoples'
>expectations w.r.t. disassembly output...

Again, current behaviour is broken.


Thiemo

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[cgd]

ica2_ts@csv.ica.uni-stuttgart.de ("Thiemo Seufer") writes:
> >The notion here is that binaries which ELF and are MIPS3 (or better),
> >and which don't have O32 or O64 indicated are interpreted as using the
> >'new' (n32/n64) register names?
> 
> Yes, thats the intention.

Why is that The Right Thing?


> >I'll admit that I've not been following closely for the last month or
> >so, but I don't understand why this is "Right."  (If there's another
> >post on the topic that explains, please just point me to it.  8-)
> 
> For 64bit-capable MIPS, there are following ABI's supported by the
> disasembler:
> 
> o32, o64, n32, n64, eabi32, eabi64.
> 
> Eabi is wrt a New ABI, so everything else than o{32,64} should
> use new register names.

However, what is the ABI reported by existing binaries marked with no
ABI bits set whatsoever?


> >It's certainly a change from existing behaviour,
> 
> Yes, it's a fix for that. The existing behaviour was introduced
> by me, too. :-)

Uh, sort-of.  As far as I can tell, the current choice of register
names (which you're trying to change) for existing un-marked binaries
seems to predate you.

The part that i have issue with is e.g. the change you made to
mips64.d which does:

[...]
-0+001c <[^>]*> 48a84807        dmtc2   t0,t1,7
[...]
+0+001c <[^>]*> 48a84807        dmtc2   a4,\$9,7
[...]

The selection of t0 for that register name, for a binary unmarked with
ABI, is a change, and I don't understand why it's correct.


> >and given that by
> >default there are no ABI markings on binaries (that I can see;
> >certainly e.g. the m4650 test just compiled with a clean binutils
> >build says "[no abi set]"),
> 
> MIPS ELF surely has ABI markings in it's header. It hasn't
> _processor_ specific flags by default, which are luckily not
> needed to check here.

by default, there are no ABI markings on binaries (as far as i can
tell, with the current and existing tools).

There are fields for such markings, e.g. in flags:

/* Code in file uses new ABI (-n32 on Irix 6).  */
#define EF_MIPS_ABI2            0x00000020

/* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
#define EF_MIPS_ABI             0x0000F000
  
/* The original o32 abi. */
#define E_MIPS_ABI_O32          0x00001000 
  
/* O32 extended to work on 64 bit architectures */
#define E_MIPS_ABI_O64          0x00002000
  
/* EABI in 32 bit mode */
#define E_MIPS_ABI_EABI32       0x00003000
     
/* EABI in 64 bit mode */
#define E_MIPS_ABI_EABI64       0x00004000


However, at least in the current mips-elf and mips64-elf toolchains as
far as I can tell, _none of those bits is set by default_ and so
objdump says "[no abi set]".

That's what i meant above when i said that no ABI is set by default.


What your change does is change the disassembly of that case -- for no
reason that i've been able to discern.  Maybe i'm just missing it in
your explanations...

Anyway, it also looks like you're ignoring the ABI2 flag, aren't you?
Since it indicates n32, i believe that means the new reg names, no?


Where the code currently in binutils (with your changes) is:

   /* Use mips64_reg_names for new ABI.  */
   if (info->flavour == bfd_target_elf_flavour
       && info->symbols != NULL
       && (((get_mips_isa(info) | INSN_ISA_MASK) & ISA_MIPS2) != 0)
       && ((elf_elfheader (bfd_asymbol_bfd(*(info->symbols)))->e_flags
           & EF_MIPS_ABI2) != 0))
     reg_names = mips64_reg_names;
   else
     reg_names = mips32_reg_names;

I believe it's more correct to change that so that either:

* instead of EF_MIPS_ABI2, you use (EF_MIPS_ABI2 | <the other new ABI bits), or

* if an ABI bit is specified use what it specifies, else if 32-bit ELF
and no ABI bit is specified use old reg names, else (must be 64-bit
ELF and no ABI bit specified) use new reg names.  That only works if
64-bit ELF _always_ encodes o32/o64 binary ABIs properly, though.
(Specifically, if GCC tries to use o64 by default when compiling
64-bit ELF code, and that falls into an assembler that produces a
64-bit ELF binary, and that binary is _not_ properly marked as
o64... then you can't really use this option.)

i think either of those gives you the current state for unmarked
binaries.


cgd

	

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[Thiemo Seufer]

cgd@sibyte.com wrote:
[snip]
> The selection of t0 for that register name, for a binary unmarked with
> ABI, is a change, and I don't understand why it's correct.

Ah, now I understand Your concern. I wasn't aware of the fact that
there are unmarked binaries. I thought the use of ABI-flags was
mandatory in ELF.

[snip] 
> There are fields for such markings, e.g. in flags:
> 
> /* Code in file uses new ABI (-n32 on Irix 6).  */
> #define EF_MIPS_ABI2            0x00000020
[snip]
> What your change does is change the disassembly of that case -- for no
> reason that i've been able to discern.  Maybe i'm just missing it in
> your explanations...

In contrary, I had missed Your point.

> Anyway, it also looks like you're ignoring the ABI2 flag, aren't you?
> Since it indicates n32, i believe that means the new reg names, no?

Now that I had a closer look: It's never set in binutils, which is
clearly a bug. It's used in elf32-mips.c as a check for n32 only,
where I found this snippet, too.

  /* Compare ABI's.  The 64-bit ABI does not use EF_MIPS_ABI.  But, it
     does set EI_CLASS differently from any 32-bit ABI.  */
  if ((new_flags & EF_MIPS_ABI) != (old_flags & EF_MIPS_ABI)
      || (elf_elfheader (ibfd)->e_ident[EI_CLASS]
          != elf_elfheader (obfd)->e_ident[EI_CLASS]))
	   
So it can be only one part of the solution.

[snip]
> I believe it's more correct to change that so that either:
> 
> * instead of EF_MIPS_ABI2, you use (EF_MIPS_ABI2 | <the other new ABI bits), or
>
> * if an ABI bit is specified use what it specifies, else if 32-bit ELF
> and no ABI bit is specified use old reg names, else (must be 64-bit
> ELF and no ABI bit specified) use new reg names. That only works if
> 64-bit ELF _always_ encodes o32/o64 binary ABIs properly, though.

I also found this snippet in elf32-mips.c, AFAICS it's best to
follow the algorithm, with the exception of checking for the special
ABI cases first. Here, ABI_64_P (which is == ELFCLASS64) is checked
first, so o64 and eabi64 are never detected. One more bug...

/* Return printable name for ABI.  */

static INLINE char *
elf_mips_abi_name (abfd)
     bfd *abfd;
{
  flagword flags;

  if (ABI_N32_P (abfd))
     return "N32";
  else if (ABI_64_P (abfd))
     return "64";

  flags = elf_elfheader (abfd)->e_flags;
  switch (flags & EF_MIPS_ABI)
    {
    case 0:
      return "none";
    case E_MIPS_ABI_O32:
      return "O32";
    case E_MIPS_ABI_O64:
      return "O64";
    case E_MIPS_ABI_EABI32:
      return "EABI32";
    case E_MIPS_ABI_EABI64:
      return "EABI64";
    default:
      return "unknown abi";
    }
}


An accordingly changed version is appended.


Thiemo


2001-06-21  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>

	/gas/testsuite/ChangeLog
	* mips/lb.d: Reflect disassembler output fixes.
	* mips/mips32.d: Likewise.
	* mips/mips64.d: Likewise. Typo.
	* mips/sb.d: Likewise.
	* mips/trunc.d: Likewise.

	/opcodes/ChangeLog
	* mips-dis.c (print_insn_arg): Don't use software integer registers
	for coprocessor registers.
	(get_mips_isa): Removed.
	(_print_insn_mips): Get distinction between old ABI and new ABI right.


diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/lb.d src/gas/testsuite/gas/mips/lb.d
--- src-orig/gas/testsuite/gas/mips/lb.d	Tue May 15 16:33:52 2001
+++ src/gas/testsuite/gas/mips/lb.d	Tue Jun 19 02:11:13 2001
@@ -388,8 +388,8 @@
 0+0378 <[^>]*> lw	a0,0\(zero\)
 0+037c <[^>]*> lwl	a0,0\(zero\)
 0+0380 <[^>]*> lwr	a0,0\(zero\)
-0+0384 <[^>]*> lwc0	a0,0\(zero\)
+0+0384 <[^>]*> lwc0	\$4,0\(zero\)
 0+0388 <[^>]*> lwc1	\$f4,0\(zero\)
-0+038c <[^>]*> lwc2	a0,0\(zero\)
-0+0390 <[^>]*> lwc3	a0,0\(zero\)
+0+038c <[^>]*> lwc2	\$4,0\(zero\)
+0+0390 <[^>]*> lwc3	\$4,0\(zero\)
 	...
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips32.d src/gas/testsuite/gas/mips/mips32.d
--- src-orig/gas/testsuite/gas/mips/mips32.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips32.d	Tue Jun 19 02:11:13 2001
@@ -26,15 +26,15 @@
 0+0040 <[^>]*> 00000000 	nop
 0+0044 <[^>]*> 4903ffee 	bc2tl	0+0000 <text_label>
 0+0048 <[^>]*> 00000000 	nop
-0+004c <[^>]*> 48411000 	cfc2	at,v0
+0+004c <[^>]*> 48411000 	cfc2	at,\$2
 0+0050 <[^>]*> 4b234567 	c2	0x1234567
-0+0054 <[^>]*> 48c21800 	ctc2	v0,v1
-0+0058 <[^>]*> 48032000 	mfc2	v1,a0
-0+005c <[^>]*> 48042800 	mfc2	a0,a1
-0+0060 <[^>]*> 48053007 	mfc2	a1,a2,7
-0+0064 <[^>]*> 48863800 	mtc2	a2,a3
-0+0068 <[^>]*> 48874000 	mtc2	a3,t0
-0+006c <[^>]*> 48884807 	mtc2	t0,t1,7
+0+0054 <[^>]*> 48c21800 	ctc2	v0,\$3
+0+0058 <[^>]*> 48032000 	mfc2	v1,\$4
+0+005c <[^>]*> 48042800 	mfc2	a0,\$5
+0+0060 <[^>]*> 48053007 	mfc2	a1,\$6,7
+0+0064 <[^>]*> 48863800 	mtc2	a2,\$7
+0+0068 <[^>]*> 48874000 	mtc2	a3,\$8
+0+006c <[^>]*> 48884807 	mtc2	t0,\$9,7
 0+0070 <[^>]*> bc250000 	cache	0x5,0\(at\)
 0+0074 <[^>]*> bc457fff 	cache	0x5,32767\(v0\)
 0+0078 <[^>]*> bc658000 	cache	0x5,-32768\(v1\)
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips64.d src/gas/testsuite/gas/mips/mips64.d
--- src-orig/gas/testsuite/gas/mips/mips64.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips64.d	Thu Jun 21 07:15:48 2001
@@ -2,16 +2,16 @@
 #name: MIPS MIPS64 instructions
 #as: -mips64
 
-# Check MIPS32 instruction assembly
+# Check MIPS64 instruction assembly
 
 .*: +file format .*mips.*
 
 Disassembly of section .text:
 0+0000 <[^>]*> 70410825 	dclo	at,v0
 0+0004 <[^>]*> 70831824 	dclz	v1,a0
-0+0008 <[^>]*> 48232000 	dmfc2	v1,a0
-0+000c <[^>]*> 48242800 	dmfc2	a0,a1
-0+0010 <[^>]*> 48253007 	dmfc2	a1,a2,7
-0+0014 <[^>]*> 48a63800 	dmtc2	a2,a3
-0+0018 <[^>]*> 48a74000 	dmtc2	a3,t0
-0+001c <[^>]*> 48a84807 	dmtc2	t0,t1,7
+0+0008 <[^>]*> 48232000 	dmfc2	v1,\$4
+0+000c <[^>]*> 48242800 	dmfc2	a0,\$5
+0+0010 <[^>]*> 48253007 	dmfc2	a1,\$6,7
+0+0014 <[^>]*> 48a63800 	dmtc2	a2,\$7
+0+0018 <[^>]*> 48a74000 	dmtc2	a3,\$8
+0+001c <[^>]*> 48a84807 	dmtc2	t0,\$9,7
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/sb.d src/gas/testsuite/gas/mips/sb.d
--- src-orig/gas/testsuite/gas/mips/sb.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/sb.d	Tue Jun 19 02:11:13 2001
@@ -386,10 +386,10 @@
 0+0370 <[^>]*> sw	a1,4\(zero\)
 0+0374 <[^>]*> sh	a0,0\(zero\)
 0+0378 <[^>]*> sw	a0,0\(zero\)
-0+037c <[^>]*> swc0	a0,0\(zero\)
+0+037c <[^>]*> swc0	\$4,0\(zero\)
 0+0380 <[^>]*> swc1	\$f4,0\(zero\)
-0+0384 <[^>]*> swc2	a0,0\(zero\)
-0+0388 <[^>]*> swc3	a0,0\(zero\)
+0+0384 <[^>]*> swc2	\$4,0\(zero\)
+0+0388 <[^>]*> swc3	\$4,0\(zero\)
 0+038c <[^>]*> swc1	\$f4,0\(zero\)
 0+0390 <[^>]*> swl	a0,0\(zero\)
 0+0394 <[^>]*> swr	a0,0\(zero\)
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/trunc.d src/gas/testsuite/gas/mips/trunc.d
--- src-orig/gas/testsuite/gas/mips/trunc.d	Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/trunc.d	Tue Jun 19 02:11:13 2001
@@ -7,23 +7,23 @@
 .*: +file format .*mips.*
 
 Disassembly of section .text:
-0+0000 <[^>]*> cfc1	a0,ra
-0+0004 <[^>]*> cfc1	a0,ra
+0+0000 <[^>]*> cfc1	a0,\$31
+0+0004 <[^>]*> cfc1	a0,\$31
 0+0008 <[^>]*> nop
 0+000c <[^>]*> ori	at,a0,0x3
 0+0010 <[^>]*> xori	at,at,0x2
-0+0014 <[^>]*> ctc1	at,ra
+0+0014 <[^>]*> ctc1	at,\$31
 0+0018 <[^>]*> nop
 0+001c <[^>]*> cvt.w.d	\$f4,\$f6
-0+0020 <[^>]*> ctc1	a0,ra
+0+0020 <[^>]*> ctc1	a0,\$31
 0+0024 <[^>]*> nop
-0+0028 <[^>]*> cfc1	a0,ra
-0+002c <[^>]*> cfc1	a0,ra
+0+0028 <[^>]*> cfc1	a0,\$31
+0+002c <[^>]*> cfc1	a0,\$31
 0+0030 <[^>]*> nop
 0+0034 <[^>]*> ori	at,a0,0x3
 0+0038 <[^>]*> xori	at,at,0x2
-0+003c <[^>]*> ctc1	at,ra
+0+003c <[^>]*> ctc1	at,\$31
 0+0040 <[^>]*> nop
 0+0044 <[^>]*> cvt.w.s	\$f4,\$f6
-0+0048 <[^>]*> ctc1	a0,ra
+0+0048 <[^>]*> ctc1	a0,\$31
 0+004c <[^>]*> nop
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/opcodes/mips-dis.c src/opcodes/mips-dis.c
--- src-orig/opcodes/mips-dis.c	Wed May 23 21:09:17 2001
+++ src/opcodes/mips-dis.c	Thu Jun 21 07:09:49 2001
@@ -256,13 +256,13 @@
       break;
 
     case 'E':
-      (*info->fprintf_func) (info->stream, "%s",
-			     reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+      (*info->fprintf_func) (info->stream, "$%d",
+			     (l >> OP_SH_RT) & OP_MASK_RT);
       break;
 
     case 'G':
-      (*info->fprintf_func) (info->stream, "%s",
-			     reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+      (*info->fprintf_func) (info->stream, "$%d",
+			     (l >> OP_SH_RD) & OP_MASK_RD);
       break;
 
     case 'N':
@@ -394,19 +394,6 @@
       break;
     }
 }
-
-/* Figure out ISA from disassemble_info data */
-
-static int
-get_mips_isa (info)
-     struct disassemble_info *info;
-{
-  int isa;
-  int cpu;
-
-  mips_isa_type (info->mach, &isa, &cpu);
-  return isa;
-}
 \f
 /* Print the mips instruction at address MEMADDR in debugged memory,
    on using INFO.  Returns length of the instruction, in bytes, which is
@@ -522,14 +509,20 @@
 #endif
 
   /* Use mips64_reg_names for new ABI.  */
-  if (info->flavour == bfd_target_elf_flavour
-      && info->symbols != NULL
-      && (((get_mips_isa(info) | INSN_ISA_MASK) & ISA_MIPS2) != 0)
-      && ((elf_elfheader (bfd_asymbol_bfd(*(info->symbols)))->e_flags
-	   & EF_MIPS_ABI2) != 0))
-    reg_names = mips64_reg_names;
-  else
-    reg_names = mips32_reg_names;
+  reg_names = mips32_reg_names;
+
+  if (info->flavour == bfd_target_elf_flavour && info->symbols != NULL)
+    {
+      Elf_Internal_Ehdr *header;
+
+      header = (Elf_Internal_Ehdr *) bfd_asymbol_bfd(*(info->symbols));
+
+      if ((header->e_flags &
+	   (E_MIPS_ABI_EABI32 | E_MIPS_ABI_EABI64 | EF_MIPS_ABI2)) != 0
+	  || (header->e_ident[EI_CLASS] == ELFCLASS64
+	      && (header->e_flags & E_MIPS_ABI_O64) == 0))
+	reg_names = mips64_reg_names;
+    }
 
   status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
   if (status == 0)

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[Daniel Jacobowitz]

On Thu, Jun 21, 2001 at 07:45:56AM +0200, Thiemo Seufer wrote:
> cgd@sibyte.com wrote:
> [snip]
> > The selection of t0 for that register name, for a binary unmarked with
> > ABI, is a change, and I don't understand why it's correct.
> 
> Ah, now I understand Your concern. I wasn't aware of the fact that
> there are unmarked binaries. I thought the use of ABI-flags was
> mandatory in ELF.

Nope.  Not only does, for instance, Linux/MIPS not use them - it would
be ABI-noncompliant to use them, unless I misread the psABI.  Only
noreorder, pic, cpic, and the four arch bits are defined for e_flags in
o32.

-- 
Daniel Jacobowitz                           Carnegie Mellon University
MontaVista Software                         Debian GNU/Linux Developer

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[cgd]

"Thiemo Seufer" <ica2_ts@csv.ica.uni-stuttgart.de> writes:
> [snip]
> > The selection of t0 for that register name, for a binary unmarked with
> > ABI, is a change, and I don't understand why it's correct.
> 
> Ah, now I understand Your concern. I wasn't aware of the fact that
> there are unmarked binaries. I thought the use of ABI-flags was
> mandatory in ELF.

Ahh, no.  See also Daniel J.'s response.


There was a discussion on the gcc-patches list last August about MIPS
ABI selection and ELF flags, under the subject of "RFA: Recording MIPS
ABI selection in binaries" -- you might go have a look at parts of it.
Of particular interest is:

	http://gcc.gnu.org/ml/gcc-patches/2000-08/msg00418.html

which details the e_flags values that the SGI compilers apparently
use.

That, combined with the current flags values in the GNU tree should
give you a mostly-complete idea of what you're up against.


> 2001-06-21  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
> 
> 	/gas/testsuite/ChangeLog
> 	* mips/lb.d: Reflect disassembler output fixes.
> 	* mips/mips32.d: Likewise.
> 	* mips/mips64.d: Likewise. Typo.
> 	* mips/sb.d: Likewise.
> 	* mips/trunc.d: Likewise.
> 
> 	/opcodes/ChangeLog
> 	* mips-dis.c (print_insn_arg): Don't use software integer registers
> 	for coprocessor registers.
> 	(get_mips_isa): Removed.
> 	(_print_insn_mips): Get distinction between old ABI and new ABI right.

This looks reasonable to me.

(thanks for noticing the mips64.d typo... d'oh!  8-)



chris

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[Eric Christopher]

> This looks reasonable to me.
> 

Same here.

-eric

-- 
Pain is not the cleanser

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[cgd]

dmj+@andrew.cmu.edu ("Daniel Jacobowitz") writes:
> On Thu, Jun 21, 2001 at 07:45:56AM +0200, Thiemo Seufer wrote:
> > cgd@sibyte.com wrote:
> > [snip]
> > > The selection of t0 for that register name, for a binary unmarked with
> > > ABI, is a change, and I don't understand why it's correct.
> > 
> > Ah, now I understand Your concern. I wasn't aware of the fact that
> > there are unmarked binaries. I thought the use of ABI-flags was
> > mandatory in ELF.
> 
> Nope.  Not only does, for instance, Linux/MIPS not use them - it would
> be ABI-noncompliant to use them, unless I misread the psABI.  Only
> noreorder, pic, cpic, and the four arch bits are defined for e_flags in
> o32.

the psABI version that you're talking about is the one at:

	http://www.sco.com/developer/devspecs/mipsabi.pdf

(MIPS RISC Processor Supplement 3rd Edition)?


Not only does it only define those e_flags bits, but it doesn't define
what the EF_MIPS_ARCH bits actually mean, and indicates that only
those with EF_MIPS_ARCH bits set to all 0 are ABI-compliant!

It also donsn't seem to provide much friendliness to little-endian
MIPS.  8-)



Really, it'd be great if people got together and worked through an
update for the MIPS ELF spec, for modern EF_MIPS_ARCH values and
additional flags (and did so in a way that brought the GNU tools, SGI,
and who knows else) under one roof, in a backward compatible way.

It's not clear that it'd be Good to try to define an updated version
of the SysV standard ABI for MIPS -- or at least, I wouldn't care to
try, maybe SGI would and should -- but at least the flags could/should
be unified.

I'd be willing to help in that, but I don't really even know where to
start, other than by staring at the bits.  8-)



chris

Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[Daniel Jacobowitz]

On Thu, Jun 21, 2001 at 06:44:45PM -0700, cgd@sibyte.com wrote:
> dmj+@andrew.cmu.edu ("Daniel Jacobowitz") writes:
> > On Thu, Jun 21, 2001 at 07:45:56AM +0200, Thiemo Seufer wrote:
> > > cgd@sibyte.com wrote:
> > > [snip]
> > > > The selection of t0 for that register name, for a binary unmarked with
> > > > ABI, is a change, and I don't understand why it's correct.
> > > 
> > > Ah, now I understand Your concern. I wasn't aware of the fact that
> > > there are unmarked binaries. I thought the use of ABI-flags was
> > > mandatory in ELF.
> > 
> > Nope.  Not only does, for instance, Linux/MIPS not use them - it would
> > be ABI-noncompliant to use them, unless I misread the psABI.  Only
> > noreorder, pic, cpic, and the four arch bits are defined for e_flags in
> > o32.
> 
> the psABI version that you're talking about is the one at:
> 
> 	http://www.sco.com/developer/devspecs/mipsabi.pdf
> 
> (MIPS RISC Processor Supplement 3rd Edition)?
> 
> 
> Not only does it only define those e_flags bits, but it doesn't define
> what the EF_MIPS_ARCH bits actually mean, and indicates that only
> those with EF_MIPS_ARCH bits set to all 0 are ABI-compliant!
> 
> It also donsn't seem to provide much friendliness to little-endian
> MIPS.  8-)

Indeed.  The trick is updating it without causing incompatibilities
with existing systems - that notice the changed e_flags and gripe.

-- 
Daniel Jacobowitz                           Carnegie Mellon University
MontaVista Software                         Debian GNU/Linux Developer