From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id B05173856964 for ; Fri, 16 Sep 2022 09:58:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B05173856964 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-ej1-x62a.google.com with SMTP id a26so19535939ejc.4 for ; Fri, 16 Sep 2022 02:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date; bh=P5VOstE7iV4QpTL595DxVqjyZleelq0VPM4pVl4siAg=; b=jwjou3xvrl2rvs9ux9Cddoeb/GZnrXKjFxXRUfhN7QMD+fjXupDV2qEZJp4oNmGHTp AgYcvkJorYS0OFHmcdIFSRRhjeNtgwN6zjDF9cE8wsLuh9oK8bhUKwNqeUKuXA7FyrFC FRRCZxw13Nwy5UZU3kdWtxZT/vttATTioVovEEa3WyG9NBgAoi14XCTUxFj/Bknd/qj1 DP1uI9ASc7TnDsZxQ0oOhxJWkHl53nhWuvRUA5SbYalfE2SBowat2CBKblcpbyp5jTA9 wn7+20yUs74g4MBtDQjgprPm+a2aePhXmgrLuhHGKT40uq2O/fsAFSD1X1iwVidTAcEE aRHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date; bh=P5VOstE7iV4QpTL595DxVqjyZleelq0VPM4pVl4siAg=; b=iMdLP2XhuU4pVqNZeoagGMXkWw9lQmIlCGaNg3IJyJfe7yskOmBV+ur5adeceb3s3Y 6KIt569GjFljG0iZS1HGrkylHtNp+16Qt5yZOITROkw3A24dwu0x4LzQdJaTYTL+tg4l Drqg+tiqsB5WQfD+jyq3mNKwDsproaEnXfu6MK5apwCLanx8APWv94SYUVXCOzFulBUB BORvb6ckkrVFmwqXIlC1J2Sxr0dtuZN+tmBmLIcmKA5tP5/ATTPMe04e8meMLzvU1MD+ KkmwdnuSSbiKWzkjo1O3BbxNzOD1+kbxZJOLQP6Y7s+SuFo/2mHihYSXUHqm8Nu+1dbJ GkKw== X-Gm-Message-State: ACrzQf0gkW0s3S9F7EZebU8EF3QPm1LoPQN6PJLJLC8XUHSAFyP5/NX9 nYFh3SSMTqUF2iwt+J+yV2ITNQ== X-Google-Smtp-Source: AMsMyM7MX3/PYBpRKCoUcPr+1I/Z13d5tSDrpfqXi6opgVCzeamYQkgtJZCWyu/qofcetn2LIV4UDQ== X-Received: by 2002:a17:907:a48:b0:77c:51b0:5aeb with SMTP id be8-20020a1709070a4800b0077c51b05aebmr3121409ejc.61.1663322310371; Fri, 16 Sep 2022 02:58:30 -0700 (PDT) Received: from localhost (guests-out.ms.mff.cuni.cz. [195.113.20.231]) by smtp.gmail.com with ESMTPSA id se28-20020a170906ce5c00b00730b3bdd8d7sm10292670ejb.179.2022.09.16.02.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Sep 2022 02:58:29 -0700 (PDT) Date: Fri, 16 Sep 2022 02:58:29 -0700 (PDT) X-Google-Original-Date: Fri, 16 Sep 2022 02:58:23 PDT (-0700) Subject: Re: [PATCH 00/13] Add support for the T-Head vendor extensions In-Reply-To: CC: christoph.muellner@vrull.eu, binutils@sourceware.org, kito.cheng@sifive.com, Jim Wilson , philipp.tomsich@vrull.eu, cooper.qu@linux.alibaba.com, lifang_xia@linux.alibaba.com, yunhai@linux.alibaba.com, zhiwei_liu@linux.alibaba.com From: Palmer Dabbelt To: nelson@rivosinc.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 16 Sep 2022 02:36:32 PDT (-0700), nelson@rivosinc.com wrote: > Hi Christoph, > > > On Tue, Sep 6, 2022 at 8:22 PM Christoph Muellner > wrote: >> >> From: Christoph Müllner >> >> This series introduces support for the T-Head vendor extensions, >> which are implemented e.g. in the XuanTie C906 and XuanTie C910 >> processors: >> * XTheadBa >> * XTheadBb >> * XTheadBs >> * XTheadCmo >> * XTheadCondMov >> * XTheadFMemIdx >> * XTheadMac >> * XTheadMemIdx >> * XTheadMemPair >> * XTheadSync >> >> The xthead* extensions are documented here: >> https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf >> >> The "th." instruction prefix prevents future conflicts with standard >> extensions and has been documentented in a PR for the RISC-V toolchain >> conventions: >> https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 >> >> The goal of this patchset is to provide access to these instruction >> so that compilers/users can optimize SW accordingly. >> >> Note, that the T-Head vendor extensions do not contain all >> vendor-specific >> functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are >> included). >> Instead the extensions cover coherent functionality, that is exposed to >> S and U mode. >> >> To enable the extensions above, the following two methods are possible: >> * add the extension to the arch string (e.g. >> * -march=rv64gc_xtheadcmo_xtheadsync) >> * implicitly select the extensions via CPU selection (e.g. >> * -mcpu=thead-c910) >> >> The patchset attempts to minimize code changes in generic/infrastructure >> code. All patches in this series come with tests to avoid future regressions. >> >> Christoph Müllner (13): >> RISC-V: Add generic support for vendor extensions >> RISC-V: Add T-Head CMO vendor extension >> RISC-V: Add T-Head SYNC vendor extension >> RISC-V: Add support for arbitrary immediate encoding formats >> RISC-V: Add T-Head Bitmanip vendor extension >> RISC-V: Add T-Head CondMov vendor extension >> RISC-V: Add T-Head MAC vendor extension >> RISC-V: Add T-Head FMemIdx vendor extension >> RISC-V: Add T-Head MemIdx vendor extension >> RISC-V: Add support for literal instruction arguments >> RISC-V: Add T-Head MemPair vendor extension > > There are three minor issues, > > 1. Probably need to add new extension support in > riscv_multi_subset_supports_ext, although it is just used for > reporting better error messages. > 2. The operand L seems only to be used for t-head for now, so it > should be still a vendor operand, named with the X prefix probably > better. > 3. I remember Lifang mentioned before that we should add these vendor > stuff based on the vendor infra in the integration branch, and that's > what I asked him to rebase his patches to there before, since the > previous policy cannot accept vendor stuff on master branch. But now > I think most of us agree to accept t-head extensions on mainline > directly, so I figured these things cannot be blocked by the vendor > infra and cannot be committed. That doesn't mean we don't need the > vendor infra, that means we can support the vendor infra later if me > or someone have time to move them back to mainline. > > Therefore, these patches look good to me for now, thank you very much > for spending so much time to implement these. But personally, I think > we should get the approval from the T-Head guys at least. Btw, If > these implementations are referred to and based on the integration > branch, then I think it would be better to keep at least the > co-authors there in the commit message here; if these patches are > re-write without referring to the implementation from the integration > branch, then I need to apologize to them, because I asked them to > rewrite their patches over there, and cannot be committed to mainline > at that time... > >> riscv: gas: Add command line option '-mcpu=' to specify the CPU >> riscv: Add T-Head entries for the -mcpu= flag > > Not sure if it is necessary to add -mcpu in assembler, since the > compiler should recognize -mcpu, and will expand it to the correct > extensions to assembler. If there are no objections for a period of > time, then please go ahead and commit these. I'd also learn towards keeping -mcpu out of the assembler, it's just going to result in subtly different behavior between GCC and GAS which will cause subtle headaches in the future. All -mcpu does is set -march and -mtune, so if we just continue keeping it in GCC then we have a single source of truth. GCC will already need to understand -march for everything that GAS needs to know anyway, so it's not like it's adding complexity. Is there something broken in GCC where -mcpu isn't setting the right -march for GAS and thus we're not getting the right extensions enabled? If that's the case I'd argue we're better off just fixing the bug over there. > > Thank you very much > Nelson > >> bfd/elfxx-riscv.c | 39 ++- >> gas/config/tc-riscv.c | 127 +++++++ >> gas/doc/c-riscv.texi | 70 ++++ >> gas/testsuite/gas/riscv/mcpu-fail-unknown.d | 3 + >> gas/testsuite/gas/riscv/mcpu-fail-unknown.l | 2 + >> gas/testsuite/gas/riscv/mcpu-ok-c906.d | 6 + >> gas/testsuite/gas/riscv/mcpu-ok-c910.d | 6 + >> gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 + >> gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 + >> gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 + >> gas/testsuite/gas/riscv/x-thead-ba.d | 13 + >> gas/testsuite/gas/riscv/x-thead-ba.s | 6 + >> gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 + >> gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 + >> gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 + >> gas/testsuite/gas/riscv/x-thead-bb.d | 30 ++ >> gas/testsuite/gas/riscv/x-thead-bb.s | 22 ++ >> gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 + >> gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 + >> gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 + >> gas/testsuite/gas/riscv/x-thead-bs.d | 14 + >> gas/testsuite/gas/riscv/x-thead-bs.s | 6 + >> gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 + >> gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++ >> gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++ >> gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++ >> gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++ >> gas/testsuite/gas/riscv/x-thead-condmov.d | 11 + >> gas/testsuite/gas/riscv/x-thead-condmov.s | 3 + >> .../gas/riscv/x-thead-fmemidx-fail.d | 3 + >> .../gas/riscv/x-thead-fmemidx-fail.l | 18 + >> .../gas/riscv/x-thead-fmemidx-fail.s | 17 + >> gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++ >> gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 + >> gas/testsuite/gas/riscv/x-thead-mac.d | 15 + >> gas/testsuite/gas/riscv/x-thead-mac.s | 7 + >> gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 + >> gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 + >> gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 + >> gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++ >> gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++ >> .../gas/riscv/x-thead-mempair-fail.d | 3 + >> .../gas/riscv/x-thead-mempair-fail.l | 30 ++ >> .../gas/riscv/x-thead-mempair-fail.s | 30 ++ >> gas/testsuite/gas/riscv/x-thead-mempair.d | 14 + >> gas/testsuite/gas/riscv/x-thead-mempair.s | 6 + >> gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 + >> gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 + >> gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 + >> gas/testsuite/gas/riscv/x-thead-sync.d | 14 + >> gas/testsuite/gas/riscv/x-thead-sync.s | 6 + >> include/opcode/riscv-opc.h | 326 ++++++++++++++++++ >> include/opcode/riscv.h | 27 ++ >> opcodes/riscv-dis.c | 44 +++ >> opcodes/riscv-opc.c | 155 +++++++++ >> 55 files changed, 1394 insertions(+), 2 deletions(-) >> create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.d >> create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.l >> create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c906.d >> create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c910.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s >> >> -- >> 2.37.2 >>