From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by sourceware.org (Postfix) with ESMTPS id 6F8943857B98 for ; Tue, 29 Nov 2022 02:38:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6F8943857B98 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pf1-x42e.google.com with SMTP id o1so7825952pfp.12 for ; Mon, 28 Nov 2022 18:38:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=message-id:to:from:cc:in-reply-to:subject:date:from:to:cc:subject :date:message-id:reply-to; bh=tL+dRj4Ny73UeSmACNj264pewVZRW9tgf06KBbOD9c4=; b=KT/iBmSsnOAk+6gh6JMNb4RCDLEDF/Mmhi7f2DOORaK1X54qlTpqqZOUBhP9IWWCkK 9RJnQDUemChA7LWknyRhmuDSLmcIXtU6qrZ4jkD/51Y6xosvwdTPPF7Us0LCSnbo+lwZ XSpI1xUU89o5ivPMX6SWvTHT8X8zT0vQ2MPCup5pv9INHFFSeMDEze5mHWDgF0XSxP5R ElCPQdAzSuWEWVBNd4fryzk8sjqunrQ06KudVqVIP1aJw7yOVrynlOhH8+ZbD0YN5Kj0 oqNOSKE+ptxy31FlRFiMxFVGOWOOYidvfn8Pd4F1OD/nJD56hAzN9GKauhwSxYbo1Eyy cJ+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=message-id:to:from:cc:in-reply-to:subject:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=tL+dRj4Ny73UeSmACNj264pewVZRW9tgf06KBbOD9c4=; b=3krrQf7ib+FBiZZZ7kJlLgqRFh8OsR6jF0OVqBv4cUnDKCq9cfB5yCsy3m/t9SwAVx CvNaGMMkLF/7umA26yHv1y7GjWRL6moL6H5O7VGYXwUOOm9HkeBAXDKptZMRj0jsGbeg y4B0l+nc7iqQnl5J5cX3+C41SZwKpXcFH2jeJ7ClG5CfPhkjw7XmxSZieZcNSlB/2s64 2iIxs0f7I1wvaRLRA2/efCmTtu9Deh++T0tArNlUV/u1eo760XdBNQ2CBRxIsMo+yqiP 9Kgnfl6IXL+HZaozpHJHypPFzkbqmA1msvTi31vBjoWPL3lr7ET6kg0Tham19QeKErXX CFQw== X-Gm-Message-State: ANoB5pnEgHtziUny87VpwKPNBr7Yha9h5eO+TpfamAvjb88/E5R+OTbo E8Vcy9IqQlNJLMt7Vsy+RxR8HjraieKy9A== X-Google-Smtp-Source: AA0mqf7Gkr0Kl25ljyTj/4ogXDdWt/2XH1mctjHLKMDMKuL+wClw70NuKZvD0KqEcDeS8TTmjYrevQ== X-Received: by 2002:a63:e646:0:b0:470:15cd:d428 with SMTP id p6-20020a63e646000000b0047015cdd428mr49636042pgj.213.1669689537191; Mon, 28 Nov 2022 18:38:57 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id sj16-20020a17090b2d9000b002192f87474fsm160294pjb.37.2022.11.28.18.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 18:38:56 -0800 (PST) Date: Mon, 28 Nov 2022 18:38:56 -0800 (PST) X-Google-Original-Date: Mon, 28 Nov 2022 18:32:45 PST (-0800) Subject: Re: [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs In-Reply-To: <03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com> CC: research_trasio@irq.a4lg.com, binutils@sourceware.org From: Palmer Dabbelt To: binutils@sourceware.org Message-ID: X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 28 Nov 2022 17:21:51 PST (-0800), binutils@sourceware.org wrote: > From: Tsukasa OI > > [DO NOT MERGE] > Until 'Smrnmi' extension is frozen/ratified and final version number is > determined, this patch should not be merged upstream. This commit uses > unratified version 0.4 as in the documentation (instead of possible 1.0 > after ratification). > > This commit adds "mnret" instruction and RNMI-related CSRs from the > Resumable Non-Maskable Interrupts ('Smrnmi') extension. > > This is based on: > , > latest 'Smrnmi' change on the master branch of the RISC-V ISA Manual > as of this writing. > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_implicit_subsets): Make 'Smrnmi' to imply > 'Zicsr' extension. (riscv_multi_subset_supports): Add new > instruction class handling. > (riscv_multi_subset_supports_ext): Likewise. > > gas/ChangeLog: > > * config/tc-riscv.c (enum riscv_csr_class): Add new CSR class. > (riscv_csr_address): Add new CSR class handling. > * testsuite/gas/riscv/csr.s: Add new CSR test. > * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. > * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. > * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. > * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. > * testsuite/gas/riscv/csr-version-1p10.d: Likewise. > * testsuite/gas/riscv/csr-version-1p10.l: Likewise. > * testsuite/gas/riscv/csr-version-1p11.d: Likewise. > * testsuite/gas/riscv/csr-version-1p11.l: Likewise. > * testsuite/gas/riscv/csr-version-1p12.d: Likewise. > * testsuite/gas/riscv/csr-version-1p12.l: Likewise. > * testsuite/gas/riscv/smrnmi.s: New test for mnret instruction. > * testsuite/gas/riscv/smrnmi.d: Likewise. > * testsuite/gas/riscv/smrnmi-noarch.d: New test for architecture > failure. > * testsuite/gas/riscv/smrnmi-noarch.l: Likewise. > > include/ChangeLog: > > * opcode/riscv-opc.h (MATCH_MNRET, MASK_MNRET, CSR_MNSCRATCH, > CSR_MNEPC, CSR_MNCAUSE, CSR_MNSTATUS): New. > * opcode/riscv.h (enum riscv_insn_class): Add new instruction > class. > > opcodes/ChangeLog: > > * riscv-opc.c (riscv_opcodes): Add 'mnret' instruction. > --- > bfd/elfxx-riscv.c | 6 ++++++ > gas/config/tc-riscv.c | 4 ++++ > gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++ > gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++ > gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++ > gas/testsuite/gas/riscv/csr-version-1p10.l | 8 ++++++++ > gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++ > gas/testsuite/gas/riscv/csr-version-1p11.l | 8 ++++++++ > gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++ > gas/testsuite/gas/riscv/csr-version-1p12.l | 8 ++++++++ > gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++ > gas/testsuite/gas/riscv/csr-version-1p9p1.l | 8 ++++++++ > gas/testsuite/gas/riscv/csr.s | 6 ++++++ > gas/testsuite/gas/riscv/smrnmi-noarch.d | 3 +++ > gas/testsuite/gas/riscv/smrnmi-noarch.l | 2 ++ > gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++ > gas/testsuite/gas/riscv/smrnmi.s | 2 ++ > include/opcode/riscv-opc.h | 15 +++++++++++++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 3 +++ > 20 files changed, 125 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.d > create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.l > create mode 100644 gas/testsuite/gas/riscv/smrnmi.d > create mode 100644 gas/testsuite/gas/riscv/smrnmi.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 0bcf2fdcfa34..d4f580733ddd 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1104,6 +1104,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > {"smaia", "ssaia", check_implicit_always}, > {"smstateen", "ssstateen", check_implicit_always}, > {"smepmp", "zicsr", check_implicit_always}, > + {"smrnmi", "zicsr", check_implicit_always}, > {"ssaia", "zicsr", check_implicit_always}, > {"sscofpmf", "zicsr", check_implicit_always}, > {"ssstateen", "zicsr", check_implicit_always}, > @@ -1225,6 +1226,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = > { > {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"smrnmi", ISA_SPEC_CLASS_DRAFT, 0, 4, 0 }, > {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -2415,6 +2417,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, > || riscv_subset_supports (rps, "zve64d") > || riscv_subset_supports (rps, "zve64f") > || riscv_subset_supports (rps, "zve32f")); > + case INSN_CLASS_SMRNMI: > + return riscv_subset_supports (rps, "smrnmi"); > case INSN_CLASS_SVINVAL: > return riscv_subset_supports (rps, "svinval"); > case INSN_CLASS_H: > @@ -2573,6 +2577,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, > return _("v' or `zve64x' or `zve32x"); > case INSN_CLASS_ZVEF: > return _("v' or `zve64d' or `zve64f' or `zve32f"); > + case INSN_CLASS_SMRNMI: > + return "smrnmi"; > case INSN_CLASS_SVINVAL: > return "svinval"; > case INSN_CLASS_H: > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 0682eb355241..85aa4d1d00d4 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -74,6 +74,7 @@ enum riscv_csr_class > CSR_CLASS_H_32, /* hypervisor, rv32 only */ > CSR_CLASS_SMAIA, /* Smaia */ > CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */ > + CSR_CLASS_SMRNMI, /* Smrnmi only */ > CSR_CLASS_SMSTATEEN, /* Smstateen only */ > CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ > CSR_CLASS_SSAIA, /* Ssaia */ > @@ -1049,6 +1050,9 @@ riscv_csr_address (const char *csr_name, > case CSR_CLASS_SMAIA: > extension = "smaia"; > break; > + case CSR_CLASS_SMRNMI: > + extension = "smrnmi"; > + break; > case CSR_CLASS_SMSTATEEN: > case CSR_CLASS_SMSTATEEN_32: > is_rv32_only = (csr_class == CSR_CLASS_SMSTATEEN_32); > diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d > index fd830666ab89..a87df625da9d 100644 > --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d > +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d > @@ -324,6 +324,10 @@ Contents of the .* section: > DW_CFA_offset_extended_sf: r4888 \(mvienh\) at cfa\+3168 > DW_CFA_offset_extended_sf: r4889 \(mviph\) at cfa\+3172 > DW_CFA_offset_extended_sf: r4948 \(miph\) at cfa\+3408 > + DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424 > + DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428 > + DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432 > + DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440 > DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120 > DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124 > DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128 > diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s > index b8b0f7902297..3ea3853a2cc5 100644 > --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s > +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s > @@ -321,6 +321,11 @@ _start: > .cfi_offset mvienh, 3168 > .cfi_offset mviph, 3172 > .cfi_offset miph, 3408 > + # Smrnmi extension > + .cfi_offset mnscratch, 7424 > + .cfi_offset mnepc, 7428 > + .cfi_offset mncause, 7432 > + .cfi_offset mnstatus, 7440 > # Smstateen extension > .cfi_offset mstateen0, 3120 > .cfi_offset mstateen1, 3124 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d > index ee41e1025cce..9c2bf4bc9628 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p10.d > +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d > @@ -623,6 +623,14 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 > [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph > [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 > +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch > +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 > +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc > +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 > +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause > +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 > +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus > +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 > [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 > [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 > [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l > index e677b78b8bb8..b00515d2cf13 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p10.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l > @@ -444,6 +444,14 @@ > .*Warning: invalid CSR `miph', needs `smaia' extension > .*Warning: invalid CSR `miph', needs rv32i extension > .*Warning: invalid CSR `miph', needs `smaia' extension > +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension > +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension > +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension > +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension > +.*Warning: invalid CSR `mncause', needs `smrnmi' extension > +.*Warning: invalid CSR `mncause', needs `smrnmi' extension > +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension > +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension > .*Warning: invalid CSR `mstateen0', needs `smstateen' extension > .*Warning: invalid CSR `mstateen0', needs `smstateen' extension > .*Warning: invalid CSR `mstateen1', needs `smstateen' extension > diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d > index a83b1bf68f98..9783cb795e2c 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p11.d > +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d > @@ -623,6 +623,14 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 > [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph > [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 > +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch > +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 > +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc > +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 > +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause > +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 > +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus > +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 > [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 > [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 > [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l > index 81ca86ca7bcc..da5167dab7e3 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p11.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l > @@ -442,6 +442,14 @@ > .*Warning: invalid CSR `miph', needs `smaia' extension > .*Warning: invalid CSR `miph', needs rv32i extension > .*Warning: invalid CSR `miph', needs `smaia' extension > +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension > +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension > +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension > +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension > +.*Warning: invalid CSR `mncause', needs `smrnmi' extension > +.*Warning: invalid CSR `mncause', needs `smrnmi' extension > +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension > +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension > .*Warning: invalid CSR `mstateen0', needs `smstateen' extension > .*Warning: invalid CSR `mstateen0', needs `smstateen' extension > .*Warning: invalid CSR `mstateen1', needs `smstateen' extension > diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d > index 612aac280768..e39473062d5a 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p12.d > +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d > @@ -623,6 +623,14 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 > [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph > [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 > +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch > +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 > +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc > +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 > +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause > +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 > +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus > +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 > [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 > [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 > [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l > index 1c0bb4ef2d8f..011e5d578309 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p12.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l > @@ -304,6 +304,14 @@ > .*Warning: invalid CSR `miph', needs `smaia' extension > .*Warning: invalid CSR `miph', needs rv32i extension > .*Warning: invalid CSR `miph', needs `smaia' extension > +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension > +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension > +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension > +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension > +.*Warning: invalid CSR `mncause', needs `smrnmi' extension > +.*Warning: invalid CSR `mncause', needs `smrnmi' extension > +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension > +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension > .*Warning: invalid CSR `mstateen0', needs `smstateen' extension > .*Warning: invalid CSR `mstateen0', needs `smstateen' extension > .*Warning: invalid CSR `mstateen1', needs `smstateen' extension > diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d > index 0fe849c269c2..819292888aaa 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d > +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d > @@ -623,6 +623,14 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 > [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph > [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 > +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch > +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 > +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc > +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 > +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause > +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 > +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus > +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 > [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 > [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 > [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > index c65d0b48e414..daf7e94bbace 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > @@ -494,6 +494,14 @@ > .*Warning: invalid CSR `miph', needs `smaia' extension > .*Warning: invalid CSR `miph', needs rv32i extension > .*Warning: invalid CSR `miph', needs `smaia' extension > +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension > +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension > +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension > +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension > +.*Warning: invalid CSR `mncause', needs `smrnmi' extension > +.*Warning: invalid CSR `mncause', needs `smrnmi' extension > +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension > +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension > .*Warning: invalid CSR `mstateen0', needs `smstateen' extension > .*Warning: invalid CSR `mstateen0', needs `smstateen' extension > .*Warning: invalid CSR `mstateen1', needs `smstateen' extension > diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s > index c7406ce34c2e..3508c42f623c 100644 > --- a/gas/testsuite/gas/riscv/csr.s > +++ b/gas/testsuite/gas/riscv/csr.s > @@ -350,6 +350,12 @@ > csr mviph > csr miph > > + # Smrnmi extension > + csr mnscratch > + csr mnepc > + csr mncause > + csr mnstatus > + > # Smstateen/Ssstateen extensions > csr mstateen0 > csr mstateen1 > diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.d b/gas/testsuite/gas/riscv/smrnmi-noarch.d > new file mode 100644 > index 000000000000..d28da9736300 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/smrnmi-noarch.d > @@ -0,0 +1,3 @@ > +#as: -march=rv32i > +#source: smrnmi.s > +#error_output: smrnmi-noarch.l > diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.l b/gas/testsuite/gas/riscv/smrnmi-noarch.l > new file mode 100644 > index 000000000000..1ad5141c1245 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/smrnmi-noarch.l > @@ -0,0 +1,2 @@ > +.*: Assembler messages: > +.*: Error: unrecognized opcode `mnret', extension `smrnmi' required > diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d > new file mode 100644 > index 000000000000..2b628e91a103 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/smrnmi.d > @@ -0,0 +1,10 @@ > +#as: -march=rv32i_smrnmi > +#source: smrnmi.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+[0-9a-f]+:[ ]+70200073[ ]+mnret > diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s > new file mode 100644 > index 000000000000..f2008bd8704e > --- /dev/null > +++ b/gas/testsuite/gas/riscv/smrnmi.s > @@ -0,0 +1,2 @@ > +target: > + mnret > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index 06e3df0f5a63..d80c7fb5a876 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2055,6 +2055,9 @@ > #define MASK_VDOTUVV 0xfc00707f > #define MATCH_VFDOTVV 0xe4001057 > #define MASK_VFDOTVV 0xfc00707f > +/* Smrnmi instruction. */ > +#define MATCH_MNRET 0x70200073 > +#define MASK_MNRET 0xffffffff > /* Svinval instruction. */ > #define MATCH_SINVAL_VMA 0x16000073 > #define MASK_SINVAL_VMA 0xfe007fff > @@ -2673,6 +2676,11 @@ > #define CSR_MVIENH 0x318 > #define CSR_MVIPH 0x319 > #define CSR_MIPH 0x354 > +/* Smrnmi extension CSR addresses. */ > +#define CSR_MNSCRATCH 0x740 > +#define CSR_MNEPC 0x741 > +#define CSR_MNCAUSE 0x742 > +#define CSR_MNSTATUS 0x744 > /* Smstateen extension */ > #define CSR_MSTATEEN0 0x30c > #define CSR_MSTATEEN1 0x30d > @@ -3106,6 +3114,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) > DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) > DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) > DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) > +/* Smrnmi instructions. */ > +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) > /* Zicbop instructions. */ > DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R); > DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W); > @@ -3550,6 +3560,11 @@ DECLARE_CSR(mieh, CSR_MIEH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_ > DECLARE_CSR(mvienh, CSR_MVIENH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > DECLARE_CSR(mviph, CSR_MVIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > DECLARE_CSR(miph, CSR_MIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > +/* Smrnmi extension CSRs. */ > +DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > +DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > +DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > +DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > /* Smstateen/Ssstateen extensions. */ > DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index c3cbde600cb0..d979ef4ac6db 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -405,6 +405,7 @@ enum riscv_insn_class > INSN_CLASS_ZKND_OR_ZKNE, > INSN_CLASS_V, > INSN_CLASS_ZVEF, > + INSN_CLASS_SMRNMI, > INSN_CLASS_SVINVAL, > INSN_CLASS_ZICBOM, > INSN_CLASS_ZICBOP, > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 0e691544f9bc..2194289469cd 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1847,6 +1847,9 @@ const struct riscv_opcode riscv_opcodes[] = > {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, > {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, > > +/* Smrnmi instructions. */ > +{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 }, > + > /* Svinval instructions. */ > {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, > {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, Reviewed-by: Palmer Dabbelt # pending freeze