[PATCH] RISC-V: Change CALL macro to use ra as the temporary address register

[PATCH] RISC-V: Change CALL macro to use ra as the temporary address register

[Palmer Dabbelt]

From: Michael Clark <michaeljclark@mac.com>

e.g.

    1:  auipc ra, %pcrel_hi(symbol)
        jalr  ra, %pcrel_lo(1b)(ra)

The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.

2017-05-01  Michael Clark  <michaeljclark@mac.com>

	* riscv-opc.c (riscv_opcodes> <call>: Use RA not T1 as a temporary
	register.
---
 opcodes/ChangeLog   | 5 +++++
 opcodes/riscv-opc.c | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b9d67d2..6610242 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-01  Michael Clark  <michaeljclark@mac.com>
+
+	* riscv-opc.c (riscv_opcodes> <call>: Use RA not T1 as a temporary
+	register.
+
 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c629d2f..0188a65 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -147,7 +147,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"jal",       "32C", "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
 {"jal",       "I",   "a",  MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
 {"call",      "I",   "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
-{"call",      "I",   "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
+{"call",      "I",   "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
 {"tail",      "I",   "c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
 {"jump",      "I",   "c,s", 0, (int) M_CALL,  match_never, INSN_MACRO },
 {"nop",       "C",   "",  MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },
-- 
2.10.2

Re: [PATCH] RISC-V: Change CALL macro to use ra as the temporary address register

[Palmer Dabbelt]

I'll fix the (riscv_opcodes> typo before committing.

On Mon, 01 May 2017 13:33:09 PDT (-0700), Palmer Dabbelt wrote:
> From: Michael Clark <michaeljclark@mac.com>
>
> e.g.
>
>     1:  auipc ra, %pcrel_hi(symbol)
>         jalr  ra, %pcrel_lo(1b)(ra)
>
> The use of ra instead of t1 for address construction provides an
> opportunity for a microarchitecture to elide the write of the
> destination address, and instead read the target address as an
> immediate spread across the fused auipc+jalr pair. The link
> register ra in the jalr overwrites the target address temporary.
>
> 2017-05-01  Michael Clark  <michaeljclark@mac.com>
>
> 	* riscv-opc.c (riscv_opcodes> <call>: Use RA not T1 as a temporary
> 	register.
> ---
>  opcodes/ChangeLog   | 5 +++++
>  opcodes/riscv-opc.c | 2 +-
>  2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
> index b9d67d2..6610242 100644
> --- a/opcodes/ChangeLog
> +++ b/opcodes/ChangeLog
> @@ -1,3 +1,8 @@
> +2017-05-01  Michael Clark  <michaeljclark@mac.com>
> +
> +	* riscv-opc.c (riscv_opcodes> <call>: Use RA not T1 as a temporary
> +	register.
> +
>  2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
>
>  	* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index c629d2f..0188a65 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -147,7 +147,7 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"jal",       "32C", "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
>  {"jal",       "I",   "a",  MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
>  {"call",      "I",   "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
> -{"call",      "I",   "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
> +{"call",      "I",   "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
>  {"tail",      "I",   "c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
>  {"jump",      "I",   "c,s", 0, (int) M_CALL,  match_never, INSN_MACRO },
>  {"nop",       "C",   "",  MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },

Re: [PATCH] RISC-V: Change CALL macro to use ra as the temporary address register

[Nick Clifton]

Hi Palmer,

> I'll fix the (riscv_opcodes> typo before committing.

Good-o

>> 2017-05-01  Michael Clark  <michaeljclark@mac.com>
>>
>> 	* riscv-opc.c (riscv_opcodes> <call>: Use RA not T1 as a temporary
>> 	register.

Approved - please apply.

Cheers
  Nick

Re: [PATCH] RISC-V: Change CALL macro to use ra as the temporary address register

[Palmer Dabbelt]

On Tue, 02 May 2017 08:36:28 PDT (-0700), Nick Clifton wrote:
> Hi Palmer,
>
>> I'll fix the (riscv_opcodes> typo before committing.
>
> Good-o
>
>>> 2017-05-01  Michael Clark  <michaeljclark@mac.com>
>>>
>>> 	* riscv-opc.c (riscv_opcodes> <call>: Use RA not T1 as a temporary
>>> 	register.
>
> Approved - please apply.

Thanks.  Committed.