From: Palmer Dabbelt <palmer@dabbelt.com>
To: Tristan Gingold <gingold@adacore.com>
Cc: binutils@sourceware.org
Subject: Re: binutils-2_28-branch: Assorted RISC-V Fixes
Date: Thu, 30 Mar 2017 20:01:00 -0000 [thread overview]
Message-ID: <mhng-61904fbb-4021-4eae-a83c-ee1ea6106b20@palmer-si-x1c4> (raw)
In-Reply-To: <063f9365-f6ce-0ecf-4c92-6119c2d26985@adacore.com>
On Thu, 23 Mar 2017 03:53:51 PDT (-0700), Tristan Gingold wrote:
> On 23/03/2017 00:04, Palmer Dabbelt wrote:
>> Since 2.28 was released a few fixes have landed on master that I think are sane
>> for the 2.28 branch. The patches have better descriptions, but they are:
>>
>> * Fixes to allow assembly of a half dozen or so compressed instructions.
>> * Debug info relocation fixes.
>> * Help text/documentation.
>>
>> Are these OK for the 2.28 branch?
>
> Yes, that's fine.
Thanks, committed.
prev parent reply other threads:[~2017-03-30 20:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-22 23:04 Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 3/7] RISC-V: Fix DW_CFA_advance_loc relocation Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 1/7] RISC-V: Fix [dis]assembly of srai/srli Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 4/7] RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 2/7] RISC-V: Fix the offset of CFA relocation Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 7/7] Sanitize RISC-V GAS help text, documentation Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 5/7] RISC-V: Fix assembler for c.addi, rd can be x0 Palmer Dabbelt
2017-03-22 23:04 ` [PATCH 6/7] RISC-V: Fix assembler for c.li, c.andi and c.addiw Palmer Dabbelt
2017-03-23 10:53 ` binutils-2_28-branch: Assorted RISC-V Fixes gingold
2017-03-30 20:01 ` Palmer Dabbelt [this message]
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