From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by sourceware.org (Postfix) with ESMTPS id 3CEA53858D1E for ; Tue, 29 Nov 2022 20:57:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3CEA53858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pj1-x102c.google.com with SMTP id k5so13814546pjo.5 for ; Tue, 29 Nov 2022 12:57:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=TRtcrHHNnNN0w78uJ+qmyIuHUrQjfcC88OV8Ch/cjVQ=; b=Z130HJcyc2G+oDYMw0hxnGT72HdqVTbQtMLkYry6eo8nVr/vczzvwXIva26poWb7c0 qW1ktZvgWdt2IfyCQH5xz9ZGWw95+WwbXf24cokBtfbWuVqiSR7rft+OExS4eCayT1sT bnQ6pSRBWQqcOZxlFfFoikKAHXsg2me0UVd2CKZe0kcP2wxjDL3EaO2CpOSvrwrmvAXt HgGvgdvfWhjgjdoIcMwYhTwaciahUEVg72X1VEN0nHCERfQadcgqbKo8yNP7Q9YDtHci NHX1SOh91LaXQQYTICBARNDzIftdHz88b6dPp08qVFdaP9pCYKvlemrd5fLALPer+9Y/ nEUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=TRtcrHHNnNN0w78uJ+qmyIuHUrQjfcC88OV8Ch/cjVQ=; b=2u3Hl/8e32iJRlndvuRn4411qqSXrq1ROxHmcxqxYMlKeHtbyHhdq4letQ3Xu//rzr 7pFy4cg7476bHTEbqW9uhmclYjpXQfkUwGN4EXoLJ/Xw09o5hLQ0lURPbAzGehXJUOTC QfjMxDsaGBaYrAmI7Qp3bfFpouNBScDcqrWIfbaitZHltuy4/JRjXxJ49WDdBG3MEtfZ GnC/SbadD+URcatTwT4kI+CE82r4TX4np1AZ0zK1lZxi/Fq4Jroz9bwt6Adxj8iCzWEY 7hjAVw8EABBQH18g+d3fZ2sfZacXpQv8OK433Fel7EPGspeYyBJPdsmN2O5YEqJ1VAF/ Y4xg== X-Gm-Message-State: ANoB5pn/zc/uzOJWKAxSjA8Pb7VI4UavFu7b6+yVDgiDZPmwupjD6eRq hXRM+2bOCq1FJU3tAGfs6MHUKnUTYRc/GA== X-Google-Smtp-Source: AA0mqf7Lurhfu4bNyQK73I3+Ix+BXMszv8DaaeS6B31oXE8HT1Ofy8J3TdMPeotlZH724Ws4oc/N5Q== X-Received: by 2002:a17:903:300c:b0:186:9ef5:4d59 with SMTP id o12-20020a170903300c00b001869ef54d59mr51556723pla.89.1669755454986; Tue, 29 Nov 2022 12:57:34 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id c15-20020a170902d48f00b00188c5f0f9e9sm11332038plg.199.2022.11.29.12.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:57:34 -0800 (PST) Date: Tue, 29 Nov 2022 12:57:34 -0800 (PST) X-Google-Original-Date: Tue, 29 Nov 2022 12:57:26 PST (-0800) Subject: Re: [QUERY]: Adding support for a platform In-Reply-To: CC: jrtc27@jrtc27.com, prabhakar.csengg@gmail.com, binutils@sourceware.org, linux-riscv@lists.infradead.org From: Palmer Dabbelt To: Andrew Waterman Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 29 Nov 2022 12:21:31 PST (-0800), Andrew Waterman wrote: > On Tue, Nov 29, 2022 at 12:12 PM Jessica Clarke wrote: >> >> On 29 Nov 2022, at 19:28, Lad, Prabhakar wrote: >> > >> > Hi Palmer, >> > >> > Oops I should have included linux-riscv to the CC list here (doing it now) >> > >> > On Tue, Nov 29, 2022 at 7:20 PM Palmer Dabbelt wrote: >> >> >> >> On Tue, 29 Nov 2022 11:16:29 PST (-0800), binutils@sourceware.org wrote: >> >>> Hi All, >> >>> >> >>> If this is not the right place to ask this question please let me know. >> >>> >> >>> So we have a RISCV platform (Renesas RZ/Five) for which we need to >> >>> adjust the TEXT_START_ADDR. So below are my queries: >> >>> * What is the procedure for upstreaming? >> >>> * Are patches accepted for individual platforms (for adjusting TEXT_START_ADDR)? >> >> >> >> Is this still related to that bug with the static binaries you'd >> >> mentioned before? I think we'd really need to figure out the root cause >> >> before we can make a reasoned decision here, my guess would be that >> >> changing TEXT_START_ADDR just works around the real bug. >> >> >> > Below is the root cause and the solution: >> > >> > TEXT_START_ADDR is the start of the text segment of an application. >> > This is being set to 0x10000 for RISCV platforms. >> > >> > So when an application is compiled with the static flag the load would >> > start from 0x10000 - xyz (depending on size of the application) >> > >> > Entry point 0x101c0 >> > There are 5 program headers, starting at offset 64Program Headers: >> > Type Offset VirtAddr PhysAddr >> > FileSiz MemSiz Flags Align >> > LOAD 0x0000000000000000 0x0000000000010000 0x0000000000010000 >> > 0x0000000000059b48 0x0000000000059b48 R E 0x1000 >> > LOAD 0x0000000000059b60 0x000000000006ab60 0x000000000006ab60 >> > 0x0000000000001f68 0x0000000000003528 RW 0x1000 >> > >> > So for the above application which is compiled statically we can see >> > the entry point is 0x101c0 and load 0x0000000000010000. >> > >> > Andes AX45MP cores have local memory ILM and DLM that are mapped in >> > the region H’0_0003_0000 - H’0_0004_FFFF on the RZ/Five SoC. When the >> > virtual address falls in this range the MMU doesn't trigger a page >> > fault and assumes the virtual address as physical address and hence >> > the application fails to run (panics somewhere). >> > >> > So to avoid this issue we set the TEXT_START_ADDR to 0x50000 so that >> > the virtual address of any statically compiled application does not >> > fall in the range of H’0_0003_0000 - H’0_0004_FFFF. >> > >> > Elf file type is EXEC (Executable file) >> > Entry point 0x504e4 >> > There are 5 program headers, starting at offset 64 >> > >> > Program Headers: >> > Type Offset VirtAddr PhysAddr >> > FileSiz MemSiz Flags Align >> > LOAD 0x0000000000000000 0x0000000000050000 0x0000000000050000 >> > 0x0000000000057dc8 0x0000000000057dc8 R E 0x1000 >> > LOAD 0x00000000000585b8 0x00000000000a95b8 0x00000000000a95b8 >> > 0x0000000000004ee0 0x00000000000064b0 RW 0x1000 >> > NOTE 0x0000000000000158 0x0000000000050158 0x0000000000050158 >> > 0x0000000000000044 0x0000000000000044 R 0x4 >> > >> > So now with the fix for statically compiled applications we can see >> > its offsetted and entry point is 0x504e4 and load is at >> > 0x0000000000050000. So with this we are for sure the MMU will always >> > trigger a page fault. >> >> Well that’s just a blatant violation of the spec. > > Right - this isn't a platform quirk; it's a violation of the ISA. > Unless this behavior is engaged by a custom mode bit, that is, in > which case, it should just be disabled by default and none of this > would be a problem. If the behavior is unconditionally enabled, this > should be treated as an erratum. I don't see this as any different than the T-Head page table attributes, where it was made abundantly clear that vendors self-certify their implementations and thus anything goes. It doesn't really matter if we called it an errata, bug, surprise feature, vendor extension, whatever; it's RISC-V so we've got to live with it. >> What happens if a >> malicious (or buggy) userspace binary goes and accesses unmapped memory >> in that range? Does it actually get access to this ILM/DLM? If so >> that’s a gaping side channel. IIUC that's the case, but that's just from reading this post. There's nothing we can do to prevent vendors from building hardware with side channels. In this case I suppose we could swap out the memory region on context switches, from a quick look at the datasheet these are single-core so that'd be safe. My guess is it'd be too slow for users to want that on by default, but I don't have any use case for this HW so I'm not sure. >> >> Jess >>