From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 811663858D3C for ; Wed, 26 Apr 2023 21:42:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 811663858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1a66911f5faso61142635ad.0 for ; Wed, 26 Apr 2023 14:42:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20221208.gappssmtp.com; s=20221208; t=1682545371; x=1685137371; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=+ARaxo5aSnaWMmhIlfVN0YCQxFNHzVXvIjChu6218No=; b=xYaPOerMKlFCZic/YO7AL+GdexHusX5q2F7O/svIb/BIeT4rZvQ/aWw4r1vH5DKTE7 rSKFhodh4vgNk7SY2yE2xfW1v87HHz9MJoX3Xslajcwi8qe/351sxs4D/Id9zzo1PDty T76cECLgMQuJnV6YCh8PxTytRTbXiAaihQyLMdGzkMR28OC5+tZjnR23Clr+imRxnGFq KaFXIE7NFgqGmJo7G/sMC4OcJMU9lcybMxyFktcwdP8pZH3RVPQBA+cualctSQX2YakD vHsf4X1R+RArLWGD7rnT1EecLmZy2sBHvgwFeWayKr9pIxlsT9Gx1z4T3t5P+THPWb1y PLZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682545371; x=1685137371; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=+ARaxo5aSnaWMmhIlfVN0YCQxFNHzVXvIjChu6218No=; b=iZcXtlsnTiiLCkh/CTIhIBED1HTcLA9crcw0Z79WPapj4i1vcgdtkDUL35ov9Lp+O7 g8rKFCWqQ5MqHMkGsgLiE1jtN8cFvbHHrXhnw11lhDK5f0uYFg4YBLPUFdLdiSphY+8E sOuG2nDNZp7LVRkRWzKJZFc2GOVCoI+BC3FpAG/CDuhEZTpOdVLUXgezDV/lcoV73e54 I9vMibFSQYr9tPFd0BA3n1l83YKdhvMer6jrQInwX3F1Z3S9MRpXR3dfNV+e1/Uq0tLq EtxwFDB3WxjZAxqxPBMFFRXQXt87sJ9TCfkzALY7EFn9b19bleAk1deh2yUzOsrMTRS5 TIMA== X-Gm-Message-State: AAQBX9dch7TRLPM2/HaKBlFX1gBqzQLw57TmaG36JPkwtnwj4KP7NGnC RDU0D0ZKPe5ACeT1v0BWyu2GCNMEqHoHcLVrnYo= X-Google-Smtp-Source: AKy350a5w1y+BDnbAGS8QVIb/aH0Ms8XLDZGZChoI8XC2D1yJyWts9z+7Fv5SUO9hSV3SnQz0GwU/g== X-Received: by 2002:a17:902:c74a:b0:1a5:a1b:bbd8 with SMTP id q10-20020a170902c74a00b001a50a1bbbd8mr19057115plq.45.1682545370988; Wed, 26 Apr 2023 14:42:50 -0700 (PDT) Received: from localhost ([135.180.227.0]) by smtp.gmail.com with ESMTPSA id iy17-20020a170903131100b001a66e81d8fdsm10387050plb.116.2023.04.26.14.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 14:42:50 -0700 (PDT) Date: Wed, 26 Apr 2023 14:42:50 -0700 (PDT) X-Google-Original-Date: Wed, 26 Apr 2023 14:42:48 PDT (-0700) Subject: Re: [committed] RISC-V: XVentanaCondops support In-Reply-To: CC: binutils@sourceware.org From: Palmer Dabbelt To: Jeff Law Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 26 Apr 2023 14:16:10 PDT (-0700), Jeff Law wrote: > > > On 4/26/23 15:09, Palmer Dabbelt wrote: > >>> >>> The Veyron V1 processor implements XVentanaCondOps, but not Zicond. >>> That's simply due to timing. >> >> Do you have a link to anything that says this?  I don't think we ever >> got a hard definition of what the requirements are, just some sort of >> annocement that the chip is going to be publicly availiable.  There's >> some stuff on the Ventana website, but it's all sort of vague marketing >> type stuff. > The processor was announced back in December at the summit which I > thought was the requirement that you and Philipp had worked out. We had the various RISC-V port maintainers and long-term contributors in FSF toolchain land (ie, binutils/GCC/glibc) agree on something posted to the mailing list. Philipp and I certainly talked about it, but there's no private agreements or anything like that -- it's just what we discuss on the mailing lists. Unfortunately he has along history of misrepresenting things, but that's really why we're so careful about making sure that all the decisions are talked about on the lists. > We're still waiting on hardware for bring-up. But in terms of the > processor features/ISA, that's immutable at this point (as much as I > wish that weren't the case). The idea was to have some sort of timeline around availability of the hardware -- essentially the goal is to avoid being stuck supporting stuff that doesn't actually make it out of the lab. I can't find anything that actually says that, but then also I'm pretty much allergic to chip company marketing material these days so I sort of stay out of it ;) The best I've been able to find is this "Veyron V1 is Highest Performance RISC-V Processor running at 3.6GHz in 5nm" [1]. The big-ticket ones like an SDK and dev board don't seem to exist anywhere outside of press releases, though (there's a github [2], but no SDK). I know it's kind of pedantic, but we've had a lot of issues in the past with RISC-V folks making stuff up and trying to push around upstream. I'm not saying you're doing that, you've been around long enough that if you say you have a chip I believe you. The goal is to be fair to everyone, though -- essentially the same as what happened for the GCC patches. 1: https://www.ventanamicro.com/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family/ 2: https://github.com/ventana-micro-systems