From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by sourceware.org (Postfix) with ESMTPS id 0F46D3834360 for ; Fri, 16 Dec 2022 19:00:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0F46D3834360 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pf1-x42a.google.com with SMTP id c7so2370334pfc.12 for ; Fri, 16 Dec 2022 11:00:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=OVLSku5736lW6WsjqdaaNl7Ry7V230+PEvb4d53CldY=; b=5CpUKZLHcdtLg8gvNLUQll+G6zoVx+kdnS0J2MiDWNRd+q5K7H+MCMOaCwSuEZw1WT Y0NlSnGK4Q2dkSdlNGLPZTl3GzqRZIiQ9wnNXRRWuJAVg/noajiTfpzAoUC1QmP80r99 naMGwHKAP9ugXUlm1vJsBNhXR1abuGZXSW/+pB764kQ17epuqojeH1rHyKJZsHxQpvXQ SaJ6femGlsjhzzlt7/xFpjgSU+usuakVmFj5c8mnwe7Yv51DwfLnjfl1VGLsCTfAA7// GaI7OU6fzovZIXi8L9a5RLq/k5RjomQ3U/ZmpE2/GjVU6UHH30gnhfHWm5se55sHwT3B D5kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=OVLSku5736lW6WsjqdaaNl7Ry7V230+PEvb4d53CldY=; b=vsrDlnEVXJTWHTo8DOGwxY1iOwM2Q4ns1stZGUbol5YmS/hAwNO/06G4jajXdbtDuG /TsAzkTSa+djKjEqcUV7Oc1l9iC8swTGl/T1loZ1euRQ4JxlzsgjQGgaouMxnU1YIl6E DZhVGE1BZUQ/U3bVcFp5L39ef4c8SgyBsFkqC9DjfX3XVKUAcBD0+csxi9jalTBS8TNn ggBJEaGTMMl/Doaf7zC8FjIOTJxcayNJykmUY4++vjbaatoGYAGnL3o3BVKRM6bfKuTo 7oVFxTLkRNGWt8OrVexBXQMzbC3Vj6+bGsjpMJeLahy3hD4ckpeZL8x0Akn21sIsVJv9 QJUQ== X-Gm-Message-State: ANoB5pkfRnfblzRJVDmgso8Owek1j7DaSKFFghZ+JQjlqfALhpOz2++y phsMElIZLYrRoHe6rGTTj2JQotVeAVAAF73x X-Google-Smtp-Source: AA0mqf7DTqD0f280rajh13CJ2hjMF5yYQfaDt8knOk8mxkaCid4b57LALAwColgQMCOvPk5GAiK/Zg== X-Received: by 2002:a62:f906:0:b0:56e:d7f4:3bf9 with SMTP id o6-20020a62f906000000b0056ed7f43bf9mr29496534pfh.7.1671217225597; Fri, 16 Dec 2022 11:00:25 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id y141-20020a626493000000b005751f455e0esm1804703pfb.120.2022.12.16.11.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 11:00:25 -0800 (PST) Date: Fri, 16 Dec 2022 11:00:25 -0800 (PST) X-Google-Original-Date: Fri, 16 Dec 2022 11:00:10 PST (-0800) Subject: Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding In-Reply-To: CC: binutils@sourceware.org, nelson@rivosinc.com, Andrew Waterman , Jim Wilson , research_trasio@irq.a4lg.com, philipp.tomsich@vrull.eu, cooper.qu@linux.alibaba.com, lifang_xia@linux.alibaba.com, yunhai@linux.alibaba.com, zhiwei_liu@linux.alibaba.com From: Palmer Dabbelt To: christoph.muellner@vrull.eu Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 16 Dec 2022 10:59:53 PST (-0800), christoph.muellner@vrull.eu wrote: > On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt wrote: > >> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu >> wrote: >> > From: Christoph Müllner >> > >> > A recent change in the XTheadFmv spec fixed an encoding bug in the >> > document. This patch changes the code to follow this bugfix. >> > >> > Spec patch can be found here: >> > https://github.com/T-head-Semi/thead-extension-spec/pull/11 >> >> There's not much info in there. Was this just a bug in the ISA manual? >> In other words, does the existing hardware (I know of at least C906s and >> C910s in the wild) behave the new way already? In that case >> > > Yes, this was just a bug in the ISA manual, which slipped through the > review. > The manual now matches the implementation. OK, thanks! > > > >> >> Reviewed-by: Palmer Dabbelt >> >> but if the hardware has the old behavior then we'll need to do something >> more complicated to avoid breaking compatibility. >> >> > >> > Signed-off-by: Christoph Müllner >> > --- >> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++-- >> > include/opcode/riscv-opc.h | 4 ++-- >> > 2 files changed, 4 insertions(+), 4 deletions(-) >> > >> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d >> b/gas/testsuite/gas/riscv/x-thead-fmv.d >> > index f2bbe010beb..af8ce0c8ee0 100644 >> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d >> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d >> > @@ -7,5 +7,5 @@ >> > Disassembly of section .text: >> > >> > 0+000 : >> > -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 >> > -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 >> > +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 >> > +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 >> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h >> > index 06e3df0f5a6..5420bfac91b 100644 >> > --- a/include/opcode/riscv-opc.h >> > +++ b/include/opcode/riscv-opc.h >> > @@ -2209,9 +2209,9 @@ >> > #define MATCH_TH_FSURW 0x5000700b >> > #define MASK_TH_FSURW 0xf800707f >> > /* Vendor-specific (T-Head) XTheadFmv instructions. */ >> > -#define MATCH_TH_FMV_HW_X 0x6000100b >> > +#define MATCH_TH_FMV_HW_X 0x5000100b >> > #define MASK_TH_FMV_HW_X 0xfff0707f >> > -#define MATCH_TH_FMV_X_HW 0x5000100b >> > +#define MATCH_TH_FMV_X_HW 0x6000100b >> > #define MASK_TH_FMV_X_HW 0xfff0707f >> > /* Vendor-specific (T-Head) XTheadInt instructions. */ >> > #define MATCH_TH_IPOP 0x0050000b >>