From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by sourceware.org (Postfix) with ESMTPS id 291B13858D32 for ; Sun, 2 Oct 2022 19:35:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 291B13858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pj1-x1030.google.com with SMTP id h8-20020a17090a054800b00205ccbae31eso13507584pjf.5 for ; Sun, 02 Oct 2022 12:35:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from :in-reply-to:subject:date:from:to:cc:subject:date; bh=wsm8cEyIfLlhexCN2KuMXPZUDk/w8tSUliHyyUuG9GU=; b=a3UxOWAmBwI1qVVV1XEUsOQw3tbs+S9LlncLRVZ6FINLpHl9G2X+m+wGulq1pXxeB9 hQgbIuvKbe9LOqyTMXJub2d9a3j4XqAKQmH8YzOsMTT0bFtNMhu6cSTyoUYRffX8ZlWT +F7DFDza7mlLJdfwcdtMY4uyfgvuF/p1TH+79of7yfKfroMz+AA6VhFxZn4PHCQst+Sy T6kg+Ah15CLmUsOaW6MXkO12uDIAe502XWprVko8BRMmeBWdTvbk6gMocTyn8rOPw9P6 mvulzSuKT0k0SiO3P1NBtTehMuwgvzLmpOCiNKRurMYBr3/4HY8Y6zP2y3moTGEGquaT /smQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date; bh=wsm8cEyIfLlhexCN2KuMXPZUDk/w8tSUliHyyUuG9GU=; b=Qt+Knk56MHPV1PgH1hdM4cyXTSjtOWtmnEZLV1pPszodqvbbRNWy+PkX/lFzwQEk/s aTHgYbrNlag148T2jbLDuuBPHnGl4E6Ptsn825Mp7RbPTmQrRIatf8rqygkHtuEBfESr IK2xVczW10ZgnVksE0YUkbQE/PIlUWjlotPNgmdAUVsZZRX7BM6vl3aL5/hbVhjx/08t HkqJ1+NYDQkksCIonfVA8bPrpVoflwImdgA57RqXucj4cQPOmWVBuiw8vs8MheHI03DL rSntsAXWykJ+ybdUyJAdlbidntcthxQdDZVJrYNBU4OwxRBjS2aS7CwhDylMO05dX4S6 80Ww== X-Gm-Message-State: ACrzQf3tfEOFj2Bu89c4zYJvgU6+KPHKna+V26p55M7BKVP6+Abxr9w/ d04f1miMi3Lvx7U2eMuNnJN1gZPpDfYsC7mY X-Google-Smtp-Source: AMsMyM46JRnXGCgJRwPpJQHSsu2PaMITMyiwEJMT27qG8CNyL7TirIe08kec1pY/FrHdT1y6smZQPw== X-Received: by 2002:a17:903:1246:b0:178:abc9:1a2b with SMTP id u6-20020a170903124600b00178abc91a2bmr18864538plh.74.1664739311320; Sun, 02 Oct 2022 12:35:11 -0700 (PDT) Received: from localhost (76-210-143-223.lightspeed.sntcca.sbcglobal.net. [76.210.143.223]) by smtp.gmail.com with ESMTPSA id nt9-20020a17090b248900b00200b12f2bf3sm5054035pjb.51.2022.10.02.12.35.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 12:35:10 -0700 (PDT) Date: Sun, 02 Oct 2022 12:35:10 -0700 (PDT) X-Google-Original-Date: Sun, 02 Oct 2022 12:35:08 PDT (-0700) Subject: Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers In-Reply-To: <7cea93e7-f75b-2d5a-d63b-73288d4b3e5e@gmail.com> From: Palmer Dabbelt To: binutils@sourceware.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sun, 02 Oct 2022 08:58:56 PDT (-0700), binutils@sourceware.org wrote: > > On 10/1/22 14:27, Andrew Burgess via Binutils wrote: >> Tsukasa OI via Binutils writes: >> >>> Hello, >>> >>> Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF >>> register numbers. RISC-V ABIs Specification (riscv-elf-psabi-doc) is not >>> ratified yet but at least frozen. So, I consider it's stable to upstream >>> it. According to the documentation, it has register numbers 96 (v0) - >>> 127 (v31). >>> >>> [Changes: v1 -> v2] >>> Remove invented word "VPRs" (at least it has no consistent uses in the >>> RISC-V ecosystem) and replaced with "Vector registers" >>> >>> [Changes: v2 -> v3] >>> Changed reference (v1.0-rc3 -> v1.0-rc4). >>> >>> Tracker on GitHub: >>> >>> >>> RISC-V ABIs Specification Version 1.0-rc4: Frozen >>> >>> >>> >>> I also added DWARF register number tests not just for CSRs (existing) and >>> vector registers (I just added), but also for GPRs (0-31) and FPRs >>> (32-63). >> Hi Tsukasa, >> >> I can't approve binutils patches, but as this mentioned RISC-V and >> DWARF, both of which I'm interested in, I took a look :) >> >> Both these patches look good to me. The register numbers align with the >> spec, and the test makes sense. > > Well, that's the key property -- they align with the spec. My worry here was the PDF not aligining with the implementation, but I think I'd just been mis-reading the sources: I'd seen RISCV_PRIV_REGNUM = 4161, RISCV_V0_REGNUM, but hadn't realized that I should actually be looking at RISCV_DWARF_REGNUM_V0 = 96, so this is OK (and it looks like GCC is correct as well). Thanks! > I'm also not sure if I can approve for binutils, but if I can, OK for > the trunk ;-) > > Jeff