From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by sourceware.org (Postfix) with ESMTPS id 455223858437 for ; Tue, 8 Feb 2022 02:00:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 455223858437 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x431.google.com with SMTP id i30so16216563pfk.8 for ; Mon, 07 Feb 2022 18:00:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=sKi4FweeVDcff5rzjqWMAv3DFKHy4N/YkaVEBKwrkzU=; b=4+ilESY+kepKOaktb3aI4QJ6Hf4z76jd3H4VqkEdnd0IO8IiDdPCCWTSg6xvi05FJs T3CRboG9C8PzLCAgvhgxV0GbE7j3aO1kfXV7IAMycPtCXS5036SBs9u2Hjcw48UDzn70 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ABdhPJybgV/o5+4GCR1wL7CNgJTCU7TQankieXX7GDZZgD7Tvbnz2norIgyM24q2PHqajrtDSMMteA== X-Received: by 2002:a63:6842:: with SMTP id d63mr1692928pgc.213.1644285656848; Mon, 07 Feb 2022 18:00:56 -0800 (PST) Received: from localhost ([12.3.194.138]) by smtp.gmail.com with ESMTPSA id a13sm9400670pgv.27.2022.02.07.18.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Feb 2022 18:00:56 -0800 (PST) Date: Mon, 07 Feb 2022 18:00:56 -0800 (PST) X-Google-Original-Date: Mon, 07 Feb 2022 16:44:48 PST (-0800) Subject: Re: [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs In-Reply-To: CC: research_trasio@irq.a4lg.com, binutils@sourceware.org From: Palmer Dabbelt To: binutils@sourceware.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Feb 2022 02:01:01 -0000 On Tue, 01 Feb 2022 05:53:35 PST (-0800), binutils@sourceware.org wrote: > This commit adds several assembler tests for Zdinx register pairs. > > gas/ChangeLog: > > * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx > register pairs. > * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. > * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx > register pairs (failure cases). > * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. > * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. > --- > .../gas/riscv/zdinx-32-regpair-fail.d | 3 + > .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++++++++++++++++ > .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++++++++++++++++ > gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++++++++++ > gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++++++++++ > 5 files changed, 357 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s > > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d > new file mode 100644 > index 00000000000..f26096ca1c9 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d > @@ -0,0 +1,3 @@ > +#as: -march=rv32ima_zdinx > +#source: zdinx-32-regpair-fail.s > +#error_output: zdinx-32-regpair-fail.l > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l > new file mode 100644 > index 00000000000..62451c74d80 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l > @@ -0,0 +1,111 @@ > +.*Assembler messages: > +.*Error: illegal operands `fadd\.d a1,a2,a4' > +.*Error: illegal operands `fadd\.d a1,a2,a4,rtz' > +.*Error: illegal operands `fadd\.d a0,a1,a4' > +.*Error: illegal operands `fadd\.d a0,a1,a4,rtz' > +.*Error: illegal operands `fadd\.d a0,a2,a1' > +.*Error: illegal operands `fadd\.d a0,a2,a1,rtz' > +.*Error: illegal operands `fsub\.d a1,a2,a4' > +.*Error: illegal operands `fsub\.d a1,a2,a4,rtz' > +.*Error: illegal operands `fsub\.d a0,a1,a4' > +.*Error: illegal operands `fsub\.d a0,a1,a4,rtz' > +.*Error: illegal operands `fsub\.d a0,a2,a1' > +.*Error: illegal operands `fsub\.d a0,a2,a1,rtz' > +.*Error: illegal operands `fmul\.d a1,a2,a4' > +.*Error: illegal operands `fmul\.d a1,a2,a4,rtz' > +.*Error: illegal operands `fmul\.d a0,a1,a4' > +.*Error: illegal operands `fmul\.d a0,a1,a4,rtz' > +.*Error: illegal operands `fmul\.d a0,a2,a1' > +.*Error: illegal operands `fmul\.d a0,a2,a1,rtz' > +.*Error: illegal operands `fdiv\.d a1,a2,a4' > +.*Error: illegal operands `fdiv\.d a1,a2,a4,rtz' > +.*Error: illegal operands `fdiv\.d a0,a1,a4' > +.*Error: illegal operands `fdiv\.d a0,a1,a4,rtz' > +.*Error: illegal operands `fdiv\.d a0,a2,a1' > +.*Error: illegal operands `fdiv\.d a0,a2,a1,rtz' > +.*Error: illegal operands `fsqrt\.d a1,a2' > +.*Error: illegal operands `fsqrt\.d a1,a2,rtz' > +.*Error: illegal operands `fsqrt\.d a0,a1' > +.*Error: illegal operands `fsqrt\.d a0,a1,rtz' > +.*Error: illegal operands `fmin\.d a1,a2,a4' > +.*Error: illegal operands `fmin\.d a0,a1,a4' > +.*Error: illegal operands `fmin\.d a0,a2,a1' > +.*Error: illegal operands `fmax\.d a1,a2,a4' > +.*Error: illegal operands `fmax\.d a0,a1,a4' > +.*Error: illegal operands `fmax\.d a0,a2,a1' > +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' > +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' > +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' > +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' > +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' > +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' > +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' > +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' > +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' > +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' > +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' > +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' > +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' > +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' > +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' > +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' > +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fsgnj\.d a1,a2,a4' > +.*Error: illegal operands `fsgnj\.d a0,a1,a4' > +.*Error: illegal operands `fsgnj\.d a0,a2,a1' > +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' > +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' > +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' > +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' > +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' > +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' > +.*Error: illegal operands `fmv\.d a1,a2' > +.*Error: illegal operands `fmv\.d a0,a1' > +.*Error: illegal operands `fneg\.d a1,a2' > +.*Error: illegal operands `fneg\.d a0,a1' > +.*Error: illegal operands `fabs\.d a1,a2' > +.*Error: illegal operands `fabs\.d a0,a1' > +.*Error: illegal operands `feq\.d a0,a1,a4' > +.*Error: illegal operands `feq\.d a0,a2,a1' > +.*Error: illegal operands `flt\.d a0,a1,a4' > +.*Error: illegal operands `flt\.d a0,a2,a1' > +.*Error: illegal operands `fle\.d a0,a1,a4' > +.*Error: illegal operands `fle\.d a0,a2,a1' > +.*Error: illegal operands `fgt\.d a0,a1,a4' > +.*Error: illegal operands `fgt\.d a0,a2,a1' > +.*Error: illegal operands `fge\.d a0,a1,a4' > +.*Error: illegal operands `fge\.d a0,a2,a1' > +.*Error: illegal operands `fclass\.d a0,a1' > +.*Error: illegal operands `fcvt\.w\.d a0,a1' > +.*Error: illegal operands `fcvt\.w\.d a0,a1,rtz' > +.*Error: illegal operands `fcvt\.w\.d a3,a1' > +.*Error: illegal operands `fcvt\.w\.d a3,a1,rtz' > +.*Error: illegal operands `fcvt\.wu\.d a0,a1' > +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rtz' > +.*Error: illegal operands `fcvt\.wu\.d a3,a1' > +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rtz' > +.*Error: illegal operands `fcvt\.d\.w a1,a2' > +.*Error: illegal operands `fcvt\.d\.w a1,a3' > +.*Error: illegal operands `fcvt\.d\.wu a1,a2' > +.*Error: illegal operands `fcvt\.d\.wu a1,a3' > +.*Error: illegal operands `fcvt\.s\.d a0,a1' > +.*Error: illegal operands `fcvt\.s\.d a0,a1,rtz' > +.*Error: illegal operands `fcvt\.s\.d a3,a1' > +.*Error: illegal operands `fcvt\.s\.d a3,a1,rtz' > +.*Error: illegal operands `fcvt\.d\.s a1,a2' > +.*Error: illegal operands `fcvt\.d\.s a1,a3' > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s > new file mode 100644 > index 00000000000..5539d9ef3fc > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s > @@ -0,0 +1,116 @@ > +target: > + fadd.d a1, a2, a4 > + fadd.d a1, a2, a4, rtz > + fadd.d a0, a1, a4 > + fadd.d a0, a1, a4, rtz > + fadd.d a0, a2, a1 > + fadd.d a0, a2, a1, rtz > + fsub.d a1, a2, a4 > + fsub.d a1, a2, a4, rtz > + fsub.d a0, a1, a4 > + fsub.d a0, a1, a4, rtz > + fsub.d a0, a2, a1 > + fsub.d a0, a2, a1, rtz > + fmul.d a1, a2, a4 > + fmul.d a1, a2, a4, rtz > + fmul.d a0, a1, a4 > + fmul.d a0, a1, a4, rtz > + fmul.d a0, a2, a1 > + fmul.d a0, a2, a1, rtz > + fdiv.d a1, a2, a4 > + fdiv.d a1, a2, a4, rtz > + fdiv.d a0, a1, a4 > + fdiv.d a0, a1, a4, rtz > + fdiv.d a0, a2, a1 > + fdiv.d a0, a2, a1, rtz > + fsqrt.d a1, a2 > + fsqrt.d a1, a2, rtz > + fsqrt.d a0, a1 > + fsqrt.d a0, a1, rtz > + fmin.d a1, a2, a4 > + fmin.d a0, a1, a4 > + fmin.d a0, a2, a1 > + fmax.d a1, a2, a4 > + fmax.d a0, a1, a4 > + fmax.d a0, a2, a1 > + fmadd.d a1, a2, a4, a6 > + fmadd.d a1, a2, a4, a6, rtz > + fmadd.d a0, a1, a4, a6 > + fmadd.d a0, a1, a4, a6, rtz > + fmadd.d a0, a2, a1, a6 > + fmadd.d a0, a2, a1, a6, rtz > + fmadd.d a0, a2, a4, a1 > + fmadd.d a0, a2, a4, a1, rtz > + fnmadd.d a1, a2, a4, a6 > + fnmadd.d a1, a2, a4, a6, rtz > + fnmadd.d a0, a1, a4, a6 > + fnmadd.d a0, a1, a4, a6, rtz > + fnmadd.d a0, a2, a1, a6 > + fnmadd.d a0, a2, a1, a6, rtz > + fnmadd.d a0, a2, a4, a1 > + fnmadd.d a0, a2, a4, a1, rtz > + fmsub.d a1, a2, a4, a6 > + fmsub.d a1, a2, a4, a6, rtz > + fmsub.d a0, a1, a4, a6 > + fmsub.d a0, a1, a4, a6, rtz > + fmsub.d a0, a2, a1, a6 > + fmsub.d a0, a2, a1, a6, rtz > + fmsub.d a0, a2, a4, a1 > + fmsub.d a0, a2, a4, a1, rtz > + fnmsub.d a1, a2, a4, a6 > + fnmsub.d a1, a2, a4, a6, rtz > + fnmsub.d a0, a1, a4, a6 > + fnmsub.d a0, a1, a4, a6, rtz > + fnmsub.d a0, a2, a1, a6 > + fnmsub.d a0, a2, a1, a6, rtz > + fnmsub.d a0, a2, a4, a1 > + fnmsub.d a0, a2, a4, a1, rtz > + fsgnj.d a1, a2, a4 > + fsgnj.d a0, a1, a4 > + fsgnj.d a0, a2, a1 > + fsgnjn.d a1, a2, a4 > + fsgnjn.d a0, a1, a4 > + fsgnjn.d a0, a2, a1 > + fsgnjx.d a1, a2, a4 > + fsgnjx.d a0, a1, a4 > + fsgnjx.d a0, a2, a1 > + fmv.d a1, a2 > + fmv.d a0, a1 > + fneg.d a1, a2 > + fneg.d a0, a1 > + fabs.d a1, a2 > + fabs.d a0, a1 > + # Compare instructions: destination is a GPR > + feq.d a0, a1, a4 > + feq.d a0, a2, a1 > + flt.d a0, a1, a4 > + flt.d a0, a2, a1 > + fle.d a0, a1, a4 > + fle.d a0, a2, a1 > + fgt.d a0, a1, a4 > + fgt.d a0, a2, a1 > + fge.d a0, a1, a4 > + fge.d a0, a2, a1 > + # fclass instruction: destination is a GPR > + fclass.d a0, a1 > + # fcvt instructions (float-int or int-float; > + # integer operand register can be odd) > + fcvt.w.d a0, a1 > + fcvt.w.d a0, a1, rtz > + fcvt.w.d a3, a1 > + fcvt.w.d a3, a1, rtz > + fcvt.wu.d a0, a1 > + fcvt.wu.d a0, a1, rtz > + fcvt.wu.d a3, a1 > + fcvt.wu.d a3, a1, rtz > + fcvt.d.w a1, a2 > + fcvt.d.w a1, a3 > + fcvt.d.wu a1, a2 > + fcvt.d.wu a1, a3 > + # fcvt instructions (float-float; FP32 operand can be odd) > + fcvt.s.d a0, a1 > + fcvt.s.d a0, a1, rtz > + fcvt.s.d a3, a1 > + fcvt.s.d a3, a1, rtz > + fcvt.d.s a1, a2 > + fcvt.d.s a1, a3 > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d > new file mode 100644 > index 00000000000..5e3c1a88592 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d > @@ -0,0 +1,65 @@ > +#as: -march=rv32ima_zdinx > +#source: zdinx-32-regpair.s > +#objdump: -dr > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+02e61553[ ]+fadd.d[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+0ae61553[ ]+fsub.d[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+12e61553[ ]+fmul.d[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+1ae61553[ ]+fdiv.d[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+5a061553[ ]+fsqrt.d[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+82e61543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+82e6154f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+82e61547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+82e6154b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 > +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c2061553[ ]+fcvt.w.d[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c20615d3[ ]+fcvt.w.d[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c2161553[ ]+fcvt.wu.d[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c21615d3[ ]+fcvt.wu.d[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+40161553[ ]+fcvt.s.d[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+401615d3[ ]+fcvt.s.d[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s > new file mode 100644 > index 00000000000..62807248e77 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s > @@ -0,0 +1,62 @@ > +target: > + fadd.d a0, a2, a4 > + fadd.d a0, a2, a4, rtz > + fsub.d a0, a2, a4 > + fsub.d a0, a2, a4, rtz > + fmul.d a0, a2, a4 > + fmul.d a0, a2, a4, rtz > + fdiv.d a0, a2, a4 > + fdiv.d a0, a2, a4, rtz > + fsqrt.d a0, a2 > + fsqrt.d a0, a2, rtz > + fmin.d a0, a2, a4 > + fmax.d a0, a2, a4 > + fmadd.d a0, a2, a4, a6 > + fmadd.d a0, a2, a4, a6, rtz > + fnmadd.d a0, a2, a4, a6 > + fnmadd.d a0, a2, a4, a6, rtz > + fmsub.d a0, a2, a4, a6 > + fmsub.d a0, a2, a4, a6, rtz > + fnmsub.d a0, a2, a4, a6 > + fnmsub.d a0, a2, a4, a6, rtz > + fsgnj.d a0, a2, a4 > + fsgnjn.d a0, a2, a4 > + fsgnjx.d a0, a2, a4 > + fmv.d a0, a2 > + fneg.d a0, a2 > + fabs.d a0, a2 > + # Compare instructions: destination is a GPR > + feq.d a0, a2, a4 > + feq.d a1, a2, a4 > + flt.d a0, a2, a4 > + flt.d a1, a2, a4 > + fle.d a0, a2, a4 > + fle.d a1, a2, a4 > + fgt.d a0, a2, a4 > + fgt.d a1, a2, a4 > + fge.d a0, a2, a4 > + fge.d a1, a2, a4 > + # fclass instruction: destination is a GPR > + fclass.d a0, a2 > + fclass.d a1, a2 > + # fcvt instructions (float-int or int-float; > + # integer operand register can be odd) > + fcvt.w.d a0, a2 > + fcvt.w.d a0, a2, rtz > + fcvt.w.d a1, a2 > + fcvt.w.d a1, a2, rtz > + fcvt.wu.d a0, a2 > + fcvt.wu.d a0, a2, rtz > + fcvt.wu.d a1, a2 > + fcvt.wu.d a1, a2, rtz > + fcvt.d.w a0, a2 > + fcvt.d.w a0, a1 > + fcvt.d.wu a0, a2 > + fcvt.d.wu a0, a1 > + # fcvt instructions (float-float; FP32 operand can be odd) > + fcvt.s.d a0, a2 > + fcvt.s.d a0, a2, rtz > + fcvt.s.d a1, a2 > + fcvt.s.d a1, a2, rtz > + fcvt.d.s a0, a2 > + fcvt.d.s a0, a1 Reviewed-by: Palmer Dabbelt