From: Palmer Dabbelt <palmer@dabbelt.com>
To: Nelson Chu <nelson.chu@sifive.com>
Cc: binutils@sourceware.org, Jim Wilson <jim.wilson.gcc@gmail.com>,
kito.cheng@sifive.com, Andrew Waterman <andrew@sifive.com>,
Nelson Chu <nelson.chu@sifive.com>
Subject: Re: [PATCH 2/2] RISC-V: Updated the default ISA spec to 20191213.
Date: Thu, 30 Dec 2021 08:46:59 -0800 (PST) [thread overview]
Message-ID: <mhng-b1c21d32-0470-4bfe-abc8-513d443d1185@palmer-ri-x1c9> (raw)
In-Reply-To: <1640880028-16820-2-git-send-email-nelson.chu@sifive.com>
On Thu, 30 Dec 2021 08:00:28 PST (-0800), Nelson Chu wrote:
> Update the default ISA spec from 2.2 to 20191213 will change the default
> version of i from 2.0 to 2.1. Since zicsr and zifencei are separated
> from i 2.1, users need to add them in the architecture string if they need
> fence.i and csr instructions. Besides, we also allow old ISA spec can
> recognize zicsr and zifencei, but we won't output them since they are
> already included in the i extension when i's version is less than 2.1.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
IIRC we talked about this at some point. It's going to cause churn for
users, but there's nothing we can do to avoid that because the ISA
changed in an incompatible fashion. We might as well rip the band-aid
off now, it's been two years ;)
I'd been playing around with providing a better message here --
essentially adding some fake patterns that match the assembler mnemonic
and print out a hint along the lines of "fence.i is no longer in i, you
need zifencei". I thought I had this floating around somewhere, but I
can't find it.
>
> bfd/
> * elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
> recognize zicsr and zifencei.
> gas/
> * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
> * testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
> the default version of i is 2.1.
> * testsuite/gas/riscv/csr-version-1p11.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p12.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
> * testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
> * testsuite/gas/riscv/option-arch-03.s: Likewise.
> ld/
> * testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
> the default version of i is 2.1.
> * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
> * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d: Likewise.
> ---
> bfd/elfxx-riscv.c | 4 +++-
> gas/config/tc-riscv.c | 2 +-
> gas/testsuite/gas/riscv/csr-version-1p10.d | 2 +-
> gas/testsuite/gas/riscv/csr-version-1p11.d | 2 +-
> gas/testsuite/gas/riscv/csr-version-1p12.d | 2 +-
> gas/testsuite/gas/riscv/csr-version-1p9p1.d | 2 +-
> gas/testsuite/gas/riscv/option-arch-03.d | 2 +-
> gas/testsuite/gas/riscv/option-arch-03.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s | 2 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d | 4 +---
> ld/testsuite/ld-riscv-elf/call-relax.d | 2 +-
> 23 files changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index c575ab0..83705ec 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1562,7 +1562,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
> rps->error_handler
> (_("x ISA extension `%s' must be set with the versions"),
> subset);
> - else
> + /* Allow old ISA spec can recognize zicsr and zifencei. */
> + else if (strcmp (subset, "zicsr") != 0
> + && strcmp (subset, "zifencei") != 0)
> rps->error_handler
> (_("cannot find default versions of the ISA extension `%s'"),
> subset);
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index dbf0e23..debe6bf 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -104,7 +104,7 @@ struct riscv_csr_extra
>
> /* Need to sync the version with RISC-V compiler. */
> #ifndef DEFAULT_RISCV_ISA_SPEC
> -#define DEFAULT_RISCV_ISA_SPEC "2.2"
> +#define DEFAULT_RISCV_ISA_SPEC "20191213"
> #endif
>
> #ifndef DEFAULT_RISCV_PRIV_SPEC
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
> index ee56ae3..88da724 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p10.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv64i -mcsr-check -mpriv-spec=1.10
> +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.10
> #source: csr.s
> #warning_output: csr-version-1p10.l
> #objdump: -dr -Mpriv-spec=1.10
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
> index a1d8169..b40c1d5 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p11.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv64i -mcsr-check -mpriv-spec=1.11
> +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.11
> #source: csr.s
> #warning_output: csr-version-1p11.l
> #objdump: -dr -Mpriv-spec=1.11
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
> index c4c2118..fbc30ee 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p12.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv64i -mcsr-check -mpriv-spec=1.12
> +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.12
> #source: csr.s
> #warning_output: csr-version-1p12.l
> #objdump: -dr -Mpriv-spec=1.12
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> index 01e05ae..a96e8c9 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv64i -mcsr-check -mpriv-spec=1.9.1
> +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1
> #source: csr.s
> #warning_output: csr-version-1p9p1.l
> #objdump: -dr -Mpriv-spec=1.9.1
> diff --git a/gas/testsuite/gas/riscv/option-arch-03.d b/gas/testsuite/gas/riscv/option-arch-03.d
> index b621d03..62d7f7d 100644
> --- a/gas/testsuite/gas/riscv/option-arch-03.d
> +++ b/gas/testsuite/gas/riscv/option-arch-03.d
> @@ -4,5 +4,5 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_c2p0"
> + Tag_RISCV_arch: "rv32i2p1_c2p0"
> #...
> diff --git a/gas/testsuite/gas/riscv/option-arch-03.s b/gas/testsuite/gas/riscv/option-arch-03.s
> index d982a0b..ccdb1c3 100644
> --- a/gas/testsuite/gas/riscv/option-arch-03.s
> +++ b/gas/testsuite/gas/riscv/option-arch-03.s
> @@ -1,3 +1,3 @@
> .attribute arch, "rv64ic"
> .option arch, +d2p0, -c
> -.option arch, rv32ic
> +.option arch, rv32i2p1c2p0
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> index c148cdb..a4b0322 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> @@ -6,4 +6,4 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0"
> + Tag_RISCV_arch: "rv32i2p1_m2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
> index acc98a5..ea097f9 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i2p0_m2p0"
> + .attribute arch, "rv32i2p1_m2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
> index acc98a5..ea097f9 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i2p0_m2p0"
> + .attribute arch, "rv32i2p1_m2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> index bc0e0fd..852fd55 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> @@ -6,4 +6,4 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0"
> + Tag_RISCV_arch: "rv32i2p1_m2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
> index acc98a5..ea097f9 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i2p0_m2p0"
> + .attribute arch, "rv32i2p1_m2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
> index 65d0fef..610c7e5 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i2p0"
> + .attribute arch, "rv32i2p1"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> index 374a043..c1cf808 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> @@ -6,4 +6,4 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
> + Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
> index b86cc55..3a9fb97 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i2p0_m2p0_xfoo2p0"
> + .attribute arch, "rv32i2p1_m2p0_xfoo2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
> index 376e373..878f2de 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i2p0_xbar2p0"
> + .attribute arch, "rv32i2p1_xbar2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s
> index e7fadf0..e05cb1e 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-a.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i0p1_m0p1_a0p1_zicsr0p1_xunknown0p1"
> + .attribute arch, "rv32i2p1_m0p1_a0p1_zicsr0p1_xunknown0p1"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s
> index 1a7a11c..91de4f4 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-b.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i0p9_m0p9_a0p9_zicsr0p9_xunknown0p9"
> + .attribute arch, "rv32i2p1_m0p9_a0p9_zicsr0p9_xunknown0p9"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s
> index 1a935e7..5b42d52 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-c.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i1p0_m1p0_a1p0_zicsr1p0_xunknown1p0"
> + .attribute arch, "rv32i2p1_m1p0_a1p0_zicsr1p0_xunknown1p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s
> index 3dbf8a2..4c4421b 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified-d.s
> @@ -1 +1 @@
> - .attribute arch, "rv32i2p0_m2p0_a2p0_zicsr2p0_xunknown2p0"
> + .attribute arch, "rv32i2p1_m2p0_a2p0_zicsr2p0_xunknown2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d
> index b835aa3..8b9140c 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-ratified.d
> @@ -4,12 +4,10 @@
> #source: attr-merge-arch-failed-ratified-d.s
> #as: -march-attr
> #ld: -r -m[riscv_choose_ilp32_emul]
> -#warning: .*mis-matched ISA version 0.9 for 'i' extension, the output version is 0.1
> #warning: .*mis-matched ISA version 0.9 for 'm' extension, the output version is 0.1
> #warning: .*mis-matched ISA version 0.9 for 'a' extension, the output version is 0.1
> #warning: .*mis-matched ISA version 0.9 for 'zicsr' extension, the output version is 0.1
> #warning: .*mis-matched ISA version 0.9 for 'xunknown' extension, the output version is 0.1
> -#warning: .*mis-matched ISA version 1.0 for 'i' extension, the output version is 0.9
> #warning: .*mis-matched ISA version 1.0 for 'm' extension, the output version is 0.9
> #warning: .*mis-matched ISA version 1.0 for 'a' extension, the output version is 0.9
> #warning: .*mis-matched ISA version 1.0 for 'zicsr' extension, the output version is 0.9
> @@ -18,5 +16,5 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_zicsr2p0_xunknown2p0"
> + Tag_RISCV_arch: "rv32i2p1_m2p0_a2p0_zicsr2p0_xunknown2p0"
> #..
> diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
> index c6022be..f8f0229 100644
> --- a/ld/testsuite/ld-riscv-elf/call-relax.d
> +++ b/ld/testsuite/ld-riscv-elf/call-relax.d
> @@ -3,7 +3,7 @@
> #source: call-relax-1.s
> #source: call-relax-2.s
> #source: call-relax-3.s
> -#as: -march=rv32ic -mno-arch-attr
> +#as: -march=rv32ic_zicsr -mno-arch-attr
> #ld: -m[riscv_choose_ilp32_emul]
> #objdump: -d
> #pass
next prev parent reply other threads:[~2021-12-30 16:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-30 16:00 [PATCH 1/2] RISC-V: Don't report mismatch warnings when versions are larger than 1.0 Nelson Chu
2021-12-30 16:00 ` [PATCH 2/2] RISC-V: Updated the default ISA spec to 20191213 Nelson Chu
2021-12-30 16:46 ` Palmer Dabbelt [this message]
2022-01-07 11:02 ` Nelson Chu
2022-02-06 12:26 ` [PATCH 1/2] RISC-V: Don't report mismatch warnings when versions are larger than 1.0 Aurelien Jarno
2022-02-07 21:09 ` Palmer Dabbelt
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