[PATCH v2 0/3] RISC-V: Zfinx extension support

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* [PATCH v2 0/3] RISC-V: Zfinx extension support
@ 2021-11-17 12:10 jiawei
  2021-11-17 12:10 ` [PATCH v2 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
                   ` (2 more replies)
  0 siblings, 3 replies; 8+ messages in thread
From: jiawei @ 2021-11-17 12:10 UTC (permalink / raw)
  To: binutils
  Cc: tariq.kurd, kito.cheng, nelson.chu, jim.wilson.gcc,
	jeremy.bennett, cmuellner, palmer, andrew, philipp.tomsich,
	lazyparser, sinan, shihua, jiawei

This patch is support zfinx extension on binutils, 
zfinx is not compatible with any float extension 
and use gpr replace fpr. We adjust the opreand set
when zfinx used. 

For disassemble part, use the function "riscv_subset_supports" 
to check if zfinx is enable as Nelson Chu's comment, 
once the arch has zfinx, then the disassblemer will 
use gpr instead of fpr with instruction generator.

Version log:

v2: Remove zfinx elf flag, use riscv_subset_supports to recongenize
whether zfinx enable or not. Adjust INSN_CLASS_* implement order in
patches. Use INSN_CLASS_F_OR_ZFINX instead of INSN_CLASS_ZFINX and
add register group choice in reg_lookup. Add Changelog in all patches
Thanks for Nelson Chu's comment.

jiawei (3):
  RISC-V: Add mininal support for z[fdq]inx
  RISC-V: Add instructions and operand set for z[fdq]inx
  RISC-V: Add testcases  for z[fdq]inx

 bfd/elfxx-riscv.c               |  21 +++
 gas/config/tc-riscv.c           |   4 +-
 gas/testsuite/gas/riscv/zdinx.d |  42 +++++
 gas/testsuite/gas/riscv/zdinx.s |  34 ++++
 gas/testsuite/gas/riscv/zfinx.d |  40 +++++
 gas/testsuite/gas/riscv/zfinx.s |  32 ++++
 gas/testsuite/gas/riscv/zqinx.d |  44 +++++
 gas/testsuite/gas/riscv/zqinx.s |  36 ++++
 include/opcode/riscv.h          |   3 +
 opcodes/riscv-dis.c             |   4 +
 opcodes/riscv-opc.c             | 296 ++++++++++++++++----------------
 11 files changed, 407 insertions(+), 149 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/zdinx.d
 create mode 100644 gas/testsuite/gas/riscv/zdinx.s
 create mode 100644 gas/testsuite/gas/riscv/zfinx.d
 create mode 100644 gas/testsuite/gas/riscv/zfinx.s
 create mode 100644 gas/testsuite/gas/riscv/zqinx.d
 create mode 100644 gas/testsuite/gas/riscv/zqinx.s

-- 
2.25.1

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2 1/3] RISC-V: Add mininal support for z[fdq]inx
  2021-11-17 12:10 [PATCH v2 0/3] RISC-V: Zfinx extension support jiawei
@ 2021-11-17 12:10 ` jiawei
  2021-11-18  2:15   ` Palmer Dabbelt
  2021-11-17 12:10 ` [PATCH v2 2/3] RISC-V: Add instructions and operand set " jiawei
  2021-11-17 12:10 ` [PATCH v2 3/3] RISC-V: Add testcases " jiawei
  2 siblings, 1 reply; 8+ messages in thread
From: jiawei @ 2021-11-17 12:10 UTC (permalink / raw)
  To: binutils
  Cc: tariq.kurd, kito.cheng, nelson.chu, jim.wilson.gcc,
	jeremy.bennett, cmuellner, palmer, andrew, philipp.tomsich,
	lazyparser, sinan, shihua, jiawei

Minimal support for zfinx, zdinx, zqinx. Like f/d/q, the zqinx 
imply zdinx and zdinx imply zfinx, where zfinx are not compatible 
with f/d/q.

bfd/ChangeLog:

* elfxx-riscv.c (riscv_implicit_subsets): Added implicit rules 
for z*inx extensions.
(riscv_supported_std_z_ext): Added entries for z*inx.
(riscv_parse_check_conflicts): Added conflict check for z*inx.

---
 bfd/elfxx-riscv.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index e2fb4003380..9f03542ab77 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1075,6 +1075,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"q", "d",		check_implicit_always},
   {"d", "f",		check_implicit_always},
   {"f", "zicsr",	check_implicit_always},
+  {"zqinx", "zdinx",	check_implicit_always},
+  {"zdinx", "zfinx",	check_implicit_always},
   {"zk", "zkn",		check_implicit_always},
   {"zk", "zkr",		check_implicit_always},
   {"zk", "zkt",		check_implicit_always},
@@ -1157,6 +1159,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zfinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zdinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zqinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zba",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -1854,6 +1859,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
         (_("rv32e does not support the `f' extension"));
       no_conflict = false;
     }
+  if (riscv_lookup_subset (rps->subset_list, "zfinx", &subset)
+      && (riscv_lookup_subset (rps->subset_list, "f", &subset)))
+    {
+      rps->error_handler
+        (_("`zfinx' is conflict with the `f/d/q' extension"));
+      no_conflict = false;
+    }
   return no_conflict;
 }
 
-- 
2.25.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2 2/3] RISC-V: Add instructions and operand set for z[fdq]inx
  2021-11-17 12:10 [PATCH v2 0/3] RISC-V: Zfinx extension support jiawei
  2021-11-17 12:10 ` [PATCH v2 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
@ 2021-11-17 12:10 ` jiawei
  2021-11-18  2:15   ` Palmer Dabbelt
  2021-11-18  7:01   ` Nelson Chu
  2021-11-17 12:10 ` [PATCH v2 3/3] RISC-V: Add testcases " jiawei
  2 siblings, 2 replies; 8+ messages in thread
From: jiawei @ 2021-11-17 12:10 UTC (permalink / raw)
  To: binutils
  Cc: tariq.kurd, kito.cheng, nelson.chu, jim.wilson.gcc,
	jeremy.bennett, cmuellner, palmer, andrew, philipp.tomsich,
	lazyparser, sinan, shihua, jiawei

Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.

bfd/ChangeLog:

* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
  z*inx extension.

gas/ChangeLog:

* config/tc-riscv.c (riscv_ip): Added register choice for z*inx.

include/ChangeLog:

* opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.

opcodes/ChangeLog:

* riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
  z*inx.
* riscv-opc.c: Reused INSN_CLASS_* for z*inx.

---
 bfd/elfxx-riscv.c      |   9 ++
 gas/config/tc-riscv.c  |   4 +-
 include/opcode/riscv.h |   3 +
 opcodes/riscv-dis.c    |   4 +
 opcodes/riscv-opc.c    | 296 ++++++++++++++++++++---------------------
 5 files changed, 167 insertions(+), 149 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9f03542ab77..6d4107b0557 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2184,6 +2184,15 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_D_AND_C:
       return (riscv_subset_supports (rps, "d")
 	      && riscv_subset_supports (rps, "c"));
+    case INSN_CLASS_F_OR_ZFINX:
+      return (riscv_subset_supports (rps, "f")
+	      || riscv_subset_supports (rps, "zfinx"));
+    case INSN_CLASS_D_OR_ZDINX:
+      return (riscv_subset_supports (rps, "d")
+	      || riscv_subset_supports (rps, "zdinx"));
+    case INSN_CLASS_Q_OR_ZQINX:
+      return (riscv_subset_supports (rps, "q")
+	      || riscv_subset_supports (rps, "zqinx"));
     case INSN_CLASS_ZBA:
       return riscv_subset_supports (rps, "zba");
     case INSN_CLASS_ZBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 8985edf4bfa..fa2c04db555 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2480,7 +2480,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	    case 'T': /* Floating point RS2.  */
 	    case 'U': /* Floating point RS1 and RS2.  */
 	    case 'R': /* Floating point RS3.  */
-	      if (reg_lookup (&asarg, RCLASS_FPR, &regno))
+	      if (reg_lookup (&asarg, (riscv_subset_supports 
+			(&riscv_rps_as, "zfinx") ? 
+			RCLASS_GPR : RCLASS_FPR), &regno))
 		{
 		  char c = *oparg;
 		  if (*asarg == ' ')
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1b5b7cb6ffc..a4125a342e1 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -323,6 +323,9 @@ enum riscv_insn_class
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,
+  INSN_CLASS_F_OR_ZFINX,
+  INSN_CLASS_D_OR_ZDINX,
+  INSN_CLASS_Q_OR_ZQINX,
   INSN_CLASS_ZBA,
   INSN_CLASS_ZBB,
   INSN_CLASS_ZBC,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 86e2e5ab214..6418503de82 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -534,6 +534,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	  xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
 	}
 
+  /* If arch has ZFINX flags, use gpr for disassemble. */
+  if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
+	  riscv_fpr_names = riscv_gpr_names_abi;
+
       for (; op->name; op++)
 	{
 	  /* Does the opcode match?  */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f4df81f4902..57827c1287e 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -517,8 +517,8 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fsrm",       0, INSN_CLASS_F,   "d,s",       MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
 {"fsrmi",      0, INSN_CLASS_F,   "d,Z",       MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
 {"fsrmi",      0, INSN_CLASS_F,   "Z",         MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS },
-{"frflags",    0, INSN_CLASS_F,   "d",         MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
-{"fsflags",    0, INSN_CLASS_F,   "s",         MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS },
+{"frflags",    0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
+{"fsflags",    0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS },
 {"fsflags",    0, INSN_CLASS_F,   "d,s",       MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
 {"fsflagsi",   0, INSN_CLASS_F,   "d,Z",       MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
 {"fsflagsi",   0, INSN_CLASS_F,   "Z",         MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS },
@@ -535,53 +535,53 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fmv.x.s",    0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
 {"fmv.s.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
 {"fmv.s",      0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.s",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.s",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.s",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
-{"fsgnjn.s",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
-{"fsgnjx.s",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
-{"fadd.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
-{"fadd.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
-{"fsub.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
-{"fsub.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
-{"fmul.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
-{"fmul.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
-{"fdiv.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
-{"fdiv.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
-{"fsqrt.s",    0, INSN_CLASS_F,   "D,S",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
-{"fsqrt.s",    0, INSN_CLASS_F,   "D,S,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
-{"fmin.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
-{"fmax.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
-{"fmadd.s",    0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
-{"fmadd.s",    0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
-{"fnmadd.s",   0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
-{"fnmadd.s",   0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
-{"fmsub.s",    0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
-{"fmsub.s",    0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
-{"fnmsub.s",   0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
-{"fnmsub.s",   0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
-{"fcvt.w.s",   0, INSN_CLASS_F,   "d,S",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
-{"fcvt.w.s",   0, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
-{"fcvt.wu.s",  0, INSN_CLASS_F,   "d,S",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.s",  0, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
-{"fcvt.s.w",   0, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
-{"fcvt.s.w",   0, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
-{"fcvt.s.wu",  0, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
-{"fcvt.s.wu",  0, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
-{"fclass.s",   0, INSN_CLASS_F,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
-{"feq.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
-{"flt.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
-{"fle.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
-{"fgt.s",      0, INSN_CLASS_F,   "d,T,S",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
-{"fge.s",      0, INSN_CLASS_F,   "d,T,S",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
-{"fcvt.l.s",  64, INSN_CLASS_F,   "d,S",       MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
-{"fcvt.l.s",  64, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
-{"fcvt.lu.s", 64, INSN_CLASS_F,   "d,S",       MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.s", 64, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
-{"fcvt.s.l",  64, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
-{"fcvt.s.l",  64, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
-{"fcvt.s.lu", 64, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
-{"fcvt.s.lu", 64, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
+{"fneg.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,U",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,U",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
+{"fsgnjn.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
+{"fsgnjx.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
+{"fadd.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
+{"fadd.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
+{"fsub.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
+{"fsub.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
+{"fmul.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
+{"fmul.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
+{"fdiv.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
+{"fdiv.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
+{"fsqrt.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
+{"fsqrt.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
+{"fmin.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
+{"fmax.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
+{"fmadd.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
+{"fmadd.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
+{"fnmadd.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
+{"fnmadd.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
+{"fmsub.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
+{"fmsub.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
+{"fnmsub.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
+{"fnmsub.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
+{"fcvt.w.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
+{"fcvt.w.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
+{"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
+{"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
+{"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
+{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
+{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
+{"fclass.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
+{"feq.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
+{"flt.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
+{"fle.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
+{"fgt.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,T,S",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
+{"fge.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,T,S",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
+{"fcvt.l.s",  64, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
+{"fcvt.l.s",  64, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
+{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
+{"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
+{"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
+{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
+{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
 
 /* Double-precision floating-point instruction subset.  */
 {"fld",        0, INSN_CLASS_D_AND_C, "D,Cn(Cc)",  MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
@@ -593,56 +593,56 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fsd",        0, INSN_CLASS_D,   "T,q(s)",    MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
 {"fsd",        0, INSN_CLASS_D,   "T,A,s",     0, (int) M_FSD, match_never, INSN_MACRO },
 {"fmv.d",      0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.d",     0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.d",     0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.d",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
-{"fsgnjn.d",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
-{"fsgnjx.d",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
-{"fadd.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
-{"fadd.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
-{"fsub.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
-{"fsub.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
-{"fmul.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
-{"fmul.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
-{"fdiv.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
-{"fdiv.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
-{"fsqrt.d",    0, INSN_CLASS_D,   "D,S",       MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
-{"fsqrt.d",    0, INSN_CLASS_D,   "D,S,m",     MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
-{"fmin.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
-{"fmax.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
-{"fmadd.d",    0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
-{"fmadd.d",    0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
-{"fnmadd.d",   0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
-{"fnmadd.d",   0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
-{"fmsub.d",    0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
-{"fmsub.d",    0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
-{"fnmsub.d",   0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
-{"fnmsub.d",   0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
-{"fcvt.w.d",   0, INSN_CLASS_D,   "d,S",       MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
-{"fcvt.w.d",   0, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
-{"fcvt.wu.d",  0, INSN_CLASS_D,   "d,S",       MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.d",  0, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
-{"fcvt.d.w",   0, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
-{"fcvt.d.wu",  0, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.d.s",   0, INSN_CLASS_D,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
-{"fcvt.s.d",   0, INSN_CLASS_D,   "D,S",       MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
-{"fcvt.s.d",   0, INSN_CLASS_D,   "D,S,m",     MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
-{"fclass.d",   0, INSN_CLASS_D,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
-{"feq.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
-{"flt.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
-{"fle.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
-{"fgt.d",      0, INSN_CLASS_D,   "d,T,S",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
-{"fge.d",      0, INSN_CLASS_D,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
+{"fneg.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,U",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,U",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
+{"fsgnjn.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
+{"fsgnjx.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
+{"fadd.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
+{"fadd.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
+{"fsub.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
+{"fsub.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
+{"fmul.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
+{"fmul.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
+{"fdiv.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
+{"fdiv.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
+{"fsqrt.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
+{"fsqrt.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,m",     MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
+{"fmin.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
+{"fmax.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
+{"fmadd.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
+{"fmadd.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
+{"fnmadd.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
+{"fnmadd.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
+{"fmsub.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
+{"fmsub.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
+{"fnmsub.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
+{"fnmsub.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
+{"fcvt.w.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
+{"fcvt.w.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
+{"fcvt.wu.d",  0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.d",  0, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
+{"fcvt.d.w",   0, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
+{"fcvt.d.wu",  0, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.d.s",   0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
+{"fcvt.s.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
+{"fcvt.s.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,m",     MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
+{"fclass.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
+{"feq.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
+{"flt.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
+{"fle.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
+{"fgt.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,T,S",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
+{"fge.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
 {"fmv.x.d",   64, INSN_CLASS_D,   "d,S",       MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
 {"fmv.d.x",   64, INSN_CLASS_D,   "D,s",       MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
-{"fcvt.l.d",  64, INSN_CLASS_D,   "d,S",       MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
-{"fcvt.l.d",  64, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
-{"fcvt.lu.d", 64, INSN_CLASS_D,   "d,S",       MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.d", 64, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
-{"fcvt.d.l",  64, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
-{"fcvt.d.l",  64, INSN_CLASS_D,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
-{"fcvt.d.lu", 64, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
-{"fcvt.d.lu", 64, INSN_CLASS_D,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
+{"fcvt.l.d",  64, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
+{"fcvt.l.d",  64, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
+{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
+{"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
+{"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
+{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
+{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
 
 /* Quad-precision floating-point instruction subset.  */
 {"flq",        0, INSN_CLASS_Q,   "D,o(s)",    MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
@@ -650,59 +650,59 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fsq",        0, INSN_CLASS_Q,   "T,q(s)",    MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
 {"fsq",        0, INSN_CLASS_Q,   "T,A,s",     0, (int) M_FSQ, match_never, INSN_MACRO },
 {"fmv.q",      0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.q",     0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.q",     0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.q",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
-{"fsgnjn.q",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
-{"fsgnjx.q",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
-{"fadd.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
-{"fadd.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
-{"fsub.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
-{"fsub.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
-{"fmul.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
-{"fmul.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
-{"fdiv.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
-{"fdiv.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
-{"fsqrt.q",    0, INSN_CLASS_Q,   "D,S",       MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
-{"fsqrt.q",    0, INSN_CLASS_Q,   "D,S,m",     MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
-{"fmin.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
-{"fmax.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
-{"fmadd.q",    0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
-{"fmadd.q",    0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
-{"fnmadd.q",   0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
-{"fnmadd.q",   0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
-{"fmsub.q",    0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
-{"fmsub.q",    0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
-{"fnmsub.q",   0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
-{"fnmsub.q",   0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
-{"fcvt.w.q",   0, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.w.q",   0, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
-{"fcvt.wu.q",  0, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.q",  0, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
-{"fcvt.q.w",   0, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
-{"fcvt.q.wu",  0, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.q.s",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
-{"fcvt.q.d",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
-{"fcvt.s.q",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.s.q",   0, INSN_CLASS_Q,   "D,S,m",     MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
-{"fcvt.d.q",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.d.q",   0, INSN_CLASS_Q,   "D,S,m",     MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
-{"fclass.q",   0, INSN_CLASS_Q,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
-{"feq.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
-{"flt.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
-{"fle.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
-{"fgt.q",      0, INSN_CLASS_Q,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
-{"fge.q",      0, INSN_CLASS_Q,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
+{"fneg.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
+{"fsgnjn.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
+{"fsgnjx.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
+{"fadd.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
+{"fadd.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
+{"fsub.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
+{"fsub.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
+{"fmul.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
+{"fmul.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
+{"fdiv.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
+{"fdiv.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
+{"fsqrt.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
+{"fsqrt.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
+{"fmin.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
+{"fmax.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
+{"fmadd.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
+{"fmadd.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
+{"fnmadd.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
+{"fnmadd.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
+{"fmsub.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
+{"fmsub.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
+{"fnmsub.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
+{"fnmsub.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
+{"fcvt.w.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.w.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
+{"fcvt.wu.q",  0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.q",  0, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
+{"fcvt.q.w",   0, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
+{"fcvt.q.wu",  0, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.q.s",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
+{"fcvt.q.d",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
+{"fcvt.s.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.s.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
+{"fcvt.d.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.d.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
+{"fclass.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
+{"feq.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
+{"flt.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
+{"fle.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
+{"fgt.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
+{"fge.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
 {"fmv.x.q",   64, INSN_CLASS_Q,   "d,S",       MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
 {"fmv.q.x",   64, INSN_CLASS_Q,   "D,s",       MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
-{"fcvt.l.q",  64, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.l.q",  64, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
-{"fcvt.lu.q", 64, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.q", 64, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
-{"fcvt.q.l",  64, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
-{"fcvt.q.l",  64, INSN_CLASS_Q,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
+{"fcvt.l.q",  64, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.l.q",  64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
+{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
+{"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
+{"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
+{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
+{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
 
 /* Compressed instructions.  */
 {"c.unimp",    0, INSN_CLASS_C,   "",          0, 0xffffU,  match_opcode, 0 },
-- 
2.25.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2 3/3] RISC-V: Add testcases  for z[fdq]inx
  2021-11-17 12:10 [PATCH v2 0/3] RISC-V: Zfinx extension support jiawei
  2021-11-17 12:10 ` [PATCH v2 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
  2021-11-17 12:10 ` [PATCH v2 2/3] RISC-V: Add instructions and operand set " jiawei
@ 2021-11-17 12:10 ` jiawei
  2021-11-18  2:15   ` Palmer Dabbelt
  2 siblings, 1 reply; 8+ messages in thread
From: jiawei @ 2021-11-17 12:10 UTC (permalink / raw)
  To: binutils
  Cc: tariq.kurd, kito.cheng, nelson.chu, jim.wilson.gcc,
	jeremy.bennett, cmuellner, palmer, andrew, philipp.tomsich,
	lazyparser, sinan, shihua, jiawei

Use gpr when the zfinx enable, the testcases contain float
instructions that reuse by z[fdq]inx.

gas/ChangeLog:

* testsuite/gas/riscv/zdinx.d: New test.
* testsuite/gas/riscv/zdinx.s: New test.
* testsuite/gas/riscv/zfinx.d: New test.
* testsuite/gas/riscv/zfinx.s: New test.
* testsuite/gas/riscv/zqinx.d: New test.
* testsuite/gas/riscv/zqinx.s: New test.

---
 gas/testsuite/gas/riscv/zdinx.d | 42 +++++++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zdinx.s | 34 +++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zfinx.d | 40 ++++++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zfinx.s | 32 ++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zqinx.d | 44 +++++++++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zqinx.s | 36 +++++++++++++++++++++++++++
 6 files changed, 228 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zdinx.d
 create mode 100644 gas/testsuite/gas/riscv/zdinx.s
 create mode 100644 gas/testsuite/gas/riscv/zfinx.d
 create mode 100644 gas/testsuite/gas/riscv/zfinx.s
 create mode 100644 gas/testsuite/gas/riscv/zqinx.d
 create mode 100644 gas/testsuite/gas/riscv/zqinx.s

diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d
new file mode 100644
index 00000000000..85c270fe913
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx.d
@@ -0,0 +1,42 @@
+#as: -march=rv64ima_zdinx
+#source: zdinx.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c5f553[ 	]+fadd.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5f553[ 	]+fsub.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+12c5f553[ 	]+fmul.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+1ac5f553[ 	]+fdiv.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+5a057553[ 	]+fsqrt.d[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+2ac58553[ 	]+fmin.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+2ac59553[ 	]+fmax.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6ac5f543[ 	]+fmadd.d[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+6ac5f54f[ 	]+fnmadd.d[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+6ac5f547[ 	]+fmsub.d[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+6ac5f54b[ 	]+fnmsub.d[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+c205f553[ 	]+fcvt.w.d[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c215f553[ 	]+fcvt.wu.d[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c225f553[ 	]+fcvt.l.d[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c235f553[ 	]+fcvt.lu.d[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+4015f553[ 	]+fcvt.s.d[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+42058553[ 	]+fcvt.d.s[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d2058553[ 	]+fcvt.d.w[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d2158553[ 	]+fcvt.d.wu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d225f553[ 	]+fcvt.d.l[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d235f553[ 	]+fcvt.d.lu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+22c58553[ 	]+fsgnj.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+22c59553[ 	]+fsgnjn.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+22c5a553[ 	]+fsgnjx.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c5a553[ 	]+feq.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c59553[ 	]+flt.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c58553[ 	]+fle.d[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a2b61553[ 	]+flt.d[ 	]+a0,a2,a1
+[ 	]+[0-9a-f]+:[ 	]+a2b60553[ 	]+fle.d[ 	]+a0,a2,a1
+[ 	]+[0-9a-f]+:[ 	]+22a51553[ 	]+fneg.d[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+22a52553[ 	]+fabs.d[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+e2059553[ 	]+fclass.d[ 	]+a0,a1
+
diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s
new file mode 100644
index 00000000000..e1bf73cf4bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx.s
@@ -0,0 +1,34 @@
+target:
+	fadd.d	a0, a1, a2
+	fsub.d	a0, a1, a2
+	fmul.d	a0, a1, a2
+	fdiv.d	a0, a1, a2
+	fsqrt.d	a0, a0
+	fmin.d	a0, a1, a2
+	fmax.d	a0, a1, a2
+	fmadd.d	a0, a1, a2, a3
+	fnmadd.d	a0, a1, a2, a3
+	fmsub.d	a0, a1, a2, a3
+	fnmsub.d	a0, a1, a2, a3
+	fcvt.w.d	a0, a1
+	fcvt.wu.d	a0, a1
+	fcvt.l.d	a0, a1
+	fcvt.lu.d	a0, a1
+	fcvt.s.d	a0, a1
+	fcvt.d.s	a0, a1
+	fcvt.d.w	a0, a1
+	fcvt.d.wu	a0, a1
+	fcvt.d.l	a0, a1
+	fcvt.d.lu	a0, a1
+	fsgnj.d	a0, a1, a2
+	fsgnjn.d	a0, a1, a2
+	fsgnjx.d	a0, a1, a2
+	feq.d	a0, a1, a2
+	flt.d	a0, a1, a2
+	fle.d	a0, a1, a2
+	fgt.d	a0, a1, a2
+	fge.d	a0, a1, a2
+	fneg.d  a0, a0
+	fabs.d	a0, a0
+	fclass.d	a0, a1
+
diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d
new file mode 100644
index 00000000000..7aebe9d5e3e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfinx.d
@@ -0,0 +1,40 @@
+#as: -march=rv64ima_zfinx
+#source: zfinx.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+00c5f553[ 	]+fadd.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+08c5f553[ 	]+fsub.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+10c5f553[ 	]+fmul.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+18c5f553[ 	]+fdiv.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+58057553[ 	]+fsqrt.s[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+28c58553[ 	]+fmin.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+28c59553[ 	]+fmax.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+68c5f543[ 	]+fmadd.s[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+68c5f54f[ 	]+fnmadd.s[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+68c5f547[ 	]+fmsub.s[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+68c5f54b[ 	]+fnmsub.s[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+c005f553[ 	]+fcvt.w.s[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c015f553[ 	]+fcvt.wu.s[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c025f553[ 	]+fcvt.l.s[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c035f553[ 	]+fcvt.lu.s[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d005f553[ 	]+fcvt.s.w[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d015f553[ 	]+fcvt.s.wu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d025f553[ 	]+fcvt.s.l[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d035f553[ 	]+fcvt.s.lu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+20c58553[ 	]+fsgnj.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+20c59553[ 	]+fsgnjn.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+20c5a553[ 	]+fsgnjx.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a0c5a553[ 	]+feq.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a0c59553[ 	]+flt.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a0c58553[ 	]+fle.s[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a0b61553[ 	]+flt.s[ 	]+a0,a2,a1
+[ 	]+[0-9a-f]+:[ 	]+a0b60553[ 	]+fle.s[ 	]+a0,a2,a1
+[ 	]+[0-9a-f]+:[ 	]+20a51553[ 	]+fneg.s[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+20a52553[ 	]+fabs.s[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+e0059553[ 	]+fclass.s[ 	]+a0,a1
+
diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s
new file mode 100644
index 00000000000..aa5cd386536
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfinx.s
@@ -0,0 +1,32 @@
+target:
+	fadd.s	a0, a1, a2
+	fsub.s	a0, a1, a2
+	fmul.s	a0, a1, a2
+	fdiv.s	a0, a1, a2
+	fsqrt.s	a0, a0
+	fmin.s	a0, a1, a2
+	fmax.s	a0, a1, a2
+	fmadd.s	a0, a1, a2, a3
+	fnmadd.s	a0, a1, a2, a3
+	fmsub.s	a0, a1, a2, a3
+	fnmsub.s	a0, a1, a2, a3
+	fcvt.w.s	a0, a1
+	fcvt.wu.s	a0, a1
+	fcvt.l.s	a0, a1
+	fcvt.lu.s	a0, a1
+	fcvt.s.w	a0, a1
+	fcvt.s.wu	a0, a1
+	fcvt.s.l	a0, a1
+	fcvt.s.lu	a0, a1
+	fsgnj.s	a0, a1, a2
+	fsgnjn.s	a0, a1, a2
+	fsgnjx.s	a0, a1, a2
+	feq.s	a0, a1, a2
+	flt.s	a0, a1, a2
+	fle.s	a0, a1, a2
+	fgt.s	a0, a1, a2
+	fge.s	a0, a1, a2
+	fneg.s  a0, a0
+	fabs.s	a0, a0
+	fclass.s	a0, a1
+
diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d
new file mode 100644
index 00000000000..5f5ab7c75cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx.d
@@ -0,0 +1,44 @@
+#as: -march=rv64ima_zqinx
+#source: zqinx.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06c5f553[ 	]+fadd.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ec5f553[ 	]+fsub.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+16c5f553[ 	]+fmul.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+1ec5f553[ 	]+fdiv.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+5e057553[ 	]+fsqrt.q[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+2ec58553[ 	]+fmin.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+2ec59553[ 	]+fmax.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6ec5f543[ 	]+fmadd.q[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+6ec5f54f[ 	]+fnmadd.q[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+6ec5f547[ 	]+fmsub.q[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+6ec5f54b[ 	]+fnmsub.q[ 	]+a0,a1,a2,a3
+[ 	]+[0-9a-f]+:[ 	]+c605f553[ 	]+fcvt.w.q[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c615f553[ 	]+fcvt.wu.q[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c625f553[ 	]+fcvt.l.q[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+c635f553[ 	]+fcvt.lu.q[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+4035f553[ 	]+fcvt.s.q[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+4235f553[ 	]+fcvt.d.q[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+46058553[ 	]+fcvt.q.s[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+46158553[ 	]+fcvt.q.d[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d6058553[ 	]+fcvt.q.w[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d6158553[ 	]+fcvt.q.wu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d625f553[ 	]+fcvt.q.l[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d635f553[ 	]+fcvt.q.lu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+26c58553[ 	]+fsgnj.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+26c59553[ 	]+fsgnjn.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+26c5a553[ 	]+fsgnjx.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c5a553[ 	]+feq.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c59553[ 	]+flt.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c58553[ 	]+fle.q[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+a6b61553[ 	]+flt.q[ 	]+a0,a2,a1
+[ 	]+[0-9a-f]+:[ 	]+a6b60553[ 	]+fle.q[ 	]+a0,a2,a1
+[ 	]+[0-9a-f]+:[ 	]+26a51553[ 	]+fneg.q[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+26a52553[ 	]+fabs.q[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+e6059553[ 	]+fclass.q[ 	]+a0,a1
+
diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s
new file mode 100644
index 00000000000..797bb1f9ed7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx.s
@@ -0,0 +1,36 @@
+target:
+	fadd.q	a0, a1, a2
+	fsub.q	a0, a1, a2
+	fmul.q	a0, a1, a2
+	fdiv.q	a0, a1, a2
+	fsqrt.q	a0, a0
+	fmin.q	a0, a1, a2
+	fmax.q	a0, a1, a2
+	fmadd.q	a0, a1, a2, a3
+	fnmadd.q	a0, a1, a2, a3
+	fmsub.q	a0, a1, a2, a3
+	fnmsub.q	a0, a1, a2, a3
+	fcvt.w.q	a0, a1
+	fcvt.wu.q	a0, a1
+	fcvt.l.q	a0, a1
+	fcvt.lu.q	a0, a1
+	fcvt.s.q	a0, a1
+	fcvt.d.q	a0, a1
+	fcvt.q.s	a0, a1
+	fcvt.q.d	a0, a1
+	fcvt.q.w	a0, a1
+	fcvt.q.wu	a0, a1
+	fcvt.q.l	a0, a1
+	fcvt.q.lu	a0, a1
+	fsgnj.q	a0, a1, a2
+	fsgnjn.q	a0, a1, a2
+	fsgnjx.q	a0, a1, a2
+	feq.q	a0, a1, a2
+	flt.q	a0, a1, a2
+	fle.q	a0, a1, a2
+	fgt.q	a0, a1, a2
+	fge.q	a0, a1, a2
+	fneg.q  a0, a0
+	fabs.q	a0, a0
+	fclass.q	a0, a1
+
-- 
2.25.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 1/3] RISC-V: Add mininal support for z[fdq]inx
  2021-11-17 12:10 ` [PATCH v2 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
@ 2021-11-18  2:15   ` Palmer Dabbelt
  0 siblings, 0 replies; 8+ messages in thread
From: Palmer Dabbelt @ 2021-11-18  2:15 UTC (permalink / raw)
  To: jiawei
  Cc: binutils, tariq.kurd, kito.cheng, Nelson Chu, Jim Wilson,
	jeremy.bennett, cmuellner, Andrew Waterman, philipp.tomsich,
	lazyparser, sinan, shihua, jiawei

On Wed, 17 Nov 2021 04:10:06 PST (-0800), jiawei@iscas.ac.cn wrote:
> Minimal support for zfinx, zdinx, zqinx. Like f/d/q, the zqinx
> imply zdinx and zdinx imply zfinx, where zfinx are not compatible
> with f/d/q.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_implicit_subsets): Added implicit rules
> for z*inx extensions.
> (riscv_supported_std_z_ext): Added entries for z*inx.
> (riscv_parse_check_conflicts): Added conflict check for z*inx.
>
> ---
>  bfd/elfxx-riscv.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index e2fb4003380..9f03542ab77 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1075,6 +1075,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
>    {"q", "d",		check_implicit_always},
>    {"d", "f",		check_implicit_always},
>    {"f", "zicsr",	check_implicit_always},
> +  {"zqinx", "zdinx",	check_implicit_always},
> +  {"zdinx", "zfinx",	check_implicit_always},
>    {"zk", "zkn",		check_implicit_always},
>    {"zk", "zkr",		check_implicit_always},
>    {"zk", "zkt",		check_implicit_always},
> @@ -1157,6 +1159,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
>    {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
>    {"zifencei",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
>    {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
> +  {"zfinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
> +  {"zdinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
> +  {"zqinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
>    {"zbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
>    {"zba",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
>    {"zbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
> @@ -1854,6 +1859,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
>          (_("rv32e does not support the `f' extension"));
>        no_conflict = false;
>      }
> +  if (riscv_lookup_subset (rps->subset_list, "zfinx", &subset)
> +      && (riscv_lookup_subset (rps->subset_list, "f", &subset)))
> +    {
> +      rps->error_handler
> +        (_("`zfinx' is conflict with the `f/d/q' extension"));
> +      no_conflict = false;
> +    }
>    return no_conflict;
>  }

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 2/3] RISC-V: Add instructions and operand set for z[fdq]inx
  2021-11-17 12:10 ` [PATCH v2 2/3] RISC-V: Add instructions and operand set " jiawei
@ 2021-11-18  2:15   ` Palmer Dabbelt
  2021-11-18  7:01   ` Nelson Chu
  1 sibling, 0 replies; 8+ messages in thread
From: Palmer Dabbelt @ 2021-11-18  2:15 UTC (permalink / raw)
  To: jiawei
  Cc: binutils, tariq.kurd, kito.cheng, Nelson Chu, Jim Wilson,
	jeremy.bennett, cmuellner, Andrew Waterman, philipp.tomsich,
	lazyparser, sinan, shihua, jiawei

On Wed, 17 Nov 2021 04:10:07 PST (-0800), jiawei@iscas.ac.cn wrote:
> Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
> verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Added support for
>   z*inx extension.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (riscv_ip): Added register choice for z*inx.
>
> include/ChangeLog:
>
> * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.
>
> opcodes/ChangeLog:
>
> * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
>   z*inx.
> * riscv-opc.c: Reused INSN_CLASS_* for z*inx.
>
> ---
>  bfd/elfxx-riscv.c      |   9 ++
>  gas/config/tc-riscv.c  |   4 +-
>  include/opcode/riscv.h |   3 +
>  opcodes/riscv-dis.c    |   4 +
>  opcodes/riscv-opc.c    | 296 ++++++++++++++++++++---------------------
>  5 files changed, 167 insertions(+), 149 deletions(-)

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 3/3] RISC-V: Add testcases  for z[fdq]inx
  2021-11-17 12:10 ` [PATCH v2 3/3] RISC-V: Add testcases " jiawei
@ 2021-11-18  2:15   ` Palmer Dabbelt
  0 siblings, 0 replies; 8+ messages in thread
From: Palmer Dabbelt @ 2021-11-18  2:15 UTC (permalink / raw)
  To: jiawei
  Cc: binutils, tariq.kurd, kito.cheng, Nelson Chu, Jim Wilson,
	jeremy.bennett, cmuellner, Andrew Waterman, philipp.tomsich,
	lazyparser, sinan, shihua, jiawei

On Wed, 17 Nov 2021 04:10:08 PST (-0800), jiawei@iscas.ac.cn wrote:
> Use gpr when the zfinx enable, the testcases contain float
> instructions that reuse by z[fdq]inx.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zdinx.d: New test.
> * testsuite/gas/riscv/zdinx.s: New test.
> * testsuite/gas/riscv/zfinx.d: New test.
> * testsuite/gas/riscv/zfinx.s: New test.
> * testsuite/gas/riscv/zqinx.d: New test.
> * testsuite/gas/riscv/zqinx.s: New test.
>
> ---
>  gas/testsuite/gas/riscv/zdinx.d | 42 +++++++++++++++++++++++++++++++
>  gas/testsuite/gas/riscv/zdinx.s | 34 +++++++++++++++++++++++++
>  gas/testsuite/gas/riscv/zfinx.d | 40 ++++++++++++++++++++++++++++++
>  gas/testsuite/gas/riscv/zfinx.s | 32 ++++++++++++++++++++++++
>  gas/testsuite/gas/riscv/zqinx.d | 44 +++++++++++++++++++++++++++++++++
>  gas/testsuite/gas/riscv/zqinx.s | 36 +++++++++++++++++++++++++++
>  6 files changed, 228 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/zdinx.d
>  create mode 100644 gas/testsuite/gas/riscv/zdinx.s
>  create mode 100644 gas/testsuite/gas/riscv/zfinx.d
>  create mode 100644 gas/testsuite/gas/riscv/zfinx.s
>  create mode 100644 gas/testsuite/gas/riscv/zqinx.d
>  create mode 100644 gas/testsuite/gas/riscv/zqinx.s

These generally look good, but we should have some negative tests too -- 
ie, these should fail on F, and things like "fadd.s a0, a0, a0" should 
fail on Zfinx.  IMO that doesn't need to block the patch set, though, as 
these do work now.

> diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d
> new file mode 100644
> index 00000000000..85c270fe913
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zdinx.d
> @@ -0,0 +1,42 @@
> +#as: -march=rv64ima_zdinx
> +#source: zdinx.s
> +#objdump: -dr
> +
> +.*:[ 	]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ 	]+[0-9a-f]+:[ 	]+02c5f553[ 	]+fadd.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+0ac5f553[ 	]+fsub.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+12c5f553[ 	]+fmul.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+1ac5f553[ 	]+fdiv.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+5a057553[ 	]+fsqrt.d[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+2ac58553[ 	]+fmin.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+2ac59553[ 	]+fmax.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+6ac5f543[ 	]+fmadd.d[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+6ac5f54f[ 	]+fnmadd.d[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+6ac5f547[ 	]+fmsub.d[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+6ac5f54b[ 	]+fnmsub.d[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+c205f553[ 	]+fcvt.w.d[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c215f553[ 	]+fcvt.wu.d[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c225f553[ 	]+fcvt.l.d[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c235f553[ 	]+fcvt.lu.d[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+4015f553[ 	]+fcvt.s.d[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+42058553[ 	]+fcvt.d.s[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d2058553[ 	]+fcvt.d.w[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d2158553[ 	]+fcvt.d.wu[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d225f553[ 	]+fcvt.d.l[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d235f553[ 	]+fcvt.d.lu[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+22c58553[ 	]+fsgnj.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+22c59553[ 	]+fsgnjn.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+22c5a553[ 	]+fsgnjx.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a2c5a553[ 	]+feq.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a2c59553[ 	]+flt.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a2c58553[ 	]+fle.d[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a2b61553[ 	]+flt.d[ 	]+a0,a2,a1
> +[ 	]+[0-9a-f]+:[ 	]+a2b60553[ 	]+fle.d[ 	]+a0,a2,a1
> +[ 	]+[0-9a-f]+:[ 	]+22a51553[ 	]+fneg.d[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+22a52553[ 	]+fabs.d[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+e2059553[ 	]+fclass.d[ 	]+a0,a1
> +
> diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s
> new file mode 100644
> index 00000000000..e1bf73cf4bf
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zdinx.s
> @@ -0,0 +1,34 @@
> +target:
> +	fadd.d	a0, a1, a2
> +	fsub.d	a0, a1, a2
> +	fmul.d	a0, a1, a2
> +	fdiv.d	a0, a1, a2
> +	fsqrt.d	a0, a0
> +	fmin.d	a0, a1, a2
> +	fmax.d	a0, a1, a2
> +	fmadd.d	a0, a1, a2, a3
> +	fnmadd.d	a0, a1, a2, a3
> +	fmsub.d	a0, a1, a2, a3
> +	fnmsub.d	a0, a1, a2, a3
> +	fcvt.w.d	a0, a1
> +	fcvt.wu.d	a0, a1
> +	fcvt.l.d	a0, a1
> +	fcvt.lu.d	a0, a1
> +	fcvt.s.d	a0, a1
> +	fcvt.d.s	a0, a1
> +	fcvt.d.w	a0, a1
> +	fcvt.d.wu	a0, a1
> +	fcvt.d.l	a0, a1
> +	fcvt.d.lu	a0, a1
> +	fsgnj.d	a0, a1, a2
> +	fsgnjn.d	a0, a1, a2
> +	fsgnjx.d	a0, a1, a2
> +	feq.d	a0, a1, a2
> +	flt.d	a0, a1, a2
> +	fle.d	a0, a1, a2
> +	fgt.d	a0, a1, a2
> +	fge.d	a0, a1, a2
> +	fneg.d  a0, a0
> +	fabs.d	a0, a0
> +	fclass.d	a0, a1
> +
> diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d
> new file mode 100644
> index 00000000000..7aebe9d5e3e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfinx.d
> @@ -0,0 +1,40 @@
> +#as: -march=rv64ima_zfinx
> +#source: zfinx.s
> +#objdump: -dr
> +
> +.*:[ 	]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ 	]+[0-9a-f]+:[ 	]+00c5f553[ 	]+fadd.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+08c5f553[ 	]+fsub.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+10c5f553[ 	]+fmul.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+18c5f553[ 	]+fdiv.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+58057553[ 	]+fsqrt.s[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+28c58553[ 	]+fmin.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+28c59553[ 	]+fmax.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+68c5f543[ 	]+fmadd.s[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+68c5f54f[ 	]+fnmadd.s[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+68c5f547[ 	]+fmsub.s[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+68c5f54b[ 	]+fnmsub.s[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+c005f553[ 	]+fcvt.w.s[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c015f553[ 	]+fcvt.wu.s[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c025f553[ 	]+fcvt.l.s[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c035f553[ 	]+fcvt.lu.s[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d005f553[ 	]+fcvt.s.w[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d015f553[ 	]+fcvt.s.wu[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d025f553[ 	]+fcvt.s.l[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d035f553[ 	]+fcvt.s.lu[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+20c58553[ 	]+fsgnj.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+20c59553[ 	]+fsgnjn.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+20c5a553[ 	]+fsgnjx.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a0c5a553[ 	]+feq.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a0c59553[ 	]+flt.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a0c58553[ 	]+fle.s[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a0b61553[ 	]+flt.s[ 	]+a0,a2,a1
> +[ 	]+[0-9a-f]+:[ 	]+a0b60553[ 	]+fle.s[ 	]+a0,a2,a1
> +[ 	]+[0-9a-f]+:[ 	]+20a51553[ 	]+fneg.s[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+20a52553[ 	]+fabs.s[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+e0059553[ 	]+fclass.s[ 	]+a0,a1
> +
> diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s
> new file mode 100644
> index 00000000000..aa5cd386536
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfinx.s
> @@ -0,0 +1,32 @@
> +target:
> +	fadd.s	a0, a1, a2
> +	fsub.s	a0, a1, a2
> +	fmul.s	a0, a1, a2
> +	fdiv.s	a0, a1, a2
> +	fsqrt.s	a0, a0
> +	fmin.s	a0, a1, a2
> +	fmax.s	a0, a1, a2
> +	fmadd.s	a0, a1, a2, a3
> +	fnmadd.s	a0, a1, a2, a3
> +	fmsub.s	a0, a1, a2, a3
> +	fnmsub.s	a0, a1, a2, a3
> +	fcvt.w.s	a0, a1
> +	fcvt.wu.s	a0, a1
> +	fcvt.l.s	a0, a1
> +	fcvt.lu.s	a0, a1
> +	fcvt.s.w	a0, a1
> +	fcvt.s.wu	a0, a1
> +	fcvt.s.l	a0, a1
> +	fcvt.s.lu	a0, a1
> +	fsgnj.s	a0, a1, a2
> +	fsgnjn.s	a0, a1, a2
> +	fsgnjx.s	a0, a1, a2
> +	feq.s	a0, a1, a2
> +	flt.s	a0, a1, a2
> +	fle.s	a0, a1, a2
> +	fgt.s	a0, a1, a2
> +	fge.s	a0, a1, a2
> +	fneg.s  a0, a0
> +	fabs.s	a0, a0
> +	fclass.s	a0, a1
> +
> diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d
> new file mode 100644
> index 00000000000..5f5ab7c75cb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx.d
> @@ -0,0 +1,44 @@
> +#as: -march=rv64ima_zqinx
> +#source: zqinx.s
> +#objdump: -dr
> +
> +.*:[ 	]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ 	]+[0-9a-f]+:[ 	]+06c5f553[ 	]+fadd.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+0ec5f553[ 	]+fsub.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+16c5f553[ 	]+fmul.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+1ec5f553[ 	]+fdiv.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+5e057553[ 	]+fsqrt.q[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+2ec58553[ 	]+fmin.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+2ec59553[ 	]+fmax.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+6ec5f543[ 	]+fmadd.q[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+6ec5f54f[ 	]+fnmadd.q[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+6ec5f547[ 	]+fmsub.q[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+6ec5f54b[ 	]+fnmsub.q[ 	]+a0,a1,a2,a3
> +[ 	]+[0-9a-f]+:[ 	]+c605f553[ 	]+fcvt.w.q[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c615f553[ 	]+fcvt.wu.q[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c625f553[ 	]+fcvt.l.q[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+c635f553[ 	]+fcvt.lu.q[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+4035f553[ 	]+fcvt.s.q[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+4235f553[ 	]+fcvt.d.q[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+46058553[ 	]+fcvt.q.s[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+46158553[ 	]+fcvt.q.d[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d6058553[ 	]+fcvt.q.w[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d6158553[ 	]+fcvt.q.wu[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d625f553[ 	]+fcvt.q.l[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d635f553[ 	]+fcvt.q.lu[ 	]+a0,a1
> +[ 	]+[0-9a-f]+:[ 	]+26c58553[ 	]+fsgnj.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+26c59553[ 	]+fsgnjn.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+26c5a553[ 	]+fsgnjx.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a6c5a553[ 	]+feq.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a6c59553[ 	]+flt.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a6c58553[ 	]+fle.q[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+a6b61553[ 	]+flt.q[ 	]+a0,a2,a1
> +[ 	]+[0-9a-f]+:[ 	]+a6b60553[ 	]+fle.q[ 	]+a0,a2,a1
> +[ 	]+[0-9a-f]+:[ 	]+26a51553[ 	]+fneg.q[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+26a52553[ 	]+fabs.q[ 	]+a0,a0
> +[ 	]+[0-9a-f]+:[ 	]+e6059553[ 	]+fclass.q[ 	]+a0,a1
> +
> diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s
> new file mode 100644
> index 00000000000..797bb1f9ed7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx.s
> @@ -0,0 +1,36 @@
> +target:
> +	fadd.q	a0, a1, a2
> +	fsub.q	a0, a1, a2
> +	fmul.q	a0, a1, a2
> +	fdiv.q	a0, a1, a2
> +	fsqrt.q	a0, a0
> +	fmin.q	a0, a1, a2
> +	fmax.q	a0, a1, a2
> +	fmadd.q	a0, a1, a2, a3
> +	fnmadd.q	a0, a1, a2, a3
> +	fmsub.q	a0, a1, a2, a3
> +	fnmsub.q	a0, a1, a2, a3
> +	fcvt.w.q	a0, a1
> +	fcvt.wu.q	a0, a1
> +	fcvt.l.q	a0, a1
> +	fcvt.lu.q	a0, a1
> +	fcvt.s.q	a0, a1
> +	fcvt.d.q	a0, a1
> +	fcvt.q.s	a0, a1
> +	fcvt.q.d	a0, a1
> +	fcvt.q.w	a0, a1
> +	fcvt.q.wu	a0, a1
> +	fcvt.q.l	a0, a1
> +	fcvt.q.lu	a0, a1
> +	fsgnj.q	a0, a1, a2
> +	fsgnjn.q	a0, a1, a2
> +	fsgnjx.q	a0, a1, a2
> +	feq.q	a0, a1, a2
> +	flt.q	a0, a1, a2
> +	fle.q	a0, a1, a2
> +	fgt.q	a0, a1, a2
> +	fge.q	a0, a1, a2
> +	fneg.q  a0, a0
> +	fabs.q	a0, a0
> +	fclass.q	a0, a1
> +

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 2/3] RISC-V: Add instructions and operand set for z[fdq]inx
  2021-11-17 12:10 ` [PATCH v2 2/3] RISC-V: Add instructions and operand set " jiawei
  2021-11-18  2:15   ` Palmer Dabbelt
@ 2021-11-18  7:01   ` Nelson Chu
  1 sibling, 0 replies; 8+ messages in thread
From: Nelson Chu @ 2021-11-18  7:01 UTC (permalink / raw)
  To: jiawei
  Cc: Binutils, tariq.kurd, Kito Cheng, jim.wilson.gcc, Jeremy Bennett,
	cmuellner, Palmer Dabbelt, Andrew Waterman, Philipp Tomsich,
	Wei Wu (吴伟),
	sinan, shihua

Hi Jiawei,

These three patches look good, and are tested without errors for now,
so committed.  Thanks for implementing these patches, and also thanks
for Palmer's review and suggestion, it would be great if we have the
negative tests, but they can be added in the future patches.  Just
that there are still some minor indents as follows,

On Wed, Nov 17, 2021 at 8:11 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
> verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Added support for
>   z*inx extension.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (riscv_ip): Added register choice for z*inx.
>
> include/ChangeLog:
>
> * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.
>
> opcodes/ChangeLog:
>
> * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
>   z*inx.
> * riscv-opc.c: Reused INSN_CLASS_* for z*inx.
>
> ---
>  bfd/elfxx-riscv.c      |   9 ++
>  gas/config/tc-riscv.c  |   4 +-
>  include/opcode/riscv.h |   3 +
>  opcodes/riscv-dis.c    |   4 +
>  opcodes/riscv-opc.c    | 296 ++++++++++++++++++++---------------------
>  5 files changed, 167 insertions(+), 149 deletions(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 9f03542ab77..6d4107b0557 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -2184,6 +2184,15 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>      case INSN_CLASS_D_AND_C:
>        return (riscv_subset_supports (rps, "d")
>               && riscv_subset_supports (rps, "c"));
> +    case INSN_CLASS_F_OR_ZFINX:
> +      return (riscv_subset_supports (rps, "f")
> +             || riscv_subset_supports (rps, "zfinx"));
> +    case INSN_CLASS_D_OR_ZDINX:
> +      return (riscv_subset_supports (rps, "d")
> +             || riscv_subset_supports (rps, "zdinx"));
> +    case INSN_CLASS_Q_OR_ZQINX:
> +      return (riscv_subset_supports (rps, "q")
> +             || riscv_subset_supports (rps, "zqinx"));
>      case INSN_CLASS_ZBA:
>        return riscv_subset_supports (rps, "zba");
>      case INSN_CLASS_ZBB:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 8985edf4bfa..fa2c04db555 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -2480,7 +2480,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>             case 'T': /* Floating point RS2.  */
>             case 'U': /* Floating point RS1 and RS2.  */
>             case 'R': /* Floating point RS3.  */
> -             if (reg_lookup (&asarg, RCLASS_FPR, &regno))
> +             if (reg_lookup (&asarg, (riscv_subset_supports
> +                       (&riscv_rps_as, "zfinx") ?
> +                       RCLASS_GPR : RCLASS_FPR), &regno))

Not sure if the coding standard here is correct, so I changed it to be
the same as other cases, that is -

+             if (reg_lookup (&asarg,
+                             (riscv_subset_supports (&riscv_rps_as, "zfinx")
+                             ? RCLASS_GPR : RCLASS_FPR), &regno))

>                 {
>                   char c = *oparg;
>                   if (*asarg == ' ')
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 1b5b7cb6ffc..a4125a342e1 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -323,6 +323,9 @@ enum riscv_insn_class
>    INSN_CLASS_ZICSR,
>    INSN_CLASS_ZIFENCEI,
>    INSN_CLASS_ZIHINTPAUSE,
> +  INSN_CLASS_F_OR_ZFINX,
> +  INSN_CLASS_D_OR_ZDINX,
> +  INSN_CLASS_Q_OR_ZQINX,
>    INSN_CLASS_ZBA,
>    INSN_CLASS_ZBB,
>    INSN_CLASS_ZBC,
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 86e2e5ab214..6418503de82 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -534,6 +534,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
>           xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
>         }
>
> +  /* If arch has ZFINX flags, use gpr for disassemble. */

Generally, the comment should end with a dot and two spaces.

> +  if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
> +         riscv_fpr_names = riscv_gpr_names_abi;
> +

Indent.

Besides, I figured that this may be broken after we applied the
.option arch +/-/= patch.  I will take care of this in future patches.


>        for (; op->name; op++)
>         {
>           /* Does the opcode match?  */
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index f4df81f4902..57827c1287e 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -517,8 +517,8 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"fsrm",       0, INSN_CLASS_F,   "d,s",       MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
>  {"fsrmi",      0, INSN_CLASS_F,   "d,Z",       MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
>  {"fsrmi",      0, INSN_CLASS_F,   "Z",         MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS },
> -{"frflags",    0, INSN_CLASS_F,   "d",         MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
> -{"fsflags",    0, INSN_CLASS_F,   "s",         MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS },
> +{"frflags",    0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
> +{"fsflags",    0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS },
>  {"fsflags",    0, INSN_CLASS_F,   "d,s",       MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
>  {"fsflagsi",   0, INSN_CLASS_F,   "d,Z",       MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
>  {"fsflagsi",   0, INSN_CLASS_F,   "Z",         MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS },
> @@ -535,53 +535,53 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"fmv.x.s",    0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
>  {"fmv.s.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
>  {"fmv.s",      0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fneg.s",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fabs.s",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fsgnj.s",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
> -{"fsgnjn.s",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
> -{"fsgnjx.s",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
> -{"fadd.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
> -{"fadd.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
> -{"fsub.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
> -{"fsub.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
> -{"fmul.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
> -{"fmul.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
> -{"fdiv.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
> -{"fdiv.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
> -{"fsqrt.s",    0, INSN_CLASS_F,   "D,S",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
> -{"fsqrt.s",    0, INSN_CLASS_F,   "D,S,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
> -{"fmin.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
> -{"fmax.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
> -{"fmadd.s",    0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
> -{"fmadd.s",    0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
> -{"fnmadd.s",   0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
> -{"fnmadd.s",   0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
> -{"fmsub.s",    0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
> -{"fmsub.s",    0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
> -{"fnmsub.s",   0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
> -{"fnmsub.s",   0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
> -{"fcvt.w.s",   0, INSN_CLASS_F,   "d,S",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
> -{"fcvt.w.s",   0, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
> -{"fcvt.wu.s",  0, INSN_CLASS_F,   "d,S",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
> -{"fcvt.wu.s",  0, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
> -{"fcvt.s.w",   0, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.w",   0, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
> -{"fcvt.s.wu",  0, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.wu",  0, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
> -{"fclass.s",   0, INSN_CLASS_F,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
> -{"feq.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
> -{"flt.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> -{"fle.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> -{"fgt.s",      0, INSN_CLASS_F,   "d,T,S",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> -{"fge.s",      0, INSN_CLASS_F,   "d,T,S",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> -{"fcvt.l.s",  64, INSN_CLASS_F,   "d,S",       MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
> -{"fcvt.l.s",  64, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
> -{"fcvt.lu.s", 64, INSN_CLASS_F,   "d,S",       MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
> -{"fcvt.lu.s", 64, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
> -{"fcvt.s.l",  64, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.l",  64, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
> -{"fcvt.s.lu", 64, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.lu", 64, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
> +{"fneg.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,U",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,U",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fsgnj.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
> +{"fsgnjn.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
> +{"fsgnjx.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
> +{"fadd.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
> +{"fadd.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
> +{"fsub.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
> +{"fsub.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
> +{"fmul.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
> +{"fmul.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
> +{"fdiv.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
> +{"fdiv.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
> +{"fsqrt.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
> +{"fsqrt.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
> +{"fmin.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
> +{"fmax.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
> +{"fmadd.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
> +{"fmadd.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
> +{"fnmadd.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
> +{"fnmadd.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
> +{"fmsub.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
> +{"fmsub.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
> +{"fnmsub.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
> +{"fnmsub.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
> +{"fcvt.w.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.w.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
> +{"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
> +{"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
> +{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
> +{"fclass.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
> +{"feq.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
> +{"flt.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> +{"fle.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> +{"fgt.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,T,S",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> +{"fge.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,T,S",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> +{"fcvt.l.s",  64, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.l.s",  64, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
> +{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
> +{"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
> +{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
>
>  /* Double-precision floating-point instruction subset.  */
>  {"fld",        0, INSN_CLASS_D_AND_C, "D,Cn(Cc)",  MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
> @@ -593,56 +593,56 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"fsd",        0, INSN_CLASS_D,   "T,q(s)",    MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
>  {"fsd",        0, INSN_CLASS_D,   "T,A,s",     0, (int) M_FSD, match_never, INSN_MACRO },
>  {"fmv.d",      0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fneg.d",     0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fabs.d",     0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fsgnj.d",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
> -{"fsgnjn.d",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
> -{"fsgnjx.d",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
> -{"fadd.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
> -{"fadd.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
> -{"fsub.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
> -{"fsub.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
> -{"fmul.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
> -{"fmul.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
> -{"fdiv.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
> -{"fdiv.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
> -{"fsqrt.d",    0, INSN_CLASS_D,   "D,S",       MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
> -{"fsqrt.d",    0, INSN_CLASS_D,   "D,S,m",     MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
> -{"fmin.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
> -{"fmax.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
> -{"fmadd.d",    0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
> -{"fmadd.d",    0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
> -{"fnmadd.d",   0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
> -{"fnmadd.d",   0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
> -{"fmsub.d",    0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
> -{"fmsub.d",    0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
> -{"fnmsub.d",   0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
> -{"fnmsub.d",   0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
> -{"fcvt.w.d",   0, INSN_CLASS_D,   "d,S",       MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
> -{"fcvt.w.d",   0, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
> -{"fcvt.wu.d",  0, INSN_CLASS_D,   "d,S",       MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
> -{"fcvt.wu.d",  0, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
> -{"fcvt.d.w",   0, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
> -{"fcvt.d.wu",  0, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
> -{"fcvt.d.s",   0, INSN_CLASS_D,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.d",   0, INSN_CLASS_D,   "D,S",       MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.d",   0, INSN_CLASS_D,   "D,S,m",     MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
> -{"fclass.d",   0, INSN_CLASS_D,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
> -{"feq.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
> -{"flt.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> -{"fle.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> -{"fgt.d",      0, INSN_CLASS_D,   "d,T,S",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> -{"fge.d",      0, INSN_CLASS_D,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> +{"fneg.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,U",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,U",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fsgnj.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
> +{"fsgnjn.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
> +{"fsgnjx.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
> +{"fadd.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
> +{"fadd.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
> +{"fsub.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
> +{"fsub.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
> +{"fmul.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
> +{"fmul.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
> +{"fdiv.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
> +{"fdiv.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
> +{"fsqrt.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
> +{"fsqrt.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,m",     MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
> +{"fmin.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
> +{"fmax.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
> +{"fmadd.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
> +{"fmadd.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
> +{"fnmadd.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
> +{"fnmadd.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
> +{"fmsub.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
> +{"fmsub.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
> +{"fnmsub.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
> +{"fnmsub.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
> +{"fcvt.w.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
> +{"fcvt.w.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
> +{"fcvt.wu.d",  0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.d",  0, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
> +{"fcvt.d.w",   0, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.wu",  0, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.s",   0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,m",     MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
> +{"fclass.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
> +{"feq.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
> +{"flt.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> +{"fle.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> +{"fgt.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,T,S",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> +{"fge.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
>  {"fmv.x.d",   64, INSN_CLASS_D,   "d,S",       MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
>  {"fmv.d.x",   64, INSN_CLASS_D,   "D,s",       MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
> -{"fcvt.l.d",  64, INSN_CLASS_D,   "d,S",       MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
> -{"fcvt.l.d",  64, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
> -{"fcvt.lu.d", 64, INSN_CLASS_D,   "d,S",       MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
> -{"fcvt.lu.d", 64, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
> -{"fcvt.d.l",  64, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.d.l",  64, INSN_CLASS_D,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
> -{"fcvt.d.lu", 64, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.d.lu", 64, INSN_CLASS_D,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
> +{"fcvt.l.d",  64, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
> +{"fcvt.l.d",  64, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
> +{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
> +{"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
> +{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
>
>  /* Quad-precision floating-point instruction subset.  */
>  {"flq",        0, INSN_CLASS_Q,   "D,o(s)",    MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
> @@ -650,59 +650,59 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"fsq",        0, INSN_CLASS_Q,   "T,q(s)",    MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
>  {"fsq",        0, INSN_CLASS_Q,   "T,A,s",     0, (int) M_FSQ, match_never, INSN_MACRO },
>  {"fmv.q",      0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fneg.q",     0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fabs.q",     0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fsgnj.q",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
> -{"fsgnjn.q",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
> -{"fsgnjx.q",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
> -{"fadd.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
> -{"fadd.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
> -{"fsub.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
> -{"fsub.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
> -{"fmul.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
> -{"fmul.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
> -{"fdiv.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
> -{"fdiv.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
> -{"fsqrt.q",    0, INSN_CLASS_Q,   "D,S",       MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
> -{"fsqrt.q",    0, INSN_CLASS_Q,   "D,S,m",     MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
> -{"fmin.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
> -{"fmax.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
> -{"fmadd.q",    0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
> -{"fmadd.q",    0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
> -{"fnmadd.q",   0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
> -{"fnmadd.q",   0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
> -{"fmsub.q",    0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
> -{"fmsub.q",    0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
> -{"fnmsub.q",   0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
> -{"fnmsub.q",   0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
> -{"fcvt.w.q",   0, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
> -{"fcvt.w.q",   0, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
> -{"fcvt.wu.q",  0, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
> -{"fcvt.wu.q",  0, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
> -{"fcvt.q.w",   0, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.wu",  0, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.s",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.d",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.q",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.q",   0, INSN_CLASS_Q,   "D,S,m",     MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
> -{"fcvt.d.q",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
> -{"fcvt.d.q",   0, INSN_CLASS_Q,   "D,S,m",     MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
> -{"fclass.q",   0, INSN_CLASS_Q,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
> -{"feq.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
> -{"flt.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> -{"fle.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> -{"fgt.q",      0, INSN_CLASS_Q,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> -{"fge.q",      0, INSN_CLASS_Q,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> +{"fneg.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fsgnj.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
> +{"fsgnjn.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
> +{"fsgnjx.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
> +{"fadd.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
> +{"fadd.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
> +{"fsub.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fsub.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
> +{"fmul.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
> +{"fmul.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
> +{"fdiv.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
> +{"fdiv.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
> +{"fsqrt.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
> +{"fsqrt.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
> +{"fmin.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
> +{"fmax.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
> +{"fmadd.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
> +{"fmadd.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
> +{"fnmadd.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
> +{"fnmadd.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
> +{"fmsub.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fmsub.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
> +{"fnmsub.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fnmsub.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
> +{"fcvt.w.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.w.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
> +{"fcvt.wu.q",  0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.q",  0, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
> +{"fcvt.q.w",   0, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.wu",  0, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.s",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.d",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
> +{"fcvt.d.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
> +{"fclass.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
> +{"feq.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
> +{"flt.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> +{"fle.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> +{"fgt.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> +{"fge.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
>  {"fmv.x.q",   64, INSN_CLASS_Q,   "d,S",       MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
>  {"fmv.q.x",   64, INSN_CLASS_Q,   "D,s",       MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
> -{"fcvt.l.q",  64, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
> -{"fcvt.l.q",  64, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
> -{"fcvt.lu.q", 64, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
> -{"fcvt.lu.q", 64, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
> -{"fcvt.q.l",  64, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.l",  64, INSN_CLASS_Q,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
> -{"fcvt.q.lu", 64, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.lu", 64, INSN_CLASS_Q,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
> +{"fcvt.l.q",  64, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.l.q",  64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
> +{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
> +{"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
> +{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
>
>  /* Compressed instructions.  */
>  {"c.unimp",    0, INSN_CLASS_C,   "",          0, 0xffffU,  match_opcode, 0 },
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2021-11-18  7:01 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-17 12:10 [PATCH v2 0/3] RISC-V: Zfinx extension support jiawei
2021-11-17 12:10 ` [PATCH v2 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
2021-11-18  2:15   ` Palmer Dabbelt
2021-11-17 12:10 ` [PATCH v2 2/3] RISC-V: Add instructions and operand set " jiawei
2021-11-18  2:15   ` Palmer Dabbelt
2021-11-18  7:01   ` Nelson Chu
2021-11-17 12:10 ` [PATCH v2 3/3] RISC-V: Add testcases " jiawei
2021-11-18  2:15   ` Palmer Dabbelt

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