From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id E2FB53858C5E for ; Mon, 3 Apr 2023 08:13:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E2FB53858C5E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32B4AFEC; Mon, 3 Apr 2023 01:14:02 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4514E3F6C4; Mon, 3 Apr 2023 01:13:17 -0700 (PDT) From: Richard Sandiford To: Jan Beulich Mail-Followup-To: Jan Beulich ,binutils@sourceware.org, richard.sandiford@arm.com Cc: binutils@sourceware.org Subject: Re: [PATCH 00/31] aarch64: Add SME2 support References: <20230330102646.3327818-1-richard.sandiford@arm.com> <62cfd941-690a-0fbd-a9e6-49aac52b5420@suse.com> Date: Mon, 03 Apr 2023 09:13:16 +0100 In-Reply-To: <62cfd941-690a-0fbd-a9e6-49aac52b5420@suse.com> (Jan Beulich's message of "Mon, 3 Apr 2023 09:16:31 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-25.5 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Jan Beulich writes: > On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: >> This series of patches adds SME2 support to the AArch64 backend. >> Details on SME2 are available here: >> >> https://developer.arm.com/documentation/ddi0602/2022-12/SME-Instructions >> >> Tested on aarch64-linux-gnu, and via automatic cross-checking >> against the architecture description and the LLVM implementation. >> >> I've pushed the series under GWP, but I'm more than happy >> to update/adjust/fix based on post-commit review, so please >> let me know if you spot anything you think should be changed. >> >> Thanks, >> Richard >> >> >> Richard Sandiford (31): >> aarch64: Add +sme2 >> aarch64: Add a _10 suffix to FLD_imm3 >> aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array >> aarch64: Add support for vgx2 and vgx4 >> aarch64; Add support for vector offset ranges >> aarch64: Add support for predicate-as-counter registers > > Shouldn't the (alias) insn forms added here all use SME2_INSN()? It > doesn't seem to make sense to permit them with ".arch_extension sme". That's deliberate (and it's deliberate for the SVE instructions like PFALSE too). The base requirements in the table come from the underlying architectural requirements. In this case, the instructions are unchanged, and so the FEAT_* requirements are the same. Accepting predicate-as-counter registers is just a syntactic convenience. It's true that, without SME2 (or SVE2p1) you might not be able to do much with the predicate-as-counter registers except move, load and store them. But that doesn't make those operations invalid (and so something that the assembler must reject). Thanks, Richard