From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 3C9FD3858CDA for ; Thu, 30 Mar 2023 16:06:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3C9FD3858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5D44E2F4; Thu, 30 Mar 2023 09:06:54 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 90E6C3F6C4; Thu, 30 Mar 2023 09:06:09 -0700 (PDT) From: Richard Sandiford To: Simon Marchi Mail-Followup-To: Simon Marchi ,binutils@sourceware.org, richard.sandiford@arm.com Cc: binutils@sourceware.org Subject: Re: [PATCH 42/43] aarch64: Add support for strided register lists References: <20230330102359.3327695-1-richard.sandiford@arm.com> <20230330102359.3327695-43-richard.sandiford@arm.com> <2bdfbe35-8159-32e0-bac1-1586e5294c2d@polymtl.ca> Date: Thu, 30 Mar 2023 17:06:08 +0100 In-Reply-To: <2bdfbe35-8159-32e0-bac1-1586e5294c2d@polymtl.ca> (Simon Marchi's message of "Thu, 30 Mar 2023 11:50:33 -0400") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-31.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Simon Marchi writes: > On 3/30/23 06:23, Richard Sandiford wrote: >> SME2 has instructions that accept strided register lists, >> such as { z0.s, z4.s, z8.s, z12.s }. The purpose of this >> patch is to extend binutils to support such lists. >> >> The parsing code already had (unused) support for strides of 2. >> The idea here is instead to accept all strides during parsing >> and reject invalid strides during constraint checking. >> >> The SME2 instructions that accept strided operands also have >> non-strided forms. The errors about invalid strides therefore >> take a bitmask of acceptable strides, which allows multiple >> possibilities to be summed up in a single message. >> >> I've tried to update all code that handles register lists. > > Hi Richard, > > In a binutils-gdb build with --enable-targets=all, I get: > > > make[4]: Entering directory '/home/smarchi/build/binutils-gdb-all-targets/binutils' > CCLD objdump > mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-dis-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist > mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-dis-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist > mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist > mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist > mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist > mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist > collect2: error: ld returned 1 exit status Yeah, I've just pushed a patch for this. Sorry for the breakage. Richard >> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h >> index 61afe561a12..ef59d531d17 100644 >> --- a/include/opcode/aarch64.h >> +++ b/include/opcode/aarch64.h >> @@ -1122,6 +1122,19 @@ struct aarch64_indexed_za >> unsigned v : 1; /* horizontal or vertical vector indicator. */ >> }; >> >> +/* Information about a list of registers. */ >> +struct aarch64_reglist >> +{ >> + unsigned first_regno : 8; >> + unsigned num_regs : 8; >> + /* The difference between the nth and the n+1th register. */ >> + unsigned stride : 8; >> + /* 1 if it is a list of reg element. */ >> + unsigned has_index : 1; >> + /* Lane index; valid only when has_index is 1. */ >> + int64_t index; >> +} reglist; > > Probably because this last "reglist" shouldn't be there. > > Simon