* [PATCH,V4 1/8] gas: scfi: make scfi_state_restore_reg function more precise
2024-07-01 2:53 [PATCH,V4 0/8] Add SCFI support for aarch64 Indu Bhagat
@ 2024-07-01 2:53 ` Indu Bhagat
2024-07-12 15:03 ` [PATCH, V4 " Indu Bhagat
2024-07-01 2:53 ` [PATCH,V4 2/8] include: opcodes: aarch64: define new subclasses Indu Bhagat
` (6 subsequent siblings)
7 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-01 2:53 UTC (permalink / raw)
To: binutils; +Cc: richard.sandiford, Richard.Earnshaw, Indu Bhagat, nickc
[No changes in V3, V4]
PS: This patch needs a global maintainer review/approval.
[New in V2]
- This patch is orthogonal to aarch64 support. It is included here
because the testcase added for it is aarch64 specific. It is a
bugfix really.
[End of New in V2]
When the SCFI machinery detects that a register has been restored from
stack, it makes some state changes in the SCFI state object.
Prior to the patch, scfi_state_restore_reg () was setting a value of
(reg, CFI_IN_REG) for (base, state) respectively. This was causing
issues in the cmp_scfi_state () function:
- The default state of all (callee-saved) regs at the beginning of
function is set to (0, CFI_UNDEFINED).
- If a register is saved and restored on some control path, the state
of reg is (reg, CFI_IN_REG) on that path.
- On another control path where the register was perhaps not
used (or saved/restored on stack) remains (0, CFI_UNDEFINED).
- The two states should be treated equal, however, at the point in
program after the register has been restored.
Fix this by resetting the state to (0, CFI_UNDEFINED) in
scfi_state_restore_reg ().
A testcase (scfi-cfg-4.s) for this is added in a subsequent commit.
gas/
* scfi.c (scfi_state_restore_reg): Reset to 0, CFI_UNDEFINED
for base, state.
---
gas/scfi.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gas/scfi.c b/gas/scfi.c
index 744822d8102..5898a57b330 100644
--- a/gas/scfi.c
+++ b/gas/scfi.c
@@ -223,11 +223,12 @@ scfi_state_restore_reg (scfi_stateS *state, unsigned int reg)
gas_assert (state->regs[reg].state == CFI_ON_STACK);
gas_assert (state->regs[reg].base == REG_CFA);
- state->regs[reg].base = reg;
+ /* PS: the register may still be on stack much after the restore. Reset the
+ SCFI state to CFI_UNDEFINED, however, to indicate that the most updated
+ source of value is register itself from here onwards. */
+ state->regs[reg].base = 0;
state->regs[reg].offset = 0;
- /* PS: the register may still be on stack much after the restore, but the
- SCFI state keeps the state as 'in register'. */
- state->regs[reg].state = CFI_IN_REG;
+ state->regs[reg].state = CFI_UNDEFINED;
}
/* Identify if the given GAS instruction GINSN saves a register
--
2.43.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH, V4 1/8] gas: scfi: make scfi_state_restore_reg function more precise
2024-07-01 2:53 ` [PATCH,V4 1/8] gas: scfi: make scfi_state_restore_reg function more precise Indu Bhagat
@ 2024-07-12 15:03 ` Indu Bhagat
0 siblings, 0 replies; 29+ messages in thread
From: Indu Bhagat @ 2024-07-12 15:03 UTC (permalink / raw)
To: binutils
[PING]
On 6/30/24 7:53 PM, Indu Bhagat wrote:
> [No changes in V3, V4]
> PS: This patch needs a global maintainer review/approval.
>
> [New in V2]
> - This patch is orthogonal to aarch64 support. It is included here
> because the testcase added for it is aarch64 specific. It is a
> bugfix really.
> [End of New in V2]
>
> When the SCFI machinery detects that a register has been restored from
> stack, it makes some state changes in the SCFI state object.
>
> Prior to the patch, scfi_state_restore_reg () was setting a value of
> (reg, CFI_IN_REG) for (base, state) respectively. This was causing
> issues in the cmp_scfi_state () function:
> - The default state of all (callee-saved) regs at the beginning of
> function is set to (0, CFI_UNDEFINED).
> - If a register is saved and restored on some control path, the state
> of reg is (reg, CFI_IN_REG) on that path.
> - On another control path where the register was perhaps not
> used (or saved/restored on stack) remains (0, CFI_UNDEFINED).
> - The two states should be treated equal, however, at the point in
> program after the register has been restored.
>
> Fix this by resetting the state to (0, CFI_UNDEFINED) in
> scfi_state_restore_reg ().
>
> A testcase (scfi-cfg-4.s) for this is added in a subsequent commit.
>
> gas/
> * scfi.c (scfi_state_restore_reg): Reset to 0, CFI_UNDEFINED
> for base, state.
> ---
> gas/scfi.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/gas/scfi.c b/gas/scfi.c
> index 744822d8102..5898a57b330 100644
> --- a/gas/scfi.c
> +++ b/gas/scfi.c
> @@ -223,11 +223,12 @@ scfi_state_restore_reg (scfi_stateS *state, unsigned int reg)
> gas_assert (state->regs[reg].state == CFI_ON_STACK);
> gas_assert (state->regs[reg].base == REG_CFA);
>
> - state->regs[reg].base = reg;
> + /* PS: the register may still be on stack much after the restore. Reset the
> + SCFI state to CFI_UNDEFINED, however, to indicate that the most updated
> + source of value is register itself from here onwards. */
> + state->regs[reg].base = 0;
> state->regs[reg].offset = 0;
> - /* PS: the register may still be on stack much after the restore, but the
> - SCFI state keeps the state as 'in register'. */
> - state->regs[reg].state = CFI_IN_REG;
> + state->regs[reg].state = CFI_UNDEFINED;
> }
>
> /* Identify if the given GAS instruction GINSN saves a register
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH,V4 2/8] include: opcodes: aarch64: define new subclasses
2024-07-01 2:53 [PATCH,V4 0/8] Add SCFI support for aarch64 Indu Bhagat
2024-07-01 2:53 ` [PATCH,V4 1/8] gas: scfi: make scfi_state_restore_reg function more precise Indu Bhagat
@ 2024-07-01 2:53 ` Indu Bhagat
2024-07-01 17:40 ` Richard Sandiford
2024-07-01 2:53 ` [PATCH,V4 3/8] opcodes: aarch64: flags to denote subclasses of ldst insns Indu Bhagat
` (5 subsequent siblings)
7 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-01 2:53 UTC (permalink / raw)
To: binutils; +Cc: richard.sandiford, Richard.Earnshaw, Indu Bhagat
[New in V4]
The existing iclass information tells us the general shape and purpose
of the instructions. In some cases, however, we need to further disect
the iclass on the basis of other finer-grain information. E.g., for the
purpose of SCFI, we need to know whether a given insn with iclass of
ldst_* is a load or a store. Similarly, whether a particular arithmetic
insn is an add or sub or mov, etc.
This patch defines new flags to demarcate the insns. Also provide an
access function for subclass lookup.
Later, we will enforce (in aarch64-gen.c) that if an iclass has at least
one instruction with a non-zero subclass, all instructions of the iclass
must have a non-zero subclass information. If none of the defined
subclasses are applicable (or not required for SCFI purposes),
F_SUBCLASS_OTHER can be used for such instructions.
include/
* opcode/aarch64.h (F_SUBCLASS): New flag.
(F_SUBCLASS_OTHER): Likewise.
(F_LDST_LOAD): Likewise.
(F_LDST_STORE): Likewise.
(F_LDST_SWAP): Likewise.
(F_ARITH_ADD): Likewise.
(F_ARITH_SUB): Likewise.
(F_ARITH_MOV): Likewise.
(F_BRANCH_CALL): Likewise.
(F_BRANCH_RET): Likewise.
(F_MAX_SUBCLASS): Likewise.
(aarch64_opcode_subclass_p): New definition.
---
include/opcode/aarch64.h | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 61758c96285..c3ac1326b9c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1359,7 +1359,31 @@ extern const aarch64_opcode aarch64_opcode_table[];
#define F_OPD_SIZE (1ULL << 34)
/* RCPC3 instruction has the field of 'size'. */
#define F_RCPC3_SIZE (1ULL << 35)
-/* Next bit is 36. */
+
+/* 4-bit flag field to indicate subclass of instructions.
+ The available 14 nonzero values are consecutive, with room for
+ more subclasses in future. */
+#define F_SUBCLASS (15ULL << 36)
+
+#define F_SUBCLASS_OTHER (F_SUBCLASS)
+
+#define F_LDST_LOAD (1ULL << 36)
+#define F_LDST_STORE (2ULL << 36)
+/* A load followed by a store (using the same address). */
+#define F_LDST_SWAP (3ULL << 36)
+/* Subclasses to denote add, sub and mov insns. */
+#define F_ARITH_ADD (4ULL << 36)
+#define F_ARITH_SUB (5ULL << 36)
+#define F_ARITH_MOV (6ULL << 36)
+/* Subclasses to denote call and ret insns. */
+#define F_BRANCH_CALL (7ULL << 36)
+#define F_BRANCH_RET (8ULL << 36)
+
+#define F_SUBCLASS_OTHER (F_SUBCLASS)
+/* PS: To perform some sanity checks, the last declared subclass flag is used.
+ Keep F_MAX_SUBCLASS updated when declaring new subclasses. */
+#define F_MAX_SUBCLASS (F_BRANCH_RET)
+/* Next bit is 40. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */
@@ -1398,6 +1422,12 @@ pseudo_opcode_p (const aarch64_opcode *opcode)
return (opcode->flags & F_PSEUDO) != 0lu;
}
+static inline bool
+aarch64_opcode_subclass_p (const aarch64_opcode* opcode, uint64_t flag)
+{
+ return ((opcode->flags & F_SUBCLASS) == flag);
+}
+
/* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range
[IDX, IDX + 1]. */
--
2.43.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 2/8] include: opcodes: aarch64: define new subclasses
2024-07-01 2:53 ` [PATCH,V4 2/8] include: opcodes: aarch64: define new subclasses Indu Bhagat
@ 2024-07-01 17:40 ` Richard Sandiford
2024-07-11 5:14 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Richard Sandiford @ 2024-07-01 17:40 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> [New in V4]
>
> The existing iclass information tells us the general shape and purpose
> of the instructions. In some cases, however, we need to further disect
> the iclass on the basis of other finer-grain information. E.g., for the
> purpose of SCFI, we need to know whether a given insn with iclass of
> ldst_* is a load or a store. Similarly, whether a particular arithmetic
> insn is an add or sub or mov, etc.
>
> This patch defines new flags to demarcate the insns. Also provide an
> access function for subclass lookup.
>
> Later, we will enforce (in aarch64-gen.c) that if an iclass has at least
> one instruction with a non-zero subclass, all instructions of the iclass
> must have a non-zero subclass information. If none of the defined
> subclasses are applicable (or not required for SCFI purposes),
> F_SUBCLASS_OTHER can be used for such instructions.
>
> include/
> * opcode/aarch64.h (F_SUBCLASS): New flag.
> (F_SUBCLASS_OTHER): Likewise.
> (F_LDST_LOAD): Likewise.
> (F_LDST_STORE): Likewise.
> (F_LDST_SWAP): Likewise.
> (F_ARITH_ADD): Likewise.
> (F_ARITH_SUB): Likewise.
> (F_ARITH_MOV): Likewise.
> (F_BRANCH_CALL): Likewise.
> (F_BRANCH_RET): Likewise.
> (F_MAX_SUBCLASS): Likewise.
> (aarch64_opcode_subclass_p): New definition.
> ---
> include/opcode/aarch64.h | 32 +++++++++++++++++++++++++++++++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 61758c96285..c3ac1326b9c 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -1359,7 +1359,31 @@ extern const aarch64_opcode aarch64_opcode_table[];
> #define F_OPD_SIZE (1ULL << 34)
> /* RCPC3 instruction has the field of 'size'. */
> #define F_RCPC3_SIZE (1ULL << 35)
> -/* Next bit is 36. */
> +
> +/* 4-bit flag field to indicate subclass of instructions.
> + The available 14 nonzero values are consecutive, with room for
> + more subclasses in future. */
> +#define F_SUBCLASS (15ULL << 36)
> +
> +#define F_SUBCLASS_OTHER (F_SUBCLASS)
> +
> +#define F_LDST_LOAD (1ULL << 36)
> +#define F_LDST_STORE (2ULL << 36)
> +/* A load followed by a store (using the same address). */
> +#define F_LDST_SWAP (3ULL << 36)
> +/* Subclasses to denote add, sub and mov insns. */
> +#define F_ARITH_ADD (4ULL << 36)
> +#define F_ARITH_SUB (5ULL << 36)
> +#define F_ARITH_MOV (6ULL << 36)
> +/* Subclasses to denote call and ret insns. */
> +#define F_BRANCH_CALL (7ULL << 36)
> +#define F_BRANCH_RET (8ULL << 36)
When I said this field was an enum, I should have said that it's
a class-specific enum. I don't think we need the ldst and arith
subclasses to use independent values, and it might be better to
allow overlap from the outset, rather than try to retrofit it later.
F_LDST_SWAP is no longer used (a good thing!)
Thanks,
Richard
> +
> +#define F_SUBCLASS_OTHER (F_SUBCLASS)
> +/* PS: To perform some sanity checks, the last declared subclass flag is used.
> + Keep F_MAX_SUBCLASS updated when declaring new subclasses. */
> +#define F_MAX_SUBCLASS (F_BRANCH_RET)
> +/* Next bit is 40. */
>
> /* Instruction constraints. */
> /* This instruction has a predication constraint on the instruction at PC+4. */
> @@ -1398,6 +1422,12 @@ pseudo_opcode_p (const aarch64_opcode *opcode)
> return (opcode->flags & F_PSEUDO) != 0lu;
> }
>
> +static inline bool
> +aarch64_opcode_subclass_p (const aarch64_opcode* opcode, uint64_t flag)
> +{
> + return ((opcode->flags & F_SUBCLASS) == flag);
> +}
> +
> /* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
> by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range
> [IDX, IDX + 1]. */
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 2/8] include: opcodes: aarch64: define new subclasses
2024-07-01 17:40 ` Richard Sandiford
@ 2024-07-11 5:14 ` Indu Bhagat
2024-07-11 12:22 ` Richard Sandiford
0 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-11 5:14 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/1/24 10:40, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> [New in V4]
>>
>> The existing iclass information tells us the general shape and purpose
>> of the instructions. In some cases, however, we need to further disect
>> the iclass on the basis of other finer-grain information. E.g., for the
>> purpose of SCFI, we need to know whether a given insn with iclass of
>> ldst_* is a load or a store. Similarly, whether a particular arithmetic
>> insn is an add or sub or mov, etc.
>>
>> This patch defines new flags to demarcate the insns. Also provide an
>> access function for subclass lookup.
>>
>> Later, we will enforce (in aarch64-gen.c) that if an iclass has at least
>> one instruction with a non-zero subclass, all instructions of the iclass
>> must have a non-zero subclass information. If none of the defined
>> subclasses are applicable (or not required for SCFI purposes),
>> F_SUBCLASS_OTHER can be used for such instructions.
>>
>> include/
>> * opcode/aarch64.h (F_SUBCLASS): New flag.
>> (F_SUBCLASS_OTHER): Likewise.
>> (F_LDST_LOAD): Likewise.
>> (F_LDST_STORE): Likewise.
>> (F_LDST_SWAP): Likewise.
>> (F_ARITH_ADD): Likewise.
>> (F_ARITH_SUB): Likewise.
>> (F_ARITH_MOV): Likewise.
>> (F_BRANCH_CALL): Likewise.
>> (F_BRANCH_RET): Likewise.
>> (F_MAX_SUBCLASS): Likewise.
>> (aarch64_opcode_subclass_p): New definition.
>> ---
>> include/opcode/aarch64.h | 32 +++++++++++++++++++++++++++++++-
>> 1 file changed, 31 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
>> index 61758c96285..c3ac1326b9c 100644
>> --- a/include/opcode/aarch64.h
>> +++ b/include/opcode/aarch64.h
>> @@ -1359,7 +1359,31 @@ extern const aarch64_opcode aarch64_opcode_table[];
>> #define F_OPD_SIZE (1ULL << 34)
>> /* RCPC3 instruction has the field of 'size'. */
>> #define F_RCPC3_SIZE (1ULL << 35)
>> -/* Next bit is 36. */
>> +
>> +/* 4-bit flag field to indicate subclass of instructions.
>> + The available 14 nonzero values are consecutive, with room for
>> + more subclasses in future. */
>> +#define F_SUBCLASS (15ULL << 36)
>> +
>> +#define F_SUBCLASS_OTHER (F_SUBCLASS)
>> +
>> +#define F_LDST_LOAD (1ULL << 36)
>> +#define F_LDST_STORE (2ULL << 36)
>> +/* A load followed by a store (using the same address). */
>> +#define F_LDST_SWAP (3ULL << 36)
>> +/* Subclasses to denote add, sub and mov insns. */
>> +#define F_ARITH_ADD (4ULL << 36)
>> +#define F_ARITH_SUB (5ULL << 36)
>> +#define F_ARITH_MOV (6ULL << 36)
>> +/* Subclasses to denote call and ret insns. */
>> +#define F_BRANCH_CALL (7ULL << 36)
>> +#define F_BRANCH_RET (8ULL << 36)
>
> When I said this field was an enum, I should have said that it's
> a class-specific enum. I don't think we need the ldst and arith
> subclasses to use independent values, and it might be better to
> allow overlap from the outset, rather than try to retrofit it later.
>
> F_LDST_SWAP is no longer used (a good thing!)
>
OK. I have switched it to iclass-specific enum with overlap. I have
removed F_LDST_SWAP and F_MAX_SUBLASS as they are unused.
I have added function-level comments:
/* Whether the opcode has the specific subclass flag.
N.B. The overlap between F_LDST_*, F_ARITH_*, and F_BRANCH_* flags means
that the callers of this function have the responsibility of
checking for
the flags appropriate for the specific iclass. */
static inline bool
aarch64_opcode_subclass_p (const aarch64_opcode* opcode, uint64_t flag)
{
return ((opcode->flags & F_SUBCLASS) == flag);
}
> Thanks,
> Richard
>
>> +
>> +#define F_SUBCLASS_OTHER (F_SUBCLASS)
>> +/* PS: To perform some sanity checks, the last declared subclass flag is used.
>> + Keep F_MAX_SUBCLASS updated when declaring new subclasses. */
>> +#define F_MAX_SUBCLASS (F_BRANCH_RET)
>> +/* Next bit is 40. */
>>
>> /* Instruction constraints. */
>> /* This instruction has a predication constraint on the instruction at PC+4. */
>> @@ -1398,6 +1422,12 @@ pseudo_opcode_p (const aarch64_opcode *opcode)
>> return (opcode->flags & F_PSEUDO) != 0lu;
>> }
>>
>> +static inline bool
>> +aarch64_opcode_subclass_p (const aarch64_opcode* opcode, uint64_t flag)
>> +{
>> + return ((opcode->flags & F_SUBCLASS) == flag);
>> +}
>> +
>> /* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
>> by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range
>> [IDX, IDX + 1]. */
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 2/8] include: opcodes: aarch64: define new subclasses
2024-07-11 5:14 ` Indu Bhagat
@ 2024-07-11 12:22 ` Richard Sandiford
2024-07-11 17:59 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Richard Sandiford @ 2024-07-11 12:22 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> On 7/1/24 10:40, Richard Sandiford wrote:
>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>> [New in V4]
>>>
>>> The existing iclass information tells us the general shape and purpose
>>> of the instructions. In some cases, however, we need to further disect
>>> the iclass on the basis of other finer-grain information. E.g., for the
>>> purpose of SCFI, we need to know whether a given insn with iclass of
>>> ldst_* is a load or a store. Similarly, whether a particular arithmetic
>>> insn is an add or sub or mov, etc.
>>>
>>> This patch defines new flags to demarcate the insns. Also provide an
>>> access function for subclass lookup.
>>>
>>> Later, we will enforce (in aarch64-gen.c) that if an iclass has at least
>>> one instruction with a non-zero subclass, all instructions of the iclass
>>> must have a non-zero subclass information. If none of the defined
>>> subclasses are applicable (or not required for SCFI purposes),
>>> F_SUBCLASS_OTHER can be used for such instructions.
>>>
>>> include/
>>> * opcode/aarch64.h (F_SUBCLASS): New flag.
>>> (F_SUBCLASS_OTHER): Likewise.
>>> (F_LDST_LOAD): Likewise.
>>> (F_LDST_STORE): Likewise.
>>> (F_LDST_SWAP): Likewise.
>>> (F_ARITH_ADD): Likewise.
>>> (F_ARITH_SUB): Likewise.
>>> (F_ARITH_MOV): Likewise.
>>> (F_BRANCH_CALL): Likewise.
>>> (F_BRANCH_RET): Likewise.
>>> (F_MAX_SUBCLASS): Likewise.
>>> (aarch64_opcode_subclass_p): New definition.
>>> ---
>>> include/opcode/aarch64.h | 32 +++++++++++++++++++++++++++++++-
>>> 1 file changed, 31 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
>>> index 61758c96285..c3ac1326b9c 100644
>>> --- a/include/opcode/aarch64.h
>>> +++ b/include/opcode/aarch64.h
>>> @@ -1359,7 +1359,31 @@ extern const aarch64_opcode aarch64_opcode_table[];
>>> #define F_OPD_SIZE (1ULL << 34)
>>> /* RCPC3 instruction has the field of 'size'. */
>>> #define F_RCPC3_SIZE (1ULL << 35)
>>> -/* Next bit is 36. */
>>> +
>>> +/* 4-bit flag field to indicate subclass of instructions.
>>> + The available 14 nonzero values are consecutive, with room for
>>> + more subclasses in future. */
>>> +#define F_SUBCLASS (15ULL << 36)
>>> +
>>> +#define F_SUBCLASS_OTHER (F_SUBCLASS)
>>> +
>>> +#define F_LDST_LOAD (1ULL << 36)
>>> +#define F_LDST_STORE (2ULL << 36)
>>> +/* A load followed by a store (using the same address). */
>>> +#define F_LDST_SWAP (3ULL << 36)
>>> +/* Subclasses to denote add, sub and mov insns. */
>>> +#define F_ARITH_ADD (4ULL << 36)
>>> +#define F_ARITH_SUB (5ULL << 36)
>>> +#define F_ARITH_MOV (6ULL << 36)
>>> +/* Subclasses to denote call and ret insns. */
>>> +#define F_BRANCH_CALL (7ULL << 36)
>>> +#define F_BRANCH_RET (8ULL << 36)
>>
>> When I said this field was an enum, I should have said that it's
>> a class-specific enum. I don't think we need the ldst and arith
>> subclasses to use independent values, and it might be better to
>> allow overlap from the outset, rather than try to retrofit it later.
>>
>> F_LDST_SWAP is no longer used (a good thing!)
>>
>
> OK. I have switched it to iclass-specific enum with overlap. I have
> removed F_LDST_SWAP and F_MAX_SUBLASS as they are unused.
>
> I have added function-level comments:
>
> /* Whether the opcode has the specific subclass flag.
> N.B. The overlap between F_LDST_*, F_ARITH_*, and F_BRANCH_* flags means
> that the callers of this function have the responsibility of
> checking for
> the flags appropriate for the specific iclass. */
> static inline bool
> aarch64_opcode_subclass_p (const aarch64_opcode* opcode, uint64_t flag)
> {
> return ((opcode->flags & F_SUBCLASS) == flag);
> }
Sounds good. How about "The overlap between flags like ... means that ...",
to make it clear that the list isn't meant to be exhaustive? We could add
other such subclasses in future.
Richard
>> Thanks,
>> Richard
>>
>>> +
>>> +#define F_SUBCLASS_OTHER (F_SUBCLASS)
>>> +/* PS: To perform some sanity checks, the last declared subclass flag is used.
>>> + Keep F_MAX_SUBCLASS updated when declaring new subclasses. */
>>> +#define F_MAX_SUBCLASS (F_BRANCH_RET)
>>> +/* Next bit is 40. */
>>>
>>> /* Instruction constraints. */
>>> /* This instruction has a predication constraint on the instruction at PC+4. */
>>> @@ -1398,6 +1422,12 @@ pseudo_opcode_p (const aarch64_opcode *opcode)
>>> return (opcode->flags & F_PSEUDO) != 0lu;
>>> }
>>>
>>> +static inline bool
>>> +aarch64_opcode_subclass_p (const aarch64_opcode* opcode, uint64_t flag)
>>> +{
>>> + return ((opcode->flags & F_SUBCLASS) == flag);
>>> +}
>>> +
>>> /* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
>>> by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range
>>> [IDX, IDX + 1]. */
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 2/8] include: opcodes: aarch64: define new subclasses
2024-07-11 12:22 ` Richard Sandiford
@ 2024-07-11 17:59 ` Indu Bhagat
0 siblings, 0 replies; 29+ messages in thread
From: Indu Bhagat @ 2024-07-11 17:59 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/11/24 05:22, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> On 7/1/24 10:40, Richard Sandiford wrote:
>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>> [New in V4]
>>>>
>>>> The existing iclass information tells us the general shape and purpose
>>>> of the instructions. In some cases, however, we need to further disect
>>>> the iclass on the basis of other finer-grain information. E.g., for the
>>>> purpose of SCFI, we need to know whether a given insn with iclass of
>>>> ldst_* is a load or a store. Similarly, whether a particular arithmetic
>>>> insn is an add or sub or mov, etc.
>>>>
>>>> This patch defines new flags to demarcate the insns. Also provide an
>>>> access function for subclass lookup.
>>>>
>>>> Later, we will enforce (in aarch64-gen.c) that if an iclass has at least
>>>> one instruction with a non-zero subclass, all instructions of the iclass
>>>> must have a non-zero subclass information. If none of the defined
>>>> subclasses are applicable (or not required for SCFI purposes),
>>>> F_SUBCLASS_OTHER can be used for such instructions.
>>>>
>>>> include/
>>>> * opcode/aarch64.h (F_SUBCLASS): New flag.
>>>> (F_SUBCLASS_OTHER): Likewise.
>>>> (F_LDST_LOAD): Likewise.
>>>> (F_LDST_STORE): Likewise.
>>>> (F_LDST_SWAP): Likewise.
>>>> (F_ARITH_ADD): Likewise.
>>>> (F_ARITH_SUB): Likewise.
>>>> (F_ARITH_MOV): Likewise.
>>>> (F_BRANCH_CALL): Likewise.
>>>> (F_BRANCH_RET): Likewise.
>>>> (F_MAX_SUBCLASS): Likewise.
>>>> (aarch64_opcode_subclass_p): New definition.
>>>> ---
>>>> include/opcode/aarch64.h | 32 +++++++++++++++++++++++++++++++-
>>>> 1 file changed, 31 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
>>>> index 61758c96285..c3ac1326b9c 100644
>>>> --- a/include/opcode/aarch64.h
>>>> +++ b/include/opcode/aarch64.h
>>>> @@ -1359,7 +1359,31 @@ extern const aarch64_opcode aarch64_opcode_table[];
>>>> #define F_OPD_SIZE (1ULL << 34)
>>>> /* RCPC3 instruction has the field of 'size'. */
>>>> #define F_RCPC3_SIZE (1ULL << 35)
>>>> -/* Next bit is 36. */
>>>> +
>>>> +/* 4-bit flag field to indicate subclass of instructions.
>>>> + The available 14 nonzero values are consecutive, with room for
>>>> + more subclasses in future. */
>>>> +#define F_SUBCLASS (15ULL << 36)
>>>> +
>>>> +#define F_SUBCLASS_OTHER (F_SUBCLASS)
>>>> +
>>>> +#define F_LDST_LOAD (1ULL << 36)
>>>> +#define F_LDST_STORE (2ULL << 36)
>>>> +/* A load followed by a store (using the same address). */
>>>> +#define F_LDST_SWAP (3ULL << 36)
>>>> +/* Subclasses to denote add, sub and mov insns. */
>>>> +#define F_ARITH_ADD (4ULL << 36)
>>>> +#define F_ARITH_SUB (5ULL << 36)
>>>> +#define F_ARITH_MOV (6ULL << 36)
>>>> +/* Subclasses to denote call and ret insns. */
>>>> +#define F_BRANCH_CALL (7ULL << 36)
>>>> +#define F_BRANCH_RET (8ULL << 36)
>>>
>>> When I said this field was an enum, I should have said that it's
>>> a class-specific enum. I don't think we need the ldst and arith
>>> subclasses to use independent values, and it might be better to
>>> allow overlap from the outset, rather than try to retrofit it later.
>>>
>>> F_LDST_SWAP is no longer used (a good thing!)
>>>
>>
>> OK. I have switched it to iclass-specific enum with overlap. I have
>> removed F_LDST_SWAP and F_MAX_SUBLASS as they are unused.
>>
>> I have added function-level comments:
>>
>> /* Whether the opcode has the specific subclass flag.
>> N.B. The overlap between F_LDST_*, F_ARITH_*, and F_BRANCH_* flags means
>> that the callers of this function have the responsibility of
>> checking for
>> the flags appropriate for the specific iclass. */
>> static inline bool
>> aarch64_opcode_subclass_p (const aarch64_opcode* opcode, uint64_t flag)
>> {
>> return ((opcode->flags & F_SUBCLASS) == flag);
>> }
>
> Sounds good. How about "The overlap between flags like ... means that ...",
> to make it clear that the list isn't meant to be exhaustive? We could add
> other such subclasses in future.
>
Thanks. I too spotted this one and made that change already after I sent
the email yesterday :)
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH,V4 3/8] opcodes: aarch64: flags to denote subclasses of ldst insns
2024-07-01 2:53 [PATCH,V4 0/8] Add SCFI support for aarch64 Indu Bhagat
2024-07-01 2:53 ` [PATCH,V4 1/8] gas: scfi: make scfi_state_restore_reg function more precise Indu Bhagat
2024-07-01 2:53 ` [PATCH,V4 2/8] include: opcodes: aarch64: define new subclasses Indu Bhagat
@ 2024-07-01 2:53 ` Indu Bhagat
2024-07-01 18:06 ` Richard Sandiford
2024-07-01 2:54 ` [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns Indu Bhagat
` (4 subsequent siblings)
7 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-01 2:53 UTC (permalink / raw)
To: binutils; +Cc: richard.sandiford, Richard.Earnshaw, Indu Bhagat
[Changes in V4]
- Specify subclasses only for those iclasses relevent to SCFI:
ldst_imm9, ldst_pos, ldstpair_indexed, ldstpair_off
[End of changes in V4]
[Changes in V3]
- Use F_LDST_SWAP for lse_atomic ld/st ops. Use of F_LDST_LOAD or
F_LDST_STORE was incorrect.
[End of changes in V3]
[New in V2]
The existing iclass information tells us the general shape and purpose
of the instructions. In some cases, however, we need to further disect
the iclass on the basis of other finer-grain information. E.g., for the
purpose of SCFI, we need to know whether a given insn with iclass
of ldst_* is a load or a store.
opcodes/
* aarch64-tbl.h: Use the new F_LDST_* flags.
---
opcodes/aarch64-tbl.h | 78 +++++++++++++++++++++----------------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7ef9cea9119..6e523db6277 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4123,39 +4123,39 @@ const struct aarch64_opcode aarch64_opcode_table[] =
__FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE),
FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE),
/* Load/store register (immediate indexed). */
- CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0),
- CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0),
- CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE),
- CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0),
- CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0),
- CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0),
- CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0),
- CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE),
- CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
- CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
- CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
+ CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, F_LDST_STORE),
+ CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, F_LDST_LOAD),
+ CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDST_LOAD | F_LDS_SIZE),
+ CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, F_LDST_STORE),
+ CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, F_LDST_LOAD),
+ CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, F_LDST_STORE),
+ CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, F_LDST_LOAD),
+ CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDST_LOAD | F_LDS_SIZE),
+ CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_LDST_STORE | F_GPRSIZE_IN_Q),
+ CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_LDST_LOAD | F_GPRSIZE_IN_Q),
+ CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, F_LDST_LOAD),
/* Load/store Allocation Tag instructions. */
MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
- MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
- MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
- MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
- MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
+ MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
+ MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
+ MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
+ MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
/* Load/store register (unsigned immediate). */
- CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
- CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
- CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE),
- CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
- CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
- CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
- CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
- CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE),
- CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
- CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
- CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
- CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0),
+ CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, F_LDST_STORE),
+ CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, F_LDST_LOAD),
+ CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDST_LOAD | F_LDS_SIZE),
+ CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, F_LDST_STORE),
+ CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, F_LDST_LOAD),
+ CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, F_LDST_STORE),
+ CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, F_LDST_LOAD),
+ CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDST_LOAD | F_LDS_SIZE),
+ CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q | F_LDST_STORE),
+ CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q | F_LDST_LOAD),
+ CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, F_LDST_LOAD),
+ CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, F_LDST_LOAD),
/* Load/store register (register offset). */
CORE_INSN ("strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0),
CORE_INSN ("ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0),
@@ -4238,19 +4238,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
CORE_INSN ("ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
/* Load/store register pair (offset). */
- CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
- CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
- CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
- CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
- {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
- MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
+ CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
+ CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
+ CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_STORE | 0),
+ CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_LOAD),
+ {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_LDST_LOAD, 0, 0, VERIFIER (ldpsw)},
+ MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_LDST_STORE),
/* Load/store register pair (indexed). */
- CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
- CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
- CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
- CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
- {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
- MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
+ CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
+ CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
+ CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_STORE),
+ CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_LOAD),
+ {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_LDST_LOAD, 0, 0, VERIFIER (ldpsw)},
+ MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_LDST_STORE),
/* Load register (literal). */
CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q),
CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0),
--
2.43.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 3/8] opcodes: aarch64: flags to denote subclasses of ldst insns
2024-07-01 2:53 ` [PATCH,V4 3/8] opcodes: aarch64: flags to denote subclasses of ldst insns Indu Bhagat
@ 2024-07-01 18:06 ` Richard Sandiford
2024-07-11 5:45 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Richard Sandiford @ 2024-07-01 18:06 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> [Changes in V4]
> - Specify subclasses only for those iclasses relevent to SCFI:
> ldst_imm9, ldst_pos, ldstpair_indexed, ldstpair_off
> [End of changes in V4]
>
> [Changes in V3]
> - Use F_LDST_SWAP for lse_atomic ld/st ops. Use of F_LDST_LOAD or
> F_LDST_STORE was incorrect.
> [End of changes in V3]
>
> [New in V2]
>
> The existing iclass information tells us the general shape and purpose
> of the instructions. In some cases, however, we need to further disect
> the iclass on the basis of other finer-grain information. E.g., for the
> purpose of SCFI, we need to know whether a given insn with iclass
> of ldst_* is a load or a store.
>
> opcodes/
> * aarch64-tbl.h: Use the new F_LDST_* flags.
> ---
> opcodes/aarch64-tbl.h | 78 +++++++++++++++++++++----------------------
> 1 file changed, 39 insertions(+), 39 deletions(-)
>
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 7ef9cea9119..6e523db6277 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -4123,39 +4123,39 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> __FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE),
> FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE),
> /* Load/store register (immediate indexed). */
> - CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0),
> - CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0),
> - CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE),
> - CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0),
> - CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0),
> - CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0),
> - CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0),
> - CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE),
> - CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
> - CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
> - CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
> + CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, F_LDST_STORE),
> + CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, F_LDST_LOAD),
> + CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDST_LOAD | F_LDS_SIZE),
> + CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, F_LDST_STORE),
> + CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, F_LDST_LOAD),
> + CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, F_LDST_STORE),
> + CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, F_LDST_LOAD),
> + CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDST_LOAD | F_LDS_SIZE),
> + CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_LDST_STORE | F_GPRSIZE_IN_Q),
> + CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_LDST_LOAD | F_GPRSIZE_IN_Q),
> + CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, F_LDST_LOAD),
> /* Load/store Allocation Tag instructions. */
> MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
> MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
> MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
> MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
> - MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
> - MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
> - MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
> - MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
> + MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
> + MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
> + MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
> + MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
These store an allocation tag, rather than storing the contents of the
registers to regular memory. I think they should be put in an "other"
category.
> /* Load/store register (unsigned immediate). */
> - CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
> - CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
> - CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE),
> - CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
> - CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
> - CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
> - CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
> - CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE),
> - CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
> - CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
> - CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
> - CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0),
> + CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, F_LDST_STORE),
AFAICT, patch 7/8 doesn't distinguish between byte stores and other sizes
of store, even though this matters for CFI purposes. I think we should
use an "other" category for anything that isn't a full load or store of
a W register, X register, or FPR.
Patch 7/8 shouldn't treat a W, B, H or S load or store as being enough
for CFI purposes. The width has to be 8 bytes or more.
Similarly, for LDP & STP, 7/8 should punt on W and S loads and stores,
since they cannot implement a full save & restore for CFI purposes.
> + CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, F_LDST_LOAD),
> + CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDST_LOAD | F_LDS_SIZE),
> + CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, F_LDST_STORE),
> + CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, F_LDST_LOAD),
> + CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, F_LDST_STORE),
> + CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, F_LDST_LOAD),
> + CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDST_LOAD | F_LDS_SIZE),
> + CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q | F_LDST_STORE),
> + CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q | F_LDST_LOAD),
> + CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, F_LDST_LOAD),
> + CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, F_LDST_LOAD),
I think PRFM should be marked "other" as well.
> /* Load/store register (register offset). */
> CORE_INSN ("strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0),
> CORE_INSN ("ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0),
> @@ -4238,19 +4238,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> CORE_INSN ("stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
> CORE_INSN ("ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
> /* Load/store register pair (offset). */
> - CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
> - CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
> - CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
> - CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
> - {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
> - MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
> + CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
> + CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
> + CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_STORE | 0),
> + CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_LOAD),
> + {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_LDST_LOAD, 0, 0, VERIFIER (ldpsw)},
The last one is also "other".
> + MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_LDST_STORE),
> /* Load/store register pair (indexed). */
> - CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
> - CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
> - CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
> - CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
> - {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
> - MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
> + CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
> + CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
> + CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_STORE),
> + CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_LOAD),
> + {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_LDST_LOAD, 0, 0, VERIFIER (ldpsw)},
Same here.
Thanks,
Richard
> + MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_LDST_STORE),
> /* Load register (literal). */
> CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q),
> CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0),
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 3/8] opcodes: aarch64: flags to denote subclasses of ldst insns
2024-07-01 18:06 ` Richard Sandiford
@ 2024-07-11 5:45 ` Indu Bhagat
2024-07-12 13:59 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-11 5:45 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/1/24 11:06, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> [Changes in V4]
>> - Specify subclasses only for those iclasses relevent to SCFI:
>> ldst_imm9, ldst_pos, ldstpair_indexed, ldstpair_off
>> [End of changes in V4]
>>
>> [Changes in V3]
>> - Use F_LDST_SWAP for lse_atomic ld/st ops. Use of F_LDST_LOAD or
>> F_LDST_STORE was incorrect.
>> [End of changes in V3]
>>
>> [New in V2]
>>
>> The existing iclass information tells us the general shape and purpose
>> of the instructions. In some cases, however, we need to further disect
>> the iclass on the basis of other finer-grain information. E.g., for the
>> purpose of SCFI, we need to know whether a given insn with iclass
>> of ldst_* is a load or a store.
>>
>> opcodes/
>> * aarch64-tbl.h: Use the new F_LDST_* flags.
>> ---
>> opcodes/aarch64-tbl.h | 78 +++++++++++++++++++++----------------------
>> 1 file changed, 39 insertions(+), 39 deletions(-)
>>
>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>> index 7ef9cea9119..6e523db6277 100644
>> --- a/opcodes/aarch64-tbl.h
>> +++ b/opcodes/aarch64-tbl.h
>> @@ -4123,39 +4123,39 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>> __FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE),
>> FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE),
>> /* Load/store register (immediate indexed). */
>> - CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0),
>> - CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0),
>> - CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE),
>> - CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0),
>> - CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0),
>> - CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0),
>> - CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0),
>> - CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE),
>> - CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
>> - CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
>> - CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
>> + CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, F_LDST_STORE),
>> + CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, F_LDST_LOAD),
>> + CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDST_LOAD | F_LDS_SIZE),
>> + CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, F_LDST_STORE),
>> + CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, F_LDST_LOAD),
>> + CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, F_LDST_STORE),
>> + CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, F_LDST_LOAD),
>> + CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDST_LOAD | F_LDS_SIZE),
>> + CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_LDST_STORE | F_GPRSIZE_IN_Q),
>> + CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_LDST_LOAD | F_GPRSIZE_IN_Q),
>> + CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, F_LDST_LOAD),
>> /* Load/store Allocation Tag instructions. */
>> MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>> MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>> MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>> MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>> - MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>> - MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>> - MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>> - MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>> + MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>> + MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>> + MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>> + MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>
> These store an allocation tag, rather than storing the contents of the
> registers to regular memory. I think they should be put in an "other"
> category.
>
I have changed these to F_SUBCLASS_OTHER. And on the ginsn generation
side, no memory ginsn op is generated (address calculation op is
generated if writeback is in effect as usual). Also added code comments
in tc-aarch-ginsn.c to clarify that skipping memory ops is needed
because the memory op affects the tag only.
>> /* Load/store register (unsigned immediate). */
>> - CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
>> - CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
>> - CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE),
>> - CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
>> - CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
>> - CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
>> - CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
>> - CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE),
>> - CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
>> - CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
>> - CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
>> - CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0),
>> + CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, F_LDST_STORE),
>
> AFAICT, patch 7/8 doesn't distinguish between byte stores and other sizes
> of store, even though this matters for CFI purposes. I think we should
> use an "other" category for anything that isn't a full load or store of
> a W register, X register, or FPR.
>
> Patch 7/8 shouldn't treat a W, B, H or S load or store as being enough
> for CFI purposes. The width has to be 8 bytes or more.
>
> Similarly, for LDP & STP, 7/8 should punt on W and S loads and stores,
> since they cannot implement a full save & restore for CFI purposes.
>
Currently, the checks in dw2gencfi.c issue a warning if CFI offsets are
not a multiple of 8. So if user says --scfi=experimental for
stp s8, s9, [sp, 96]
they get an error:
Error: register save offset not a multiple of 8
I was sort of relying on the above for some cases, while leaving the
users on their own for other cases. E.g, No error is issued if the user
does a save/restore of S register like so:
str s8, [sp, 96]
Hmm, I could punt on W and S by not creating ginsn mem ops for them
altogether. Should the user be warned though ? How about something like :
Warning: ignored probable save/restore op of less than 8-byte
As this will be diagnosed by the ginsn creation code, the warning will
be issued when a load / store:
- of callee-saved register,
- of width < 8 bytes,
- and with addr_reg involving REG_SP or REG_FP is seen
To avoid the high number of warnings, we could warn once (for the first
sub 8-byte applicable load/store). Do you think the warning is useful ?
>> + CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, F_LDST_LOAD),
>> + CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDST_LOAD | F_LDS_SIZE),
>> + CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, F_LDST_STORE),
>> + CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, F_LDST_LOAD),
>> + CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, F_LDST_STORE),
>> + CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, F_LDST_LOAD),
>> + CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDST_LOAD | F_LDS_SIZE),
>> + CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q | F_LDST_STORE),
>> + CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q | F_LDST_LOAD),
>> + CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, F_LDST_LOAD),
>> + CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, F_LDST_LOAD),
>
> I think PRFM should be marked "other" as well.
>
Done.
>> /* Load/store register (register offset). */
>> CORE_INSN ("strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0),
>> CORE_INSN ("ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0),
>> @@ -4238,19 +4238,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>> CORE_INSN ("stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>> CORE_INSN ("ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>> /* Load/store register pair (offset). */
>> - CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
>> - CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
>> - CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>> - CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>> - {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
>> - MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
>> + CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
>> + CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
>> + CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_STORE | 0),
>> + CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_LOAD),
>> + {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_LDST_LOAD, 0, 0, VERIFIER (ldpsw)},
>
> The last one is also "other".
>
>> + MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_LDST_STORE),
>> /* Load/store register pair (indexed). */
>> - CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
>> - CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
>> - CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>> - CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>> - {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
>> - MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
>> + CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
>> + CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),
>> + CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_STORE),
>> + CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, F_LDST_LOAD),
>> + {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_LDST_LOAD, 0, 0, VERIFIER (ldpsw)},
>
> Same here.
>
> Thanks,
> Richard
>
>> + MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, F_LDST_STORE),
>> /* Load register (literal). */
>> CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q),
>> CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0),
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 3/8] opcodes: aarch64: flags to denote subclasses of ldst insns
2024-07-11 5:45 ` Indu Bhagat
@ 2024-07-12 13:59 ` Indu Bhagat
2024-07-13 7:34 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-12 13:59 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/10/24 22:45, Indu Bhagat wrote:
> On 7/1/24 11:06, Richard Sandiford wrote:
>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>> [Changes in V4]
>>> - Specify subclasses only for those iclasses relevent to SCFI:
>>> ldst_imm9, ldst_pos, ldstpair_indexed, ldstpair_off
>>> [End of changes in V4]
>>>
>>> [Changes in V3]
>>> - Use F_LDST_SWAP for lse_atomic ld/st ops. Use of F_LDST_LOAD or
>>> F_LDST_STORE was incorrect.
>>> [End of changes in V3]
>>>
>>> [New in V2]
>>>
>>> The existing iclass information tells us the general shape and purpose
>>> of the instructions. In some cases, however, we need to further disect
>>> the iclass on the basis of other finer-grain information. E.g., for the
>>> purpose of SCFI, we need to know whether a given insn with iclass
>>> of ldst_* is a load or a store.
>>>
>>> opcodes/
>>> * aarch64-tbl.h: Use the new F_LDST_* flags.
>>> ---
>>> opcodes/aarch64-tbl.h | 78 +++++++++++++++++++++----------------------
>>> 1 file changed, 39 insertions(+), 39 deletions(-)
>>>
>>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>>> index 7ef9cea9119..6e523db6277 100644
>>> --- a/opcodes/aarch64-tbl.h
>>> +++ b/opcodes/aarch64-tbl.h
>>> @@ -4123,39 +4123,39 @@ const struct aarch64_opcode
>>> aarch64_opcode_table[] =
>>> __FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, OP4 (Fd,
>>> Fn, Fm, COND), QL_FP_COND, F_FPTYPE),
>>> FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd,
>>> Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE),
>>> /* Load/store register (immediate indexed). */
>>> - CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_W8, 0),
>>> - CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_W8, 0),
>>> - CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE),
>>> - CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft,
>>> ADDR_SIMM9), QL_LDST_FP, 0),
>>> - CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft,
>>> ADDR_SIMM9), QL_LDST_FP, 0),
>>> - CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_W16, 0),
>>> - CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_W16, 0),
>>> - CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE),
>>> - CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
>>> - CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
>>> - CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_X32, 0),
>>> + CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_W8, F_LDST_STORE),
>>> + CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_W8, F_LDST_LOAD),
>>> + CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_R8, F_LDST_LOAD | F_LDS_SIZE),
>>> + CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft,
>>> ADDR_SIMM9), QL_LDST_FP, F_LDST_STORE),
>>> + CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft,
>>> ADDR_SIMM9), QL_LDST_FP, F_LDST_LOAD),
>>> + CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_W16, F_LDST_STORE),
>>> + CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_W16, F_LDST_LOAD),
>>> + CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_R16, F_LDST_LOAD | F_LDS_SIZE),
>>> + CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_R, F_LDST_STORE | F_GPRSIZE_IN_Q),
>>> + CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_R, F_LDST_LOAD | F_GPRSIZE_IN_Q),
>>> + CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>> ADDR_SIMM9), QL_LDST_X32, F_LDST_LOAD),
>>> /* Load/store Allocation Tag instructions. */
>>> MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>> MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>> MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>> MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>> - MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>> - MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>> - MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>> - MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>> + MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>>> + MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>>> + MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>>> + MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2
>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>>
>> These store an allocation tag, rather than storing the contents of the
>> registers to regular memory. I think they should be put in an "other"
>> category.
>>
>
> I have changed these to F_SUBCLASS_OTHER. And on the ginsn generation
> side, no memory ginsn op is generated (address calculation op is
> generated if writeback is in effect as usual). Also added code comments
> in tc-aarch-ginsn.c to clarify that skipping memory ops is needed
> because the memory op affects the tag only.
>
>>> /* Load/store register (unsigned immediate). */
>>> - CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS,
>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
>>> - CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS,
>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
>>> - CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos,
>>> OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE),
>>> - CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS,
>>> OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
>>> - CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS,
>>> OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
>>> - CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS,
>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
>>> - CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS,
>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
>>> - CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos,
>>> OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE),
>>> - CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS,
>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
>>> - CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS,
>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
>>> - CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos,
>>> OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
>>> - CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS,
>>> OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0),
>>> + CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS,
>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, F_LDST_STORE),
>>
>> AFAICT, patch 7/8 doesn't distinguish between byte stores and other sizes
>> of store, even though this matters for CFI purposes. I think we should
>> use an "other" category for anything that isn't a full load or store of
>> a W register, X register, or FPR.
>>
>> Patch 7/8 shouldn't treat a W, B, H or S load or store as being enough
>> for CFI purposes. The width has to be 8 bytes or more.
>>
>> Similarly, for LDP & STP, 7/8 should punt on W and S loads and stores,
>> since they cannot implement a full save & restore for CFI purposes.
>>
>
> Currently, the checks in dw2gencfi.c issue a warning if CFI offsets are
> not a multiple of 8. So if user says --scfi=experimental for
> stp s8, s9, [sp, 96]
> they get an error:
> Error: register save offset not a multiple of 8
>
> I was sort of relying on the above for some cases, while leaving the
> users on their own for other cases. E.g, No error is issued if the user
> does a save/restore of S register like so:
> str s8, [sp, 96]
>
> Hmm, I could punt on W and S by not creating ginsn mem ops for them
> altogether. Should the user be warned though ? How about something like :
> Warning: ignored probable save/restore op of less than 8-byte
>
> As this will be diagnosed by the ginsn creation code, the warning will
> be issued when a load / store:
> - of callee-saved register,
> - of width < 8 bytes,
> - and with addr_reg involving REG_SP or REG_FP is seen
>
> To avoid the high number of warnings, we could warn once (for the first
> sub 8-byte applicable load/store). Do you think the warning is useful ?
>
I am inclining towards working on this as a follow-up patch (not
included in V5). Punting on S and W registers should be easy, but I
would like to test it out to be sure I am not misssing anything.
Further, I am tending towards not adding a new warning for this in the
current infrastructure at all (mostly because there will be false
positives which dilutes the eficacy of the warning). IIUC, the usage of
W and S registers to save/restore callee-saved registers is not
ABI-conformant anyway.
Please let me know your opinion on defering this as a follow-up patch.
Thanks
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 3/8] opcodes: aarch64: flags to denote subclasses of ldst insns
2024-07-12 13:59 ` Indu Bhagat
@ 2024-07-13 7:34 ` Indu Bhagat
0 siblings, 0 replies; 29+ messages in thread
From: Indu Bhagat @ 2024-07-13 7:34 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/12/24 6:59 AM, Indu Bhagat wrote:
> On 7/10/24 22:45, Indu Bhagat wrote:
>> On 7/1/24 11:06, Richard Sandiford wrote:
>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>> [Changes in V4]
>>>> - Specify subclasses only for those iclasses relevent to SCFI:
>>>> ldst_imm9, ldst_pos, ldstpair_indexed, ldstpair_off
>>>> [End of changes in V4]
>>>>
>>>> [Changes in V3]
>>>> - Use F_LDST_SWAP for lse_atomic ld/st ops. Use of F_LDST_LOAD or
>>>> F_LDST_STORE was incorrect.
>>>> [End of changes in V3]
>>>>
>>>> [New in V2]
>>>>
>>>> The existing iclass information tells us the general shape and purpose
>>>> of the instructions. In some cases, however, we need to further disect
>>>> the iclass on the basis of other finer-grain information. E.g., for
>>>> the
>>>> purpose of SCFI, we need to know whether a given insn with iclass
>>>> of ldst_* is a load or a store.
>>>>
>>>> opcodes/
>>>> * aarch64-tbl.h: Use the new F_LDST_* flags.
>>>> ---
>>>> opcodes/aarch64-tbl.h | 78
>>>> +++++++++++++++++++++----------------------
>>>> 1 file changed, 39 insertions(+), 39 deletions(-)
>>>>
>>>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>>>> index 7ef9cea9119..6e523db6277 100644
>>>> --- a/opcodes/aarch64-tbl.h
>>>> +++ b/opcodes/aarch64-tbl.h
>>>> @@ -4123,39 +4123,39 @@ const struct aarch64_opcode
>>>> aarch64_opcode_table[] =
>>>> __FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, OP4
>>>> (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE),
>>>> FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd,
>>>> Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE),
>>>> /* Load/store register (immediate indexed). */
>>>> - CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_W8, 0),
>>>> - CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_W8, 0),
>>>> - CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2
>>>> (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE),
>>>> - CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft,
>>>> ADDR_SIMM9), QL_LDST_FP, 0),
>>>> - CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft,
>>>> ADDR_SIMM9), QL_LDST_FP, 0),
>>>> - CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_W16, 0),
>>>> - CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_W16, 0),
>>>> - CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2
>>>> (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE),
>>>> - CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
>>>> - CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
>>>> - CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2
>>>> (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
>>>> + CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_W8, F_LDST_STORE),
>>>> + CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_W8, F_LDST_LOAD),
>>>> + CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2
>>>> (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDST_LOAD | F_LDS_SIZE),
>>>> + CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft,
>>>> ADDR_SIMM9), QL_LDST_FP, F_LDST_STORE),
>>>> + CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft,
>>>> ADDR_SIMM9), QL_LDST_FP, F_LDST_LOAD),
>>>> + CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_W16, F_LDST_STORE),
>>>> + CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_W16, F_LDST_LOAD),
>>>> + CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2
>>>> (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDST_LOAD | F_LDS_SIZE),
>>>> + CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_R, F_LDST_STORE | F_GPRSIZE_IN_Q),
>>>> + CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt,
>>>> ADDR_SIMM9), QL_LDST_R, F_LDST_LOAD | F_GPRSIZE_IN_Q),
>>>> + CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2
>>>> (Rt, ADDR_SIMM9), QL_LDST_X32, F_LDST_LOAD),
>>>> /* Load/store Allocation Tag instructions. */
>>>> MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>>> MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>>> MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>>> MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>>> - MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>>> - MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>>> - MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>>> - MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
>>>> + MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>>>> + MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>>>> + MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>>>> + MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2
>>>> (Rt_SP, ADDR_SIMM13), QL_LDST_AT, F_LDST_STORE),
>>>
>>> These store an allocation tag, rather than storing the contents of the
>>> registers to regular memory. I think they should be put in an "other"
>>> category.
>>>
>>
>> I have changed these to F_SUBCLASS_OTHER. And on the ginsn generation
>> side, no memory ginsn op is generated (address calculation op is
>> generated if writeback is in effect as usual). Also added code
>> comments in tc-aarch-ginsn.c to clarify that skipping memory ops is
>> needed because the memory op affects the tag only.
>>
>>>> /* Load/store register (unsigned immediate). */
>>>> - CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS,
>>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
>>>> - CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS,
>>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
>>>> - CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos,
>>>> OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE),
>>>> - CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS,
>>>> OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
>>>> - CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS,
>>>> OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0),
>>>> - CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS,
>>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
>>>> - CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS,
>>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0),
>>>> - CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos,
>>>> OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE),
>>>> - CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS,
>>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
>>>> - CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS,
>>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q),
>>>> - CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos,
>>>> OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0),
>>>> - CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS,
>>>> OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0),
>>>> + CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS,
>>>> OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, F_LDST_STORE),
>>>
>>> AFAICT, patch 7/8 doesn't distinguish between byte stores and other
>>> sizes
>>> of store, even though this matters for CFI purposes. I think we should
>>> use an "other" category for anything that isn't a full load or store of
>>> a W register, X register, or FPR.
>>>
>>> Patch 7/8 shouldn't treat a W, B, H or S load or store as being enough
>>> for CFI purposes. The width has to be 8 bytes or more.
>>>
>>> Similarly, for LDP & STP, 7/8 should punt on W and S loads and stores,
>>> since they cannot implement a full save & restore for CFI purposes.
>>>
>>
>> Currently, the checks in dw2gencfi.c issue a warning if CFI offsets
>> are not a multiple of 8. So if user says --scfi=experimental for
>> stp s8, s9, [sp, 96]
>> they get an error:
>> Error: register save offset not a multiple of 8
>>
>> I was sort of relying on the above for some cases, while leaving the
>> users on their own for other cases. E.g, No error is issued if the
>> user does a save/restore of S register like so:
>> str s8, [sp, 96]
>>
>> Hmm, I could punt on W and S by not creating ginsn mem ops for them
>> altogether. Should the user be warned though ? How about something
>> like :
>> Warning: ignored probable save/restore op of less than 8-byte
>>
>> As this will be diagnosed by the ginsn creation code, the warning will
>> be issued when a load / store:
>> - of callee-saved register,
>> - of width < 8 bytes,
>> - and with addr_reg involving REG_SP or REG_FP is seen
>>
>> To avoid the high number of warnings, we could warn once (for the
>> first sub 8-byte applicable load/store). Do you think the warning is
>> useful ?
>>
>
> I am inclining towards working on this as a follow-up patch (not
> included in V5). Punting on S and W registers should be easy, but I
> would like to test it out to be sure I am not misssing anything.
>
> Further, I am tending towards not adding a new warning for this in the
> current infrastructure at all (mostly because there will be false
> positives which dilutes the eficacy of the warning). IIUC, the usage of
> W and S registers to save/restore callee-saved registers is not
> ABI-conformant anyway.
>
> Please let me know your opinion on defering this as a follow-up patch.
>
This is hopefully addressed in V5 that I will be sending soon.
No warning yet, but we will now punt on S and W registers.
Thanks
Indu
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns
2024-07-01 2:53 [PATCH,V4 0/8] Add SCFI support for aarch64 Indu Bhagat
` (2 preceding siblings ...)
2024-07-01 2:53 ` [PATCH,V4 3/8] opcodes: aarch64: flags to denote subclasses of ldst insns Indu Bhagat
@ 2024-07-01 2:54 ` Indu Bhagat
2024-07-01 18:13 ` Richard Sandiford
2024-07-01 2:54 ` [PATCH,V4 5/8] opcodes: aarch64: flags to denote subclasses of uncond branches Indu Bhagat
` (3 subsequent siblings)
7 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-01 2:54 UTC (permalink / raw)
To: binutils; +Cc: richard.sandiford, Richard.Earnshaw, Indu Bhagat
[Changes in V4]
- Specify subclasses only for those iclasses relevent to SCFI:
addsub_imm, and addsub_ext
[End of changes in V4]
[No changes in V3]
[New in V2]
Use the three new subclass flags: F_ARITH_ADD, F_ARITH_SUB,
F_ARITH_MOV, to indicate add, sub and mov ops respectively.
opcodes/
* aarch64-tbl.h: Use the new F_ARITH_* flags.
---
opcodes/aarch64-tbl.h | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 6e523db6277..57727254d43 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3205,22 +3205,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
/* Add/subtract (extended register). */
- CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
- CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
- CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
- CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
- CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
- CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
+ CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
+ CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
+ CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF),
+ CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
/* Add/subtract (immediate). */
- CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
- CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF),
- CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
- CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
- CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
- CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
- CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
- MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
- MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
+ CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
+ CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
+ CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
+ CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_SF),
+ CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
+ MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_ADD),
+ MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_SUB),
/* Add/subtract (shifted register). */
CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
--
2.43.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns
2024-07-01 2:54 ` [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns Indu Bhagat
@ 2024-07-01 18:13 ` Richard Sandiford
2024-07-11 5:47 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Richard Sandiford @ 2024-07-01 18:13 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> [Changes in V4]
> - Specify subclasses only for those iclasses relevent to SCFI:
> addsub_imm, and addsub_ext
> [End of changes in V4]
>
> [No changes in V3]
> [New in V2]
>
> Use the three new subclass flags: F_ARITH_ADD, F_ARITH_SUB,
> F_ARITH_MOV, to indicate add, sub and mov ops respectively.
>
> opcodes/
> * aarch64-tbl.h: Use the new F_ARITH_* flags.
> ---
> opcodes/aarch64-tbl.h | 30 +++++++++++++++---------------
> 1 file changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 6e523db6277..57727254d43 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -3205,22 +3205,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
> CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
> /* Add/subtract (extended register). */
> - CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
> - CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
> - CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
> - CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
> - CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
> - CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
> + CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
> + CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
> + CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
> + CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF),
> + CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
> + CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
> /* Add/subtract (immediate). */
> - CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
> - CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF),
> - CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
> - CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
> - CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
> - CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
> - CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
> - MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
> - MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
> + CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
> + CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
> + CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
> + CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
> + CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_SF),
> + CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
> + CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
> + MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_ADD),
> + MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_SUB),
I suppose this raises the question: is GINSN_TYPE_ADD specifically
for address arithmetic, or is it a normal addition? If it's a
normal addition then ADDG doesn't really fit. If it's address
arithmetic then it might be worth making the names more explicit.
Thanks,
Richard
> /* Add/subtract (shifted register). */
> CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
> CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns
2024-07-01 18:13 ` Richard Sandiford
@ 2024-07-11 5:47 ` Indu Bhagat
2024-07-11 12:52 ` Richard Sandiford
0 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-11 5:47 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/1/24 11:13, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> [Changes in V4]
>> - Specify subclasses only for those iclasses relevent to SCFI:
>> addsub_imm, and addsub_ext
>> [End of changes in V4]
>>
>> [No changes in V3]
>> [New in V2]
>>
>> Use the three new subclass flags: F_ARITH_ADD, F_ARITH_SUB,
>> F_ARITH_MOV, to indicate add, sub and mov ops respectively.
>>
>> opcodes/
>> * aarch64-tbl.h: Use the new F_ARITH_* flags.
>> ---
>> opcodes/aarch64-tbl.h | 30 +++++++++++++++---------------
>> 1 file changed, 15 insertions(+), 15 deletions(-)
>>
>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>> index 6e523db6277..57727254d43 100644
>> --- a/opcodes/aarch64-tbl.h
>> +++ b/opcodes/aarch64-tbl.h
>> @@ -3205,22 +3205,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>> CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
>> CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
>> /* Add/subtract (extended register). */
>> - CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>> - CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>> - CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>> - CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>> - CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>> - CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>> + CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
>> + CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>> + CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>> + CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF),
>> + CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>> + CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>> /* Add/subtract (immediate). */
>> - CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>> - CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF),
>> - CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>> - CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>> - CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
>> - CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>> - CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>> - MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>> - MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>> + CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>> + CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
>> + CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>> + CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>> + CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_SF),
>> + CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>> + CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>> + MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_ADD),
>> + MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_SUB),
>
> I suppose this raises the question: is GINSN_TYPE_ADD specifically
> for address arithmetic, or is it a normal addition? If it's a
> normal addition then ADDG doesn't really fit. If it's address
> arithmetic then it might be worth making the names more explicit.
>
For SCFI, we are interested in the insns which may have manipulated
REG_SP and REG_FP, so the intention is around address arithmetic.
ATM, we generate ginsn for _all_ add, sub (and mov) in the iclass
addsub_imm, addsub_ext (and movewide..), irrespective of whether the
destination is REG_SP/REG_FP or not.
IOW, "keep the ginsn creation code not tied to GINSN_GEN_SCFI" has been
followed where affordable.
I dont have a good new name (F_ADDR_ARITH_* ?); I personally find
F_ADDR_ARITH_* unsuitable because this new name ties the
subclassification to the current usecase (SCFI and its need to see those
address arithmetic). But may be I am overthinking.
If you have a suggestion, please let me know.
Thanks
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns
2024-07-11 5:47 ` Indu Bhagat
@ 2024-07-11 12:52 ` Richard Sandiford
2024-07-11 17:58 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Richard Sandiford @ 2024-07-11 12:52 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> On 7/1/24 11:13, Richard Sandiford wrote:
>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>> [Changes in V4]
>>> - Specify subclasses only for those iclasses relevent to SCFI:
>>> addsub_imm, and addsub_ext
>>> [End of changes in V4]
>>>
>>> [No changes in V3]
>>> [New in V2]
>>>
>>> Use the three new subclass flags: F_ARITH_ADD, F_ARITH_SUB,
>>> F_ARITH_MOV, to indicate add, sub and mov ops respectively.
>>>
>>> opcodes/
>>> * aarch64-tbl.h: Use the new F_ARITH_* flags.
>>> ---
>>> opcodes/aarch64-tbl.h | 30 +++++++++++++++---------------
>>> 1 file changed, 15 insertions(+), 15 deletions(-)
>>>
>>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>>> index 6e523db6277..57727254d43 100644
>>> --- a/opcodes/aarch64-tbl.h
>>> +++ b/opcodes/aarch64-tbl.h
>>> @@ -3205,22 +3205,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>>> CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
>>> CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
>>> /* Add/subtract (extended register). */
>>> - CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>>> - CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>>> - CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>>> - CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>>> - CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>>> - CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>>> + CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
>>> + CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>> + CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>> + CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF),
>>> + CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>>> + CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>> /* Add/subtract (immediate). */
>>> - CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>> - CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF),
>>> - CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>> - CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>>> - CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
>>> - CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>> - CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>>> - MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>>> - MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>>> + CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>> + CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
>>> + CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>> + CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>> + CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_SF),
>>> + CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>>> + CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>> + MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_ADD),
>>> + MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_SUB),
>>
>> I suppose this raises the question: is GINSN_TYPE_ADD specifically
>> for address arithmetic, or is it a normal addition? If it's a
>> normal addition then ADDG doesn't really fit. If it's address
>> arithmetic then it might be worth making the names more explicit.
>>
>
> For SCFI, we are interested in the insns which may have manipulated
> REG_SP and REG_FP, so the intention is around address arithmetic.
>
> ATM, we generate ginsn for _all_ add, sub (and mov) in the iclass
> addsub_imm, addsub_ext (and movewide..), irrespective of whether the
> destination is REG_SP/REG_FP or not.
>
> IOW, "keep the ginsn creation code not tied to GINSN_GEN_SCFI" has been
> followed where affordable.
I think this is useful even for SCFI, since large stack allocations could
be done using intermediate calculations into temporary registers.
> I dont have a good new name (F_ADDR_ARITH_* ?); I personally find
> F_ADDR_ARITH_* unsuitable because this new name ties the
> subclassification to the current usecase (SCFI and its need to see those
> address arithmetic). But may be I am overthinking.
>
> If you have a suggestion, please let me know.
The distinction between a full addition and address addition sounds
like it could be generally useful, beyond just SCFI. How abot having
both GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR? Places that are only
interested in address arithmetic can treat both types in the same way.
Types that want natural addition can handle GINSN_TYPE_ADD only.
Thanks,
Richard
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns
2024-07-11 12:52 ` Richard Sandiford
@ 2024-07-11 17:58 ` Indu Bhagat
2024-07-11 18:43 ` Richard Sandiford
0 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-11 17:58 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/11/24 05:52, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> On 7/1/24 11:13, Richard Sandiford wrote:
>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>> [Changes in V4]
>>>> - Specify subclasses only for those iclasses relevent to SCFI:
>>>> addsub_imm, and addsub_ext
>>>> [End of changes in V4]
>>>>
>>>> [No changes in V3]
>>>> [New in V2]
>>>>
>>>> Use the three new subclass flags: F_ARITH_ADD, F_ARITH_SUB,
>>>> F_ARITH_MOV, to indicate add, sub and mov ops respectively.
>>>>
>>>> opcodes/
>>>> * aarch64-tbl.h: Use the new F_ARITH_* flags.
>>>> ---
>>>> opcodes/aarch64-tbl.h | 30 +++++++++++++++---------------
>>>> 1 file changed, 15 insertions(+), 15 deletions(-)
>>>>
>>>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>>>> index 6e523db6277..57727254d43 100644
>>>> --- a/opcodes/aarch64-tbl.h
>>>> +++ b/opcodes/aarch64-tbl.h
>>>> @@ -3205,22 +3205,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>>>> CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
>>>> CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
>>>> /* Add/subtract (extended register). */
>>>> - CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>>>> - CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>>>> - CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>>>> - CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>>>> - CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>>>> - CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>>>> + CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
>>>> + CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>> + CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>> + CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF),
>>>> + CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>>>> + CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>> /* Add/subtract (immediate). */
>>>> - CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>> - CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF),
>>>> - CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>> - CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>>>> - CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
>>>> - CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>> - CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>>>> - MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>>>> - MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>>>> + CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>> + CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
>>>> + CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>> + CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>> + CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_SF),
>>>> + CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>>>> + CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>> + MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_ADD),
>>>> + MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_SUB),
>>>
>>> I suppose this raises the question: is GINSN_TYPE_ADD specifically
>>> for address arithmetic, or is it a normal addition? If it's a
>>> normal addition then ADDG doesn't really fit. If it's address
>>> arithmetic then it might be worth making the names more explicit.
>>>
>>
Apologies, my brain tricked me into reading the above as "is F_ARITH_ADD
specifically for address arithmetic or is it normal addition?" all this
time until now, and hence, what might appear as a confused reply in the
previous email.
Hopefully I have not digressed too far.
>> For SCFI, we are interested in the insns which may have manipulated
>> REG_SP and REG_FP, so the intention is around address arithmetic.
>>
>> ATM, we generate ginsn for _all_ add, sub (and mov) in the iclass
>> addsub_imm, addsub_ext (and movewide..), irrespective of whether the
>> destination is REG_SP/REG_FP or not.
>>
>> IOW, "keep the ginsn creation code not tied to GINSN_GEN_SCFI" has been
>> followed where affordable.
>
> I think this is useful even for SCFI, since large stack allocations could
> be done using intermediate calculations into temporary registers.
>
Yes to using intermediate calculations into temporary registers. This
is true especially for aarch64 where we may see patterns like:
mov x16, 4384
add sp, sp, x16
(which I would like to support for SCFI/aarch64 next. Adding support
for this means enabling some data flow for sp traceability; SCFI does
not have much of data flow ATM.)
But I am not sure if the GINSN_TYPE_ADD / GINSN_TYPE_ADD_ADDR
demarcation will be useful for SCFI because: effectively GINSN_TYPE_ADD
with dest as REG_SP/REG_FP is address arithmetic for SCFI. SCFI can (and
does) ignore the rest of GINSN_TYPE_ADD / GINSN_TYPE_SUB ops.
>> I dont have a good new name (F_ADDR_ARITH_* ?); I personally find
>> F_ADDR_ARITH_* unsuitable because this new name ties the
>> subclassification to the current usecase (SCFI and its need to see those
>> address arithmetic). But may be I am overthinking.
>>
>> If you have a suggestion, please let me know.
>
> The distinction between a full addition and address addition sounds
> like it could be generally useful, beyond just SCFI. How abot having
> both GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR? Places that are only
> interested in address arithmetic can treat both types in the same way.
> Types that want natural addition can handle GINSN_TYPE_ADD only.
>
The distinction may be useful for usecases other than SCFI, true;
depending on the usecase.
I think my nervousness with the explicit demarcation using two type of
ginsns, GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR now, is on the generation
side:
- Wont we simply look at the destination register being REG_SP /
REG_FP in some cases to pick GINSN_TYPE_ADD_ADDR instead of
GINSN_TYPE_ADD. If so, GINSN_TYPE_ADD_ADDR contains no more information
than GINSN_TYPE_ADD in those cases.
- Also, for other ISAs, I am not sure ATM if this will make things
more complicated on the ginsn creation side as other rules to pick
GINSN_TYPE_ADD_ADDR vs GINSN_TYPE_ADD may be involved. And not all might
be implementable at the time of ginsn creation (as some def-use analysis
may be necessary to demarcate them?)
Indu
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns
2024-07-11 17:58 ` Indu Bhagat
@ 2024-07-11 18:43 ` Richard Sandiford
2024-07-12 12:53 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Richard Sandiford @ 2024-07-11 18:43 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> On 7/11/24 05:52, Richard Sandiford wrote:
>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>> On 7/1/24 11:13, Richard Sandiford wrote:
>>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>>> [Changes in V4]
>>>>> - Specify subclasses only for those iclasses relevent to SCFI:
>>>>> addsub_imm, and addsub_ext
>>>>> [End of changes in V4]
>>>>>
>>>>> [No changes in V3]
>>>>> [New in V2]
>>>>>
>>>>> Use the three new subclass flags: F_ARITH_ADD, F_ARITH_SUB,
>>>>> F_ARITH_MOV, to indicate add, sub and mov ops respectively.
>>>>>
>>>>> opcodes/
>>>>> * aarch64-tbl.h: Use the new F_ARITH_* flags.
>>>>> ---
>>>>> opcodes/aarch64-tbl.h | 30 +++++++++++++++---------------
>>>>> 1 file changed, 15 insertions(+), 15 deletions(-)
>>>>>
>>>>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>>>>> index 6e523db6277..57727254d43 100644
>>>>> --- a/opcodes/aarch64-tbl.h
>>>>> +++ b/opcodes/aarch64-tbl.h
>>>>> @@ -3205,22 +3205,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>>>>> CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
>>>>> CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
>>>>> /* Add/subtract (extended register). */
>>>>> - CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>>>>> - CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>>>>> - CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>>>>> - CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>>>>> - CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>>>>> - CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>>>>> + CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
>>>>> + CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>>> + CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>>> + CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF),
>>>>> + CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>>>>> + CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>>> /* Add/subtract (immediate). */
>>>>> - CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>>> - CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF),
>>>>> - CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>>> - CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>>>>> - CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
>>>>> - CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>>> - CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>>>>> - MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>>>>> - MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>>>>> + CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>>> + CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
>>>>> + CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>>> + CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>>> + CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_SF),
>>>>> + CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>>>>> + CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>>> + MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_ADD),
>>>>> + MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_SUB),
>>>>
>>>> I suppose this raises the question: is GINSN_TYPE_ADD specifically
>>>> for address arithmetic, or is it a normal addition? If it's a
>>>> normal addition then ADDG doesn't really fit. If it's address
>>>> arithmetic then it might be worth making the names more explicit.
>>>>
>>>
>
>
> Apologies, my brain tricked me into reading the above as "is F_ARITH_ADD
> specifically for address arithmetic or is it normal addition?" all this
> time until now, and hence, what might appear as a confused reply in the
> previous email.
>
> Hopefully I have not digressed too far.
>
>>> For SCFI, we are interested in the insns which may have manipulated
>>> REG_SP and REG_FP, so the intention is around address arithmetic.
>>>
>>> ATM, we generate ginsn for _all_ add, sub (and mov) in the iclass
>>> addsub_imm, addsub_ext (and movewide..), irrespective of whether the
>>> destination is REG_SP/REG_FP or not.
>>>
>>> IOW, "keep the ginsn creation code not tied to GINSN_GEN_SCFI" has been
>>> followed where affordable.
>>
>> I think this is useful even for SCFI, since large stack allocations could
>> be done using intermediate calculations into temporary registers.
>>
>
> Yes to using intermediate calculations into temporary registers. This
> is true especially for aarch64 where we may see patterns like:
>
> mov x16, 4384
> add sp, sp, x16
>
> (which I would like to support for SCFI/aarch64 next. Adding support
> for this means enabling some data flow for sp traceability; SCFI does
> not have much of data flow ATM.)
>
> But I am not sure if the GINSN_TYPE_ADD / GINSN_TYPE_ADD_ADDR
> demarcation will be useful for SCFI because: effectively GINSN_TYPE_ADD
> with dest as REG_SP/REG_FP is address arithmetic for SCFI. SCFI can (and
> does) ignore the rest of GINSN_TYPE_ADD / GINSN_TYPE_SUB ops.
>
>>> I dont have a good new name (F_ADDR_ARITH_* ?); I personally find
>>> F_ADDR_ARITH_* unsuitable because this new name ties the
>>> subclassification to the current usecase (SCFI and its need to see those
>>> address arithmetic). But may be I am overthinking.
>>>
>>> If you have a suggestion, please let me know.
>>
>> The distinction between a full addition and address addition sounds
>> like it could be generally useful, beyond just SCFI. How abot having
>> both GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR? Places that are only
>> interested in address arithmetic can treat both types in the same way.
>> Types that want natural addition can handle GINSN_TYPE_ADD only.
>>
>
> The distinction may be useful for usecases other than SCFI, true;
> depending on the usecase.
>
> I think my nervousness with the explicit demarcation using two type of
> ginsns, GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR now, is on the generation
> side:
>
> - Wont we simply look at the destination register being REG_SP /
> REG_FP in some cases to pick GINSN_TYPE_ADD_ADDR instead of
> GINSN_TYPE_ADD. If so, GINSN_TYPE_ADD_ADDR contains no more information
> than GINSN_TYPE_ADD in those cases.
I was thinking the distinction between GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR
would be based on the opcode rather than the register. ADDG would be
GINSN_TYPE_ADD_ADDR (since it adds "enough bits" to support address
arithmetic, but does not carry into the tag bits). ADD would instead be
GINSN_TYPE_ADD (since it's a full-register add). Both mappings would be
independent of the destination register.
I'm just nervous about saying that ADD and ADDG are the same operation,
unless that operation is specifically described as being for addresses only.
Another option would be to leave ADDG and SUBG as "other" for the
initial patch and deal with them as a follow-on.
> - Also, for other ISAs, I am not sure ATM if this will make things
> more complicated on the ginsn creation side as other rules to pick
> GINSN_TYPE_ADD_ADDR vs GINSN_TYPE_ADD may be involved. And not all might
> be implementable at the time of ginsn creation (as some def-use analysis
> may be necessary to demarcate them?)
I think all other ISAs would just use GINSN_TYPE_ADD, unless they're
doing a similar tag operation to ADDG/SUBG.
Thanks,
Richard
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns
2024-07-11 18:43 ` Richard Sandiford
@ 2024-07-12 12:53 ` Indu Bhagat
0 siblings, 0 replies; 29+ messages in thread
From: Indu Bhagat @ 2024-07-12 12:53 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/11/24 11:43, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> On 7/11/24 05:52, Richard Sandiford wrote:
>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>> On 7/1/24 11:13, Richard Sandiford wrote:
>>>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>>>> [Changes in V4]
>>>>>> - Specify subclasses only for those iclasses relevent to SCFI:
>>>>>> addsub_imm, and addsub_ext
>>>>>> [End of changes in V4]
>>>>>>
>>>>>> [No changes in V3]
>>>>>> [New in V2]
>>>>>>
>>>>>> Use the three new subclass flags: F_ARITH_ADD, F_ARITH_SUB,
>>>>>> F_ARITH_MOV, to indicate add, sub and mov ops respectively.
>>>>>>
>>>>>> opcodes/
>>>>>> * aarch64-tbl.h: Use the new F_ARITH_* flags.
>>>>>> ---
>>>>>> opcodes/aarch64-tbl.h | 30 +++++++++++++++---------------
>>>>>> 1 file changed, 15 insertions(+), 15 deletions(-)
>>>>>>
>>>>>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>>>>>> index 6e523db6277..57727254d43 100644
>>>>>> --- a/opcodes/aarch64-tbl.h
>>>>>> +++ b/opcodes/aarch64-tbl.h
>>>>>> @@ -3205,22 +3205,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>>>>>> CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
>>>>>> CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
>>>>>> /* Add/subtract (extended register). */
>>>>>> - CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>>>>>> - CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>>>>>> - CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>>>>>> - CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
>>>>>> - CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
>>>>>> - CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
>>>>>> + CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
>>>>>> + CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>>>> + CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>>>> + CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF),
>>>>>> + CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>>>>>> + CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>>>> /* Add/subtract (immediate). */
>>>>>> - CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>>>> - CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF),
>>>>>> - CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>>>> - CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>>>>>> - CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
>>>>>> - CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
>>>>>> - CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
>>>>>> - MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>>>>>> - MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
>>>>>> + CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>>>> + CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
>>>>>> + CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
>>>>>> + CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>>>> + CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_SF),
>>>>>> + CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
>>>>>> + CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
>>>>>> + MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_ADD),
>>>>>> + MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, F_ARITH_SUB),
>>>>>
>>>>> I suppose this raises the question: is GINSN_TYPE_ADD specifically
>>>>> for address arithmetic, or is it a normal addition? If it's a
>>>>> normal addition then ADDG doesn't really fit. If it's address
>>>>> arithmetic then it might be worth making the names more explicit.
>>>>>
>>>>
>>
>>
>> Apologies, my brain tricked me into reading the above as "is F_ARITH_ADD
>> specifically for address arithmetic or is it normal addition?" all this
>> time until now, and hence, what might appear as a confused reply in the
>> previous email.
>>
>> Hopefully I have not digressed too far.
>>
>>>> For SCFI, we are interested in the insns which may have manipulated
>>>> REG_SP and REG_FP, so the intention is around address arithmetic.
>>>>
>>>> ATM, we generate ginsn for _all_ add, sub (and mov) in the iclass
>>>> addsub_imm, addsub_ext (and movewide..), irrespective of whether the
>>>> destination is REG_SP/REG_FP or not.
>>>>
>>>> IOW, "keep the ginsn creation code not tied to GINSN_GEN_SCFI" has been
>>>> followed where affordable.
>>>
>>> I think this is useful even for SCFI, since large stack allocations could
>>> be done using intermediate calculations into temporary registers.
>>>
>>
>> Yes to using intermediate calculations into temporary registers. This
>> is true especially for aarch64 where we may see patterns like:
>>
>> mov x16, 4384
>> add sp, sp, x16
>>
>> (which I would like to support for SCFI/aarch64 next. Adding support
>> for this means enabling some data flow for sp traceability; SCFI does
>> not have much of data flow ATM.)
>>
>> But I am not sure if the GINSN_TYPE_ADD / GINSN_TYPE_ADD_ADDR
>> demarcation will be useful for SCFI because: effectively GINSN_TYPE_ADD
>> with dest as REG_SP/REG_FP is address arithmetic for SCFI. SCFI can (and
>> does) ignore the rest of GINSN_TYPE_ADD / GINSN_TYPE_SUB ops.
>>
>>>> I dont have a good new name (F_ADDR_ARITH_* ?); I personally find
>>>> F_ADDR_ARITH_* unsuitable because this new name ties the
>>>> subclassification to the current usecase (SCFI and its need to see those
>>>> address arithmetic). But may be I am overthinking.
>>>>
>>>> If you have a suggestion, please let me know.
>>>
>>> The distinction between a full addition and address addition sounds
>>> like it could be generally useful, beyond just SCFI. How abot having
>>> both GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR? Places that are only
>>> interested in address arithmetic can treat both types in the same way.
>>> Types that want natural addition can handle GINSN_TYPE_ADD only.
>>>
>>
>> The distinction may be useful for usecases other than SCFI, true;
>> depending on the usecase.
>>
>> I think my nervousness with the explicit demarcation using two type of
>> ginsns, GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR now, is on the generation
>> side:
>>
>> - Wont we simply look at the destination register being REG_SP /
>> REG_FP in some cases to pick GINSN_TYPE_ADD_ADDR instead of
>> GINSN_TYPE_ADD. If so, GINSN_TYPE_ADD_ADDR contains no more information
>> than GINSN_TYPE_ADD in those cases.
>
> I was thinking the distinction between GINSN_TYPE_ADD and GINSN_TYPE_ADD_ADDR
> would be based on the opcode rather than the register. ADDG would be
> GINSN_TYPE_ADD_ADDR (since it adds "enough bits" to support address
> arithmetic, but does not carry into the tag bits). ADD would instead be
> GINSN_TYPE_ADD (since it's a full-register add). Both mappings would be
> independent of the destination register.
>
> I'm just nervous about saying that ADD and ADDG are the same operation,
> unless that operation is specifically described as being for addresses only.
>
> Another option would be to leave ADDG and SUBG as "other" for the
> initial patch and deal with them as a follow-on.
>
Right. Your concern is valid. ADDG/SUBG should not be tagged as
F_ARITH_ADD/F_ARITH_SUB. I have changed these to F_SUBCLASS_OTHER.
In hindsight, in V4, tc-aarch64-ginsn.c would generate vanilla
GINSN_TYPE_ADD/GINSN_TYPE_SUB with no regard to the _scaling_ (As per
specification: "ADDG adds an immediate value scaled by the Tag granule
to the address in the source register").
Now in V5, we will generate GINSN_TYPE_OTHER (via the
aarch64_ginsn_unhandled () codepath) if an addg/subg is seen to affect
correctness.
>> - Also, for other ISAs, I am not sure ATM if this will make things
>> more complicated on the ginsn creation side as other rules to pick
>> GINSN_TYPE_ADD_ADDR vs GINSN_TYPE_ADD may be involved. And not all might
>> be implementable at the time of ginsn creation (as some def-use analysis
>> may be necessary to demarcate them?)
>
> I think all other ISAs would just use GINSN_TYPE_ADD, unless they're
> doing a similar tag operation to ADDG/SUBG.
>
> Thanks,
> Richard
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH,V4 5/8] opcodes: aarch64: flags to denote subclasses of uncond branches
2024-07-01 2:53 [PATCH,V4 0/8] Add SCFI support for aarch64 Indu Bhagat
` (3 preceding siblings ...)
2024-07-01 2:54 ` [PATCH,V4 4/8] opcodes: aarch64: flags to denote subclasses of arithmetic insns Indu Bhagat
@ 2024-07-01 2:54 ` Indu Bhagat
2024-07-01 2:54 ` [PATCH,V4 6/8] opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.c Indu Bhagat
` (2 subsequent siblings)
7 siblings, 0 replies; 29+ messages in thread
From: Indu Bhagat @ 2024-07-01 2:54 UTC (permalink / raw)
To: binutils; +Cc: richard.sandiford, Richard.Earnshaw, Indu Bhagat
[Changes in V4]
- Use F_SUBCLASS_OTHER for instructions where F_BRANCH_CALL or
F_BRANCH_RET does not apply.
[End of changes in V4]
[No changes in V3]
[New in V2]
Use the two new subclass flags: F_BRANCH_CALL, F_BRANCH_RET, to indicate
call to and return from subroutine respectively.
opcodes/
* aarch64-tbl.h: Use the new F_BRANCH_* flags.
---
opcodes/aarch64-tbl.h | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 57727254d43..9ce39b9fb77 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3863,26 +3863,26 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV),
CORE_INSN ("lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV),
/* Unconditional branch (immediate). */
- CORE_INSN ("b", 0x14000000, 0xfc000000, branch_imm, OP_B, OP1 (ADDR_PCREL26), QL_PCREL_26, 0),
- CORE_INSN ("bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, OP1 (ADDR_PCREL26), QL_PCREL_26, 0),
+ CORE_INSN ("b", 0x14000000, 0xfc000000, branch_imm, OP_B, OP1 (ADDR_PCREL26), QL_PCREL_26, F_SUBCLASS_OTHER),
+ CORE_INSN ("bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, OP1 (ADDR_PCREL26), QL_PCREL_26, F_BRANCH_CALL),
/* Unconditional branch (register). */
- CORE_INSN ("br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0),
- CORE_INSN ("blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0),
- CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)),
- CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
- CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
- PAUTH_INSN ("braa", 0xd71f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
- PAUTH_INSN ("brab", 0xd71f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
- PAUTH_INSN ("blraa", 0xd73f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
- PAUTH_INSN ("blrab", 0xd73f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
- PAUTH_INSN ("braaz", 0xd61f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
- PAUTH_INSN ("brabz", 0xd61f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
- PAUTH_INSN ("blraaz", 0xd63f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
- PAUTH_INSN ("blrabz", 0xd63f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
- PAUTH_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
- PAUTH_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
- PAUTH_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
- PAUTH_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
+ CORE_INSN ("br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_SUBCLASS_OTHER),
+ CORE_INSN ("blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_BRANCH_CALL),
+ CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_BRANCH_RET | F_OPD0_OPT | F_DEFAULT (30)),
+ CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, F_BRANCH_RET),
+ CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, F_SUBCLASS_OTHER),
+ PAUTH_INSN ("braa", 0xd71f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, F_SUBCLASS_OTHER),
+ PAUTH_INSN ("brab", 0xd71f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, F_SUBCLASS_OTHER),
+ PAUTH_INSN ("blraa", 0xd73f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, F_BRANCH_CALL),
+ PAUTH_INSN ("blrab", 0xd73f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, F_BRANCH_CALL),
+ PAUTH_INSN ("braaz", 0xd61f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, F_SUBCLASS_OTHER),
+ PAUTH_INSN ("brabz", 0xd61f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, F_SUBCLASS_OTHER),
+ PAUTH_INSN ("blraaz", 0xd63f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, F_BRANCH_CALL),
+ PAUTH_INSN ("blrabz", 0xd63f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, F_BRANCH_CALL),
+ PAUTH_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, F_BRANCH_RET),
+ PAUTH_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, F_BRANCH_RET),
+ PAUTH_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, F_BRANCH_RET),
+ PAUTH_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, F_BRANCH_RET),
/* Compare & branch (immediate). */
CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF),
CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF),
--
2.43.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [PATCH,V4 6/8] opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.c
2024-07-01 2:53 [PATCH,V4 0/8] Add SCFI support for aarch64 Indu Bhagat
` (4 preceding siblings ...)
2024-07-01 2:54 ` [PATCH,V4 5/8] opcodes: aarch64: flags to denote subclasses of uncond branches Indu Bhagat
@ 2024-07-01 2:54 ` Indu Bhagat
2024-07-01 2:54 ` [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI Indu Bhagat
2024-07-01 2:54 ` [PATCH,V4 8/8] gas: aarch64: testsuite: add new tests " Indu Bhagat
7 siblings, 0 replies; 29+ messages in thread
From: Indu Bhagat @ 2024-07-01 2:54 UTC (permalink / raw)
To: binutils; +Cc: richard.sandiford, Richard.Earnshaw, Indu Bhagat
[New in V4]
Enforce some checks on the newly added subclass flags:
- If a subclass is set of one insn of an iclass, every insn of that
iclass must have non-zero subclass field.
- For all other iclasses, the subclass bits are zero for all insns.
include/
* opcode/aarch64.h (enum aarch64_insn_class): Identify the
maximum iclass enum value.
opcodes/
* aarch64-gen.c (iclass_has_subclasses_p): New array of bool.
(read_table): Enforce checks on subclass flags.
---
include/opcode/aarch64.h | 3 ++-
opcodes/aarch64-gen.c | 19 +++++++++++++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c3ac1326b9c..82171b037f6 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1082,7 +1082,8 @@ enum aarch64_insn_class
sve2_urqvs,
sve_index1,
rcpc3,
- lut
+ lut,
+ last_iclass = lut
};
/* Opcode enumerators. */
diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
index 02dcde1f676..2473f6704ce 100644
--- a/opcodes/aarch64-gen.c
+++ b/opcodes/aarch64-gen.c
@@ -123,6 +123,8 @@ get_aarch64_opcode (const opcode_node *opcode_node)
return &index2table (opcode_node->index)[real_index (opcode_node->index)];
}
+static bool iclass_has_subclasses_p[last_iclass];
+
static void
read_table (const struct aarch64_opcode* table)
{
@@ -181,6 +183,9 @@ read_table (const struct aarch64_opcode* table)
++errors;
}
+ if (ent->flags & F_SUBCLASS)
+ iclass_has_subclasses_p[ent->iclass] = true;
+
*new_ent = new_opcode_node ();
(*new_ent)->opcode = ent->opcode;
(*new_ent)->mask = ent->mask;
@@ -188,6 +193,20 @@ read_table (const struct aarch64_opcode* table)
new_ent = &((*new_ent)->next);
} while ((++ent)->name);
+ ent = table;
+ do
+ {
+ /* If a subclass is set for one insn of an iclass, every insn of that
+ iclass must have non-zero subclass field. */
+ if ((iclass_has_subclasses_p[ent->iclass] && !(ent->flags & F_SUBCLASS))
+ || (!iclass_has_subclasses_p[ent->iclass] && (ent->flags & F_SUBCLASS)))
+ {
+ fprintf (stderr, "%s: unexpected subclass\n", ent->name);
+ ++errors;
+ }
+ ent++;
+ } while (ent->name);
+
if (errors)
{
fprintf (stderr, "%u errors, exiting\n", errors);
--
2.43.0
^ permalink raw reply [flat|nested] 29+ messages in thread* [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI
2024-07-01 2:53 [PATCH,V4 0/8] Add SCFI support for aarch64 Indu Bhagat
` (5 preceding siblings ...)
2024-07-01 2:54 ` [PATCH,V4 6/8] opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.c Indu Bhagat
@ 2024-07-01 2:54 ` Indu Bhagat
2024-07-01 19:49 ` Richard Sandiford
2024-07-01 2:54 ` [PATCH,V4 8/8] gas: aarch64: testsuite: add new tests " Indu Bhagat
7 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-01 2:54 UTC (permalink / raw)
To: binutils; +Cc: richard.sandiford, Richard.Earnshaw, Indu Bhagat
[Changes in V4]
- Use data types uniformly. Use 'unsigned int' instead of 'uint32_t'
for DWARF register numbers. Use offsetT where applicable.
- Minor code restructuring in aarch64_ginsn_safe_to_skip_p (). Move
common code out of switch case.
- Add FP/Advanced SIMD registers to callee-saved registers too.
Updated commit log to include some of the details.
- Check for opnd type AARCH64_OPND_QLF_W or AARCH64_OPND_QLF_S_S in
aarch64_ginsn_ldstp () to detect 32-bit word operations.
- Skip generating ginsns for movk, movz, movn. These do more work than
just simple mov; Skip generating ginsn altogether for these.
- ginsn_dw2_regnum () is now switch case on opnd_class. Each case
exposed by the current set of ginsn creation logic is handled.
- Skip Z register usage altogether for now. Skip sve_misc iclass but
error out if callee-saved FP/Advanced SIMD registers or stack
management are involved.
[End of changes in V4]
[No changes in V3]
[Changes in V2]
- Factored out the ginsn creation functionality from tc-aarch64.c into
tc-aarch64-ginsn.c.
- The switch case in aarch64_ginsn_new now is based on iclass rather
than (earlier) opcode.
- Rename aarch64_ginsn_jump / aarch64_ginsn_jump_cond to
aarch64_ginsn_branch_uncond / aarch64_ginsn_branch_cond respectively.
- Explicitly whitelist irg insn.
- Other minor code comment and readability fixes.
[End of changes in V2]
For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in
GAS works on the generic GAS insns (ginsns). This patch adds support in
the aarch64 backend to create ginsns for a subset of the supported
machine instructions. The subset includes the minimal necessary
instructions to ensure SCFI correctness:
- Any potential register saves and unsaves. Hence, process instructions
belonging to a variety of iclasses involving str, ldr, stp, ldp.
- Any change of flow instructions. This includes all conditional and
unconditional branches, call (bl, blr, etc.) and return.
- Most importantly, any instruction that could affect the two registers
of interest: REG_SP, REG_FP. This set includes all pre-indexed and
post-indexed memory operations, with writeback, on the stack. This
set must also include other instructions (e.g., arithmetic insns)
where the destination register is one of the afore-mentioned registers.
With respect to callee-saved registers in Aarch64, FP/Advanced SIMD
registers D8-D15 are included along with the relevant GPRs. Calculating
offsets for loads and stores especially for Q registers needs special
attention here.
As an example,
str q8, [sp, #16]
On big-endian:
STR Qn stores as a 128-bit integer (MSB first), hence, should record
D8 as being saved at sp+24 rather than sp+16.
On little-endian:
should record D8 as being saved at sp+16
D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used;
hence, they remain "interesting" for SCFI purposes in such cases. A CFI
save slot always represents the low 64 bits, regardless of whether a
save occurs on D, Q or Z registers. Currently, the ginsn creation
machinery can handle D and Q registers on little-endian and big-endian.
Apart from creating ginsn, another key responsibility of the backend is
to make sure there are safeguards in place to detect and alert if an
instruction of interest may have been skipped. This is done via
aarch64_ginsn_unhandled () (similar to the x86 backend). This function
, hence, is also intended to alert when future ISA changes may otherwise
render SCFI results incorrect, because of missing ginsns for the newly
added machine instructions.
At this time, becuase of the complexities wrt endianness in handling Z
register usage, skip sve_misc opclass altogether for now. The SCFI
machinery will error out (using the aarch64_ginsn_unhandled () code
path) though if Z register usage affects correctness.
The current SCFI machinery does not currently synthesize the
PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame. The
support for this is planned for near future.
SCFI is enabled for ELF targets only.
gas/
* config/tc-aarch64-ginsn.c: New file.
* config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c
file. Invoke aarch64_ginsn_new.
* config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI
enablement.
(TARGET_USE_SCFI): Likewise.
(SCFI_MAX_REG_ID): New definition.
(REG_FP): Likewise.
(REG_LR): Likewise.
(REG_SP): Likewise.
(SCFI_INIT_CFA_OFFSET): Likewise.
(SCFI_CALLEE_SAVED_REG_P): Likewise.
(aarch64_scfi_callee_saved_p): New declaration.
---
gas/config/tc-aarch64-ginsn.c | 797 ++++++++++++++++++++++++++++++++++
gas/config/tc-aarch64.c | 15 +
gas/config/tc-aarch64.h | 21 +
3 files changed, 833 insertions(+)
create mode 100644 gas/config/tc-aarch64-ginsn.c
diff --git a/gas/config/tc-aarch64-ginsn.c b/gas/config/tc-aarch64-ginsn.c
new file mode 100644
index 00000000000..dbee8df88b1
--- /dev/null
+++ b/gas/config/tc-aarch64-ginsn.c
@@ -0,0 +1,797 @@
+/* tc-aarch64-ginsn.c -- Ginsn generation for the AArch64 ISA
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* This file contains the implementation of the ginsn creation for aarch64
+ instructions. Most functions will read the aarch64_instruction inst
+ object, but none should need to modify it. */
+
+#ifdef OBJ_ELF
+
+/* DWARF register number for R1. Used as dummy value when WZR. */
+#define GINSN_DW2_REGNUM_R1_DUMMY 1
+
+/* Return whether the given register number is a callee-saved register for
+ SCFI purposes.
+
+ Apart from the callee-saved GPRs, SCFI always tracks SP, FP and LR
+ additionally. As for the FP/Advanced SIMD registers, v8-v15 are
+ callee-saved. */
+
+bool
+aarch64_scfi_callee_saved_p (unsigned int dw2reg_num)
+{
+ /* PS: Ensure SCFI_MAX_REG_ID is the max DWARF register number to cover
+ all the registers here. */
+ if (dw2reg_num == REG_SP /* x31. */
+ || dw2reg_num == REG_FP /* x29. */
+ || dw2reg_num == REG_LR /* x30. */
+ || (dw2reg_num >= 19 && dw2reg_num <= 28) /* x19 - x28. */
+ || (dw2reg_num >= 72 && dw2reg_num <= 79) /* v8 - v15. */)
+ return true;
+
+ return false;
+}
+
+/* Get the DWARF register number for the given OPND.
+ Whether 31 is used to encode WZR or SP is specified via SP_ALLOWED_P.
+
+ The caller must decide the value of SP_ALLOWED_P based on the instruction
+ encoding. */
+
+static unsigned int
+ginsn_dw2_regnum (aarch64_opnd_info *opnd, bool sp_allowed_p)
+{
+ enum aarch64_operand_class opnd_class;
+ unsigned int dw2reg_num = 0;
+
+ opnd_class = aarch64_get_operand_class (opnd->type);
+
+ switch (opnd_class)
+ {
+ case AARCH64_OPND_CLASS_FP_REG:
+ dw2reg_num = opnd->reg.regno + 64;
+ break;
+ case AARCH64_OPND_CLASS_SVE_REGLIST:
+ dw2reg_num = opnd->reglist.first_regno + 64;
+ break;
+ case AARCH64_OPND_CLASS_MODIFIED_REG:
+ case AARCH64_OPND_CLASS_INT_REG:
+ case AARCH64_OPND_CLASS_ADDRESS:
+ /* Use a dummy register value in case of WZR, else this will be an
+ incorrect dependency on REG_SP. */
+ if (!sp_allowed_p && opnd->reg.regno == REG_SP)
+ dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
+ else
+ /* For GPRs of our interest (callee-saved regs, SP, FP, LR),
+ DWARF register number is the same as AArch64 register number. */
+ dw2reg_num = opnd->reg.regno;
+ break;
+ case AARCH64_OPND_CLASS_SYSTEM:
+ /* For prfm etc., where a opnd->type AARCH64_OPND_PRFOP is seen. */
+ dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
+ break;
+ default:
+ as_bad ("Unexpected value in ginsn_dw2_regnum");
+ break;
+ }
+
+ return dw2reg_num;
+}
+
+/* Generate ginsn for addsub instructions with immediate opnd. */
+
+static ginsnS *
+aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
+{
+ ginsnS *ginsn = NULL;
+ bool add_p, sub_p;
+ offsetT src_imm = 0;
+ unsigned int dst_reg, opnd_reg;
+ aarch64_opnd_info *dst, *opnd;
+ ginsnS *(*ginsn_func) (const symbolS *, bool,
+ enum ginsn_src_type, unsigned int, offsetT,
+ enum ginsn_src_type, unsigned int, offsetT,
+ enum ginsn_dst_type, unsigned int, offsetT);
+
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+
+ add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
+ sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
+ gas_assert (add_p || sub_p);
+ ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
+
+ gas_assert (aarch64_num_of_operands (opcode) == 3);
+ dst = &base->operands[0];
+ opnd = &base->operands[1];
+
+ dst_reg = ginsn_dw2_regnum (dst, true);
+
+ if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
+ src_imm = inst.reloc.exp.X_add_number;
+ /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
+ and handle via aarch64_ginsn_unhandled () code path. */
+ else if (inst.reloc.type != BFD_RELOC_UNUSED)
+ return ginsn;
+ /* FIXME - verify the understanding and remove assert. */
+ else
+ gas_assert (0);
+
+ opnd_reg = ginsn_dw2_regnum (opnd, true);
+
+ ginsn = ginsn_func (insn_end_sym, true,
+ GINSN_SRC_REG, opnd_reg, 0,
+ GINSN_SRC_IMM, 0, src_imm,
+ GINSN_DST_REG, dst_reg, 0);
+ ginsn_set_where (ginsn);
+
+ return ginsn;
+}
+
+/* Generate ginsn for addsub instructions with reg opnd. */
+
+static ginsnS *
+aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
+{
+ ginsnS *ginsn = NULL;
+ bool add_p, sub_p;
+ unsigned int dst_reg, src1_reg, src2_reg;
+ aarch64_opnd_info *dst, *src1, *src2;
+ ginsnS *(*ginsn_func) (const symbolS *, bool,
+ enum ginsn_src_type, unsigned int, offsetT,
+ enum ginsn_src_type, unsigned int, offsetT,
+ enum ginsn_dst_type, unsigned int, offsetT);
+
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+
+ add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
+ sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
+ gas_assert (add_p || sub_p);
+ ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
+
+ gas_assert (aarch64_num_of_operands (opcode) == 3);
+ dst = &base->operands[0];
+ src1 = &base->operands[1];
+ src2 = &base->operands[2];
+
+ dst_reg = ginsn_dw2_regnum (dst, true);
+ src1_reg = ginsn_dw2_regnum (src1, true);
+ src2_reg = ginsn_dw2_regnum (src2, false);
+
+ ginsn = ginsn_func (insn_end_sym, true,
+ GINSN_SRC_REG, src1_reg, 0,
+ GINSN_SRC_REG, src2_reg, 0,
+ GINSN_DST_REG, dst_reg, 0);
+ ginsn_set_where (ginsn);
+
+ return ginsn;
+}
+
+/* Generate ginsn for the load pair and store pair instructions. */
+
+static ginsnS *
+aarch64_ginsn_ldstp (const symbolS *insn_end_sym)
+{
+ ginsnS *ginsn = NULL;
+ ginsnS *ginsn_ind = NULL;
+ ginsnS *ginsn_mem1 = NULL;
+ ginsnS *ginsn_mem2 = NULL;
+ unsigned int opnd_reg, addr_reg;
+ offsetT offset, mem_offset;
+ unsigned int width = 8;
+ bool store_p = false;
+
+ aarch64_opnd_info *opnd1, *opnd2, *addr;
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+
+ /* This function is for handling ldp / stp ops only. */
+ gas_assert (opcode->iclass == ldstpair_indexed
+ || opcode->iclass == ldstpair_off);
+ gas_assert (aarch64_num_of_operands (opcode) == 3);
+
+ opnd1 = &base->operands[0];
+ opnd2 = &base->operands[1];
+ addr = &base->operands[2];
+ store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
+
+ addr_reg = ginsn_dw2_regnum (addr, true);
+ gas_assert (!addr->addr.offset.is_reg);
+ mem_offset = addr->addr.offset.imm;
+
+ /* ldstp may load or store two 32-bit words or two 64-bit doublewords. */
+ if (opnd1->qualifier == AARCH64_OPND_QLF_W
+ || opnd1->qualifier == AARCH64_OPND_QLF_S_S)
+ width = 4;
+
+ /* Handle address calculation. */
+ if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
+ {
+ /* Pre-indexed store, e.g., stp x29, x30, [sp, -128]!
+ Pre-indexed addressing is like offset addressing, except that
+ the base pointer is updated as a result of the instruction.
+
+ Post-indexed store, e.g., stp x29, x30, [sp],128
+ Post-index addressing is useful for popping off the stack. The
+ instruction loads the value from the location pointed at by the stack
+ pointer, and then moves the stack pointer on to the next full location
+ in the stack. */
+ ginsn_ind = ginsn_new_add (insn_end_sym, false,
+ GINSN_SRC_REG, addr_reg, 0,
+ GINSN_SRC_IMM, 0, mem_offset,
+ GINSN_DST_REG, addr_reg, 0);
+ ginsn_set_where (ginsn_ind);
+ }
+
+ /* Save / restore of WZR is not of interest for SCFI. However, the address
+ processing component may have updated the stack pointer. At least, emit
+ that ginsn and return. PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
+ now; Check explicitly the regno for WZR. Also note,
+ TBD_GINSN_GEN_NOT_SCFI. */
+ if (opnd1->reg.regno == REG_SP /* WZR. */)
+ return ginsn_ind;
+
+ /* With post-index addressing, the value is loaded from the
+ address in the base pointer, and then the pointer is updated.
+ With pre-index addressing, the addr computation has already
+ been explicitly done. */
+ offset = mem_offset;
+ if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
+ offset = 0;
+
+ if (opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
+ {
+ width = 16;
+ if (target_big_endian)
+ offset += 8;
+ }
+
+ opnd_reg = ginsn_dw2_regnum (opnd1, false);
+ if (store_p)
+ {
+ ginsn_mem1 = ginsn_new_store (insn_end_sym, false,
+ GINSN_SRC_REG, opnd_reg,
+ GINSN_DST_INDIRECT, addr_reg, offset);
+ ginsn_set_where (ginsn_mem1);
+
+ opnd_reg = ginsn_dw2_regnum (opnd2, false);
+ ginsn_mem2 = ginsn_new_store (insn_end_sym, false,
+ GINSN_SRC_REG, opnd_reg,
+ GINSN_DST_INDIRECT, addr_reg,
+ offset + width);
+ ginsn_set_where (ginsn_mem2);
+ }
+ else
+ {
+ opnd_reg = ginsn_dw2_regnum (opnd1, false);
+ ginsn_mem1 = ginsn_new_load (insn_end_sym, false,
+ GINSN_SRC_INDIRECT, addr_reg, offset,
+ GINSN_DST_REG, opnd_reg);
+ ginsn_set_where (ginsn_mem1);
+
+ opnd_reg = ginsn_dw2_regnum (opnd2, false);
+ ginsn_mem2 = ginsn_new_load (insn_end_sym, false,
+ GINSN_SRC_INDIRECT, addr_reg, offset + width,
+ GINSN_DST_REG, opnd_reg);
+ ginsn_set_where (ginsn_mem2);
+ }
+
+ /* Link the list of ginsns created. */
+ if (addr->addr.preind && addr->addr.writeback)
+ gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem1));
+
+ gas_assert (!ginsn_link_next (ginsn_mem1, ginsn_mem2));
+
+ if (addr->addr.postind && addr->addr.writeback)
+ gas_assert (!ginsn_link_next (ginsn_mem2, ginsn_ind));
+
+ /* Make note of the first instruction in the list. */
+ ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem1;
+ return ginsn;
+}
+
+/* Generate ginsn for load and store instructions. */
+
+static ginsnS *
+aarch64_ginsn_ldstr (const symbolS *insn_end_sym)
+{
+ ginsnS *ginsn = NULL;
+ ginsnS *ginsn_ind = NULL;
+ ginsnS *ginsn_mem = NULL;
+ unsigned int opnd_reg, addr_reg;
+ offsetT offset, mem_offset;
+ bool store_p = false;
+
+ aarch64_opnd_info *opnd1, *addr;
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+
+ /* This function is for handling ldr, str ops only. */
+ gas_assert (opcode->iclass == ldst_imm9 || opcode->iclass == ldst_pos);
+ gas_assert (aarch64_num_of_operands (opcode) == 2);
+
+ opnd1 = &base->operands[0];
+ addr = &base->operands[1];
+ store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
+
+ addr_reg = ginsn_dw2_regnum (addr, true);
+
+ /* STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}].
+ LDR <Xt>, [<Xn|SP>], #<simm>. */
+ opnd_reg = ginsn_dw2_regnum (opnd1, false);
+
+ if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
+ mem_offset = inst.reloc.exp.X_add_number;
+ else
+ {
+ gas_assert (!addr->addr.offset.is_reg);
+ mem_offset = addr->addr.offset.imm;
+ }
+
+ /* Handle address calculation. */
+ if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
+ {
+ ginsn_ind = ginsn_new_add (insn_end_sym, false,
+ GINSN_SRC_REG, addr_reg, 0,
+ GINSN_SRC_IMM, 0, mem_offset,
+ GINSN_DST_REG, addr_reg, 0);
+ ginsn_set_where (ginsn_ind);
+ }
+
+ /* Save / restore of WZR is not of interest for SCFI. However, the address
+ processing component may have updated the stack pointer. At least, emit
+ that ginsn and return. PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
+ now; Check explicitly the regno for WZR. Also note,
+ TBD_GINSN_GEN_NOT_SCFI. */
+ if (opnd1->reg.regno == REG_SP /* WZR. */)
+ return ginsn_ind;
+
+ /* With post-index addressing, the value is loaded from the
+ address in the base pointer, and then the pointer is updated.
+ With pre-index addressing, the addr computation has already
+ been explicitly done. */
+ offset = mem_offset;
+ if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
+ offset = 0;
+ if (target_big_endian && opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
+ offset += 8;
+
+ if (store_p)
+ ginsn_mem = ginsn_new_store (insn_end_sym, false,
+ GINSN_SRC_REG, opnd_reg,
+ GINSN_DST_INDIRECT, addr_reg, offset);
+ else
+ ginsn_mem = ginsn_new_load (insn_end_sym, false,
+ GINSN_SRC_INDIRECT, addr_reg, offset,
+ GINSN_DST_REG, opnd_reg);
+ ginsn_set_where (ginsn_mem);
+
+ if (addr->addr.preind && addr->addr.writeback)
+ gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem));
+ else if (addr->addr.postind && addr->addr.writeback)
+ gas_assert (!ginsn_link_next (ginsn_mem, ginsn_ind));
+
+ /* Make note of the first instruction in the list. */
+ ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem;
+
+ return ginsn;
+}
+
+/* Generate ginsn for unconditional branch instructions. */
+
+static ginsnS *
+aarch64_ginsn_branch_uncond (const symbolS *insn_end_sym)
+{
+ ginsnS *ginsn = NULL;
+ const symbolS *src_symbol = NULL;
+ enum ginsn_src_type src_type = GINSN_SRC_UNKNOWN;
+ unsigned int src_reg = 0;
+
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+
+ if (opcode->iclass == branch_imm)
+ {
+ /* b or bl. opcode 0x14000000 or 0x94000000. */
+ gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_CALL26
+ || inst.reloc.type == BFD_RELOC_AARCH64_JUMP26);
+ src_symbol = inst.reloc.exp.X_add_symbol;
+ src_type = GINSN_SRC_SYMBOL;
+ }
+ else if (aarch64_num_of_operands (opcode) >= 1)
+ {
+ gas_assert (opcode->iclass == branch_reg);
+ /* Some insns (e.g., braa, blraa etc.) may have > 1 operands. For
+ current SCFI implementation, it suffices however to simply pass
+ the information about the first source. Although, strictly speaking,
+ (if reg) the source info is currently of no material use either. */
+ src_type = GINSN_SRC_REG;
+ src_reg = ginsn_dw2_regnum (&base->operands[0], false);
+ }
+
+ if (aarch64_opcode_subclass_p (opcode, F_BRANCH_CALL))
+ {
+ gas_assert (src_type != GINSN_SRC_UNKNOWN);
+ ginsn = ginsn_new_call (insn_end_sym, true,
+ src_type, src_reg, src_symbol);
+ }
+ else if (aarch64_opcode_subclass_p (opcode, F_BRANCH_RET))
+ /* TBD_GINSN_REPRESENTATION_LIMIT. The following function to create a
+ GINSN_TYPE_RETURN does not allow src info ATM. */
+ ginsn = ginsn_new_return (insn_end_sym, true);
+ else
+ ginsn = ginsn_new_jump (insn_end_sym, true,
+ src_type, src_reg, src_symbol);
+
+ ginsn_set_where (ginsn);
+
+ return ginsn;
+}
+
+/* Generate ginsn for conditional branch instructions. */
+
+static ginsnS *
+aarch64_ginsn_branch_cond (const symbolS *insn_end_sym)
+{
+ ginsnS *ginsn;
+ const symbolS *src_symbol;
+ enum ginsn_src_type src_type;
+
+ gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_BRANCH19
+ || inst.reloc.type == BFD_RELOC_AARCH64_TSTBR14);
+
+ src_symbol = inst.reloc.exp.X_add_symbol;
+ src_type = GINSN_SRC_SYMBOL;
+ ginsn = ginsn_new_jump_cond (insn_end_sym, true, src_type, 0, src_symbol);
+ ginsn_set_where (ginsn);
+
+ return ginsn;
+}
+
+/* Generate ginsn for mov instructions. */
+
+static ginsnS *
+aarch64_ginsn_mov (const symbolS *insn_end_sym)
+{
+ ginsnS *ginsn = NULL;
+ unsigned int src_reg = 0, dst_reg;
+ aarch64_opnd_info *src, *dst;
+ offsetT src_imm = 0;
+ enum ginsn_src_type src_type;
+
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+
+ gas_assert (aarch64_num_of_operands (opcode) == 2);
+
+ dst = &base->operands[0];
+ src = &base->operands[1];
+
+ dst_reg = ginsn_dw2_regnum (dst, true);
+
+ /* For some mov ops, e.g., movn, movk, or movz, there may optionally be more
+ work than just a simple mov. Skip handling these mov altogether and let
+ the aarch64_ginsn_unhandled () alert if these insns affect SCFI
+ correctness. TBD_GINSN_GEN_NOT_SCFI. */
+ if (src->type == AARCH64_OPND_HALF)
+ return ginsn;
+
+ if (src->type == AARCH64_OPND_IMM_MOV
+ && aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
+ {
+ src_imm = inst.reloc.exp.X_add_number;
+ src_type = GINSN_SRC_IMM;
+ }
+ else
+ {
+ /* mov x27, sp. */
+ src_reg = ginsn_dw2_regnum (src, true);
+ src_type = GINSN_SRC_REG;
+ }
+
+ ginsn = ginsn_new_mov (insn_end_sym, false,
+ src_type, src_reg, src_imm,
+ GINSN_DST_REG, dst_reg, 0);
+ ginsn_set_where (ginsn);
+
+ return ginsn;
+}
+
+/* Check if an instruction is whitelisted.
+
+ An instruction is a candidate for whitelisting if not generating ginsn for
+ it, does not affect SCFI correctness.
+
+ TBD_GINSN_GEN_NOT_SCFI. This function assumes GINSN_GEN_SCFI is in effect.
+ When other ginsn_gen_mode are added, this will need fixing. */
+
+static bool
+aarch64_ginsn_safe_to_skip_p (void)
+{
+ bool skip_p = false;
+ aarch64_opnd_info *opnd = NULL;
+ unsigned int dw2_regnum;
+ unsigned int opnd_reg;
+ int num_opnds = 0;
+
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+
+ /* ATM, whitelisting operations with no operands does not seem to be
+ necessary. */
+ num_opnds = aarch64_num_of_operands (opcode);
+ if (!num_opnds)
+ return skip_p;
+
+ opnd = &base->operands[0];
+
+ switch (opcode->iclass)
+ {
+ case ldst_regoff:
+ /* It is not expected to have reg offset based ld/st ops to be used
+ for reg save and restore operations. Warn the user though. */
+ opnd_reg = ginsn_dw2_regnum (opnd, false);
+ if (aarch64_scfi_callee_saved_p (opnd_reg))
+ {
+ skip_p = true;
+ as_warn ("SCFI: ignored probable save/restore op with reg offset");
+ }
+ break;
+
+ case dp_2src:
+ /* irg insn needs to be explicitly whitelisted. This is because the
+ dest is Rd_SP, but irg insn affects the tag only. To detect irg
+ insn, avoid an opcode-based check, however. */
+ if (opnd->type == AARCH64_OPND_Rd_SP)
+ {
+ dw2_regnum = ginsn_dw2_regnum (opnd, true);
+ if (dw2_regnum == REG_SP)
+ skip_p = true;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return skip_p;
+}
+
+#define AARCH64_GINSN_UNHANDLED_NONE 0
+#define AARCH64_GINSN_UNHANDLED_DEST_REG 1
+#define AARCH64_GINSN_UNHANDLED_CFG 2
+#define AARCH64_GINSN_UNHANDLED_STACKOP 3
+#define AARCH64_GINSN_UNHANDLED_UNEXPECTED 4
+
+/* Check the input insn for its impact on the correctness of the synthesized
+ CFI. Returns an error code to the caller. */
+
+static int
+aarch64_ginsn_unhandled (void)
+{
+ int err = AARCH64_GINSN_UNHANDLED_NONE;
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+ aarch64_opnd_info *dest = &base->operands[0];
+ int num_opnds = aarch64_num_of_operands (opcode);
+ aarch64_opnd_info *addr;
+ unsigned int dw2_regnum;
+ unsigned int addr_reg;
+ aarch64_opnd_info *opnd = NULL;
+ unsigned int opnd_reg;
+ bool sp_allowed_p = false;
+
+ /* All change of flow instructions are important for SCFI. */
+ if (opcode->iclass == condbranch
+ || opcode->iclass == compbranch
+ || opcode->iclass == testbranch
+ || opcode->iclass == branch_imm
+ || opcode->iclass == branch_reg)
+ err = AARCH64_GINSN_UNHANDLED_CFG;
+ /* Also, any memory instructions that may involve an update to the stack
+ pointer or save/restore of callee-saved registers must not be skipped.
+ Note that, some iclasses cannot be used to push or pop stack because of
+ disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
+ loadlit, ldstnapair_offs. FIXME double-check.
+ Also, these iclasses do not seem to be amenable to being used for
+ save/restore ops either. FIXME double-check. */
+ else if (opcode->iclass == ldstpair_off
+ || opcode->iclass == ldstpair_indexed
+ || opcode->iclass == ldst_imm9
+ || opcode->iclass == ldst_imm10
+ || opcode->iclass == ldst_pos
+ /* STR Zn are especially complicated as they do not store in the same byte
+ order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
+ whereas STR Zn stores as a stream of bytes (LSB first). FIXME Simply punt
+ on the big-endian and little-endian SVE PCS case for now. */
+ || opcode->iclass == sve_misc)
+ {
+ opnd = &base->operands[0];
+ addr = &base->operands[num_opnds - 1];
+ addr_reg = ginsn_dw2_regnum (addr, true);
+ opnd_reg = ginsn_dw2_regnum (opnd, false);
+ /* For all skipped memory operations, check if an update to REG_SP or
+ REG_FP is involved. */
+ if ((addr_reg == REG_SP || addr_reg == REG_FP)
+ && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
+ || aarch64_scfi_callee_saved_p (opnd_reg)))
+
+ err = AARCH64_GINSN_UNHANDLED_STACKOP;
+ }
+ /* Finally, irrespective of the iclass, check if the missed instructions are
+ affecting REG_SP or REG_FP. */
+ else if (dest && (dest->type == AARCH64_OPND_Rd
+ || dest->type == AARCH64_OPND_Rd_SP))
+ {
+ sp_allowed_p = (dest->type == AARCH64_OPND_Rd_SP) ? true : false;
+ dw2_regnum = ginsn_dw2_regnum (dest, sp_allowed_p);
+
+ if (dw2_regnum == REG_SP || dw2_regnum == REG_FP)
+ err = AARCH64_GINSN_UNHANDLED_DEST_REG;
+ }
+
+ return err;
+}
+
+/* Generate one or more generic GAS instructions, a.k.a, ginsns for the
+ current machine instruction.
+
+ Returns the head of linked list of ginsn(s) added, if success; Returns NULL
+ if failure.
+
+ The input ginsn_gen_mode GMODE determines the set of minimal necessary
+ ginsns necessary for correctness of any passes applicable for that mode.
+ For supporting the GINSN_GEN_SCFI generation mode, following is the list of
+ machine instructions that must be translated into the corresponding ginsns
+ to ensure correctness of SCFI:
+ - All instructions affecting the two registers that could potentially
+ be used as the base register for CFA tracking. For SCFI, the base
+ register for CFA tracking is limited to REG_SP and REG_FP only.
+ - All change of flow instructions: conditional and unconditional
+ branches, call and return from functions.
+ - All instructions that can potentially be a register save / restore
+ operations.
+ - All instructions that may update the stack pointer: pre-indexed and
+ post-indexed stack operations with writeback.
+
+ The function currently supports GINSN_GEN_SCFI ginsn generation mode only.
+ To support other generation modes will require work on this target-specific
+ process of creation of ginsns:
+ - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
+ possible starting points.
+ - Also note that ginsn representation may need enhancements. Specifically,
+ note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers.
+ */
+
+static ginsnS *
+aarch64_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode)
+{
+ int err = 0;
+ ginsnS *ginsn = NULL;
+ unsigned int dw2_regnum;
+ aarch64_opnd_info *dest = NULL;
+ bool sp_allowed_p = false;
+ aarch64_inst *base = &inst.base;
+ const aarch64_opcode *opcode = base->opcode;
+
+ /* Currently supports generation of selected ginsns, sufficient for
+ the use-case of SCFI only. To remove this condition will require
+ work on this target-specific process of creation of ginsns. Some
+ of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
+ examples. */
+ if (gmode != GINSN_GEN_SCFI)
+ return ginsn;
+
+ switch (opcode->iclass)
+ {
+ case addsub_ext:
+ /* TBD_GINSN_GEN_NOT_SCFI: other insns are not of interest for SCFI. */
+ if (aarch64_opcode_subclass_p (opcode, F_ARITH_ADD)
+ || aarch64_opcode_subclass_p (opcode, F_ARITH_SUB))
+ ginsn = aarch64_ginsn_addsub_reg (insn_end_sym);
+ break;
+
+ case addsub_imm:
+ if (aarch64_opcode_subclass_p (opcode, F_ARITH_MOV))
+ ginsn = aarch64_ginsn_mov (insn_end_sym);
+ else if (aarch64_opcode_subclass_p (opcode, F_ARITH_ADD)
+ || aarch64_opcode_subclass_p (opcode, F_ARITH_SUB))
+ ginsn = aarch64_ginsn_addsub_imm (insn_end_sym);
+ break;
+
+ case movewide:
+ ginsn = aarch64_ginsn_mov (insn_end_sym);
+ break;
+
+ case ldst_imm9:
+ case ldst_pos:
+ ginsn = aarch64_ginsn_ldstr (insn_end_sym);
+ break;
+
+ case ldstpair_indexed:
+ case ldstpair_off:
+ ginsn = aarch64_ginsn_ldstp (insn_end_sym);
+ break;
+
+ case branch_imm:
+ case branch_reg:
+ ginsn = aarch64_ginsn_branch_uncond (insn_end_sym);
+ break;
+
+ case compbranch:
+ /* Although cbz/cbnz has an additional operand and are functionally
+ distinct from conditional branches, it is fine to use the same ginsn
+ type for both from the perspective of SCFI. */
+ case testbranch:
+ case condbranch:
+ ginsn = aarch64_ginsn_branch_cond (insn_end_sym);
+ break;
+
+ default:
+ /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for
+ GINSN_GEN_SCFI mode. */
+ break;
+ }
+
+ if (!ginsn && !aarch64_ginsn_safe_to_skip_p ())
+ {
+ /* For all unhandled insns, check that they no not impact SCFI
+ correctness. */
+ err = aarch64_ginsn_unhandled ();
+ switch (err)
+ {
+ case AARCH64_GINSN_UNHANDLED_NONE:
+ break;
+ case AARCH64_GINSN_UNHANDLED_DEST_REG:
+ /* Not all writes to REG_FP are harmful in context of SCFI. Simply
+ generate a GINSN_TYPE_OTHER with destination set to the
+ appropriate register. The SCFI machinery will bail out if this
+ ginsn affects SCFI correctness. */
+ dest = &base->operands[0];
+ sp_allowed_p = (dest->type == AARCH64_OPND_Rd_SP) ? true : false;
+ dw2_regnum = ginsn_dw2_regnum (dest, sp_allowed_p);
+ ginsn = ginsn_new_other (insn_end_sym, true,
+ GINSN_SRC_IMM, 0,
+ GINSN_SRC_IMM, 0,
+ GINSN_DST_REG, dw2_regnum);
+ ginsn_set_where (ginsn);
+ break;
+ case AARCH64_GINSN_UNHANDLED_CFG:
+ case AARCH64_GINSN_UNHANDLED_STACKOP:
+ as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"),
+ opcode->opcode);
+ break;
+ case AARCH64_GINSN_UNHANDLED_UNEXPECTED:
+ as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"),
+ opcode->opcode);
+ break;
+ default:
+ abort ();
+ break;
+ }
+ }
+
+ return ginsn;
+}
+
+#endif /* OBJ_ELF. */
+
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5d15ee9fc02..4f4dd404551 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -33,6 +33,7 @@
#include "dw2gencfi.h"
#include "sframe.h"
#include "gen-sframe.h"
+#include "scfi.h"
#endif
#include "dw2gencfi.h"
@@ -8591,6 +8592,10 @@ dump_opcode_operands (const aarch64_opcode *opcode)
}
#endif /* DEBUG_AARCH64 */
+#ifdef OBJ_ELF
+# include "tc-aarch64-ginsn.c"
+#endif
+
/* This is the guts of the machine-dependent assembler. STR points to a
machine dependent instruction. This function is supposed to emit
the frags/bytes it assembles to. */
@@ -8728,6 +8733,16 @@ md_assemble (char *str)
output_inst (copy);
}
+#ifdef OBJ_ELF
+ if (flag_synth_cfi)
+ {
+ ginsnS *ginsn;
+ ginsn = aarch64_ginsn_new (symbol_temp_new_now (),
+ frch_ginsn_gen_mode ());
+ frch_ginsn_data_append (ginsn);
+ }
+#endif
+
/* Issue non-fatal messages if any. */
output_operand_error_report (str, true);
return;
diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
index 1b8badad9fd..4906a6e7000 100644
--- a/gas/config/tc-aarch64.h
+++ b/gas/config/tc-aarch64.h
@@ -263,6 +263,27 @@ extern void aarch64_after_parse_args (void);
#ifdef OBJ_ELF
+#define TARGET_USE_GINSN 1
+/* Allow GAS to synthesize DWARF CFI for hand-written asm.
+ PS: TARGET_USE_CFIPOP is a pre-condition. */
+#define TARGET_USE_SCFI 1
+/* Identify the maximum DWARF register number of all the registers being
+ tracked for SCFI. This is the last DWARF register number of the set
+ of SP, FP, and all callee-saved registers. For Aarch64, this means 79
+ because FP/Advanced SIMD v8-v15 are also callee-saved registers. */
+# define SCFI_MAX_REG_ID 79
+/* Identify the DWARF register number of the frame-pointer register. */
+# define REG_FP 29
+/* Identify the DWARF register number of the link register. */
+# define REG_LR 30
+/* Identify the DWARF register number of the stack-pointer register. */
+# define REG_SP 31
+
+#define SCFI_INIT_CFA_OFFSET 0
+
+#define SCFI_CALLEE_SAVED_REG_P(dw2reg) aarch64_scfi_callee_saved_p (dw2reg)
+extern bool aarch64_scfi_callee_saved_p (uint32_t dw2reg_num);
+
/* Whether SFrame stack trace info is supported. */
extern bool aarch64_support_sframe_p (void);
#define support_sframe_p aarch64_support_sframe_p
--
2.43.0
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI
2024-07-01 2:54 ` [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI Indu Bhagat
@ 2024-07-01 19:49 ` Richard Sandiford
2024-07-11 6:30 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Richard Sandiford @ 2024-07-01 19:49 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> [Changes in V4]
> - Use data types uniformly. Use 'unsigned int' instead of 'uint32_t'
> for DWARF register numbers. Use offsetT where applicable.
> - Minor code restructuring in aarch64_ginsn_safe_to_skip_p (). Move
> common code out of switch case.
> - Add FP/Advanced SIMD registers to callee-saved registers too.
> Updated commit log to include some of the details.
> - Check for opnd type AARCH64_OPND_QLF_W or AARCH64_OPND_QLF_S_S in
> aarch64_ginsn_ldstp () to detect 32-bit word operations.
> - Skip generating ginsns for movk, movz, movn. These do more work than
> just simple mov; Skip generating ginsn altogether for these.
> - ginsn_dw2_regnum () is now switch case on opnd_class. Each case
> exposed by the current set of ginsn creation logic is handled.
> - Skip Z register usage altogether for now. Skip sve_misc iclass but
> error out if callee-saved FP/Advanced SIMD registers or stack
> management are involved.
> [End of changes in V4]
>
> [No changes in V3]
>
> [Changes in V2]
> - Factored out the ginsn creation functionality from tc-aarch64.c into
> tc-aarch64-ginsn.c.
> - The switch case in aarch64_ginsn_new now is based on iclass rather
> than (earlier) opcode.
> - Rename aarch64_ginsn_jump / aarch64_ginsn_jump_cond to
> aarch64_ginsn_branch_uncond / aarch64_ginsn_branch_cond respectively.
> - Explicitly whitelist irg insn.
> - Other minor code comment and readability fixes.
> [End of changes in V2]
>
> For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in
> GAS works on the generic GAS insns (ginsns). This patch adds support in
> the aarch64 backend to create ginsns for a subset of the supported
> machine instructions. The subset includes the minimal necessary
> instructions to ensure SCFI correctness:
>
> - Any potential register saves and unsaves. Hence, process instructions
> belonging to a variety of iclasses involving str, ldr, stp, ldp.
> - Any change of flow instructions. This includes all conditional and
> unconditional branches, call (bl, blr, etc.) and return.
> - Most importantly, any instruction that could affect the two registers
> of interest: REG_SP, REG_FP. This set includes all pre-indexed and
> post-indexed memory operations, with writeback, on the stack. This
> set must also include other instructions (e.g., arithmetic insns)
> where the destination register is one of the afore-mentioned registers.
>
> With respect to callee-saved registers in Aarch64, FP/Advanced SIMD
> registers D8-D15 are included along with the relevant GPRs. Calculating
> offsets for loads and stores especially for Q registers needs special
> attention here.
>
> As an example,
> str q8, [sp, #16]
> On big-endian:
> STR Qn stores as a 128-bit integer (MSB first), hence, should record
> D8 as being saved at sp+24 rather than sp+16.
> On little-endian:
> should record D8 as being saved at sp+16
>
> D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used;
> hence, they remain "interesting" for SCFI purposes in such cases. A CFI
> save slot always represents the low 64 bits, regardless of whether a
> save occurs on D, Q or Z registers. Currently, the ginsn creation
> machinery can handle D and Q registers on little-endian and big-endian.
>
> Apart from creating ginsn, another key responsibility of the backend is
> to make sure there are safeguards in place to detect and alert if an
> instruction of interest may have been skipped. This is done via
> aarch64_ginsn_unhandled () (similar to the x86 backend). This function
> , hence, is also intended to alert when future ISA changes may otherwise
> render SCFI results incorrect, because of missing ginsns for the newly
> added machine instructions.
>
> At this time, becuase of the complexities wrt endianness in handling Z
> register usage, skip sve_misc opclass altogether for now. The SCFI
> machinery will error out (using the aarch64_ginsn_unhandled () code
> path) though if Z register usage affects correctness.
>
> The current SCFI machinery does not currently synthesize the
> PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame. The
> support for this is planned for near future.
>
> SCFI is enabled for ELF targets only.
>
> gas/
> * config/tc-aarch64-ginsn.c: New file.
> * config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c
> file. Invoke aarch64_ginsn_new.
> * config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI
> enablement.
> (TARGET_USE_SCFI): Likewise.
> (SCFI_MAX_REG_ID): New definition.
> (REG_FP): Likewise.
> (REG_LR): Likewise.
> (REG_SP): Likewise.
> (SCFI_INIT_CFA_OFFSET): Likewise.
> (SCFI_CALLEE_SAVED_REG_P): Likewise.
> (aarch64_scfi_callee_saved_p): New declaration.
> ---
> gas/config/tc-aarch64-ginsn.c | 797 ++++++++++++++++++++++++++++++++++
> gas/config/tc-aarch64.c | 15 +
> gas/config/tc-aarch64.h | 21 +
> 3 files changed, 833 insertions(+)
> create mode 100644 gas/config/tc-aarch64-ginsn.c
>
> diff --git a/gas/config/tc-aarch64-ginsn.c b/gas/config/tc-aarch64-ginsn.c
> new file mode 100644
> index 00000000000..dbee8df88b1
> --- /dev/null
> +++ b/gas/config/tc-aarch64-ginsn.c
> @@ -0,0 +1,797 @@
> +/* tc-aarch64-ginsn.c -- Ginsn generation for the AArch64 ISA
> +
> + Copyright (C) 2024 Free Software Foundation, Inc.
> + Contributed by ARM Ltd.
Not so :)
> +
> + This file is part of GAS.
> +
> + GAS is free software; you can redistribute it and/or modify
> + it under the terms of the GNU General Public License as published by
> + the Free Software Foundation; either version 3 of the license, or
> + (at your option) any later version.
> +
> + GAS is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + GNU General Public License for more details.
> +
> + You should have received a copy of the GNU General Public License
> + along with this program; see the file COPYING3. If not,
> + see <http://www.gnu.org/licenses/>. */
> +
> +/* This file contains the implementation of the ginsn creation for aarch64
> + instructions. Most functions will read the aarch64_instruction inst
> + object, but none should need to modify it. */
> +
> +#ifdef OBJ_ELF
> +
> +/* DWARF register number for R1. Used as dummy value when WZR. */
> +#define GINSN_DW2_REGNUM_R1_DUMMY 1
> +
> +/* Return whether the given register number is a callee-saved register for
> + SCFI purposes.
> +
> + Apart from the callee-saved GPRs, SCFI always tracks SP, FP and LR
> + additionally. As for the FP/Advanced SIMD registers, v8-v15 are
> + callee-saved. */
> +
> +bool
> +aarch64_scfi_callee_saved_p (unsigned int dw2reg_num)
> +{
> + /* PS: Ensure SCFI_MAX_REG_ID is the max DWARF register number to cover
> + all the registers here. */
> + if (dw2reg_num == REG_SP /* x31. */
> + || dw2reg_num == REG_FP /* x29. */
> + || dw2reg_num == REG_LR /* x30. */
> + || (dw2reg_num >= 19 && dw2reg_num <= 28) /* x19 - x28. */
> + || (dw2reg_num >= 72 && dw2reg_num <= 79) /* v8 - v15. */)
> + return true;
> +
> + return false;
> +}
> +
> +/* Get the DWARF register number for the given OPND.
> + Whether 31 is used to encode WZR or SP is specified via SP_ALLOWED_P.
> +
> + The caller must decide the value of SP_ALLOWED_P based on the instruction
> + encoding. */
> +
> +static unsigned int
> +ginsn_dw2_regnum (aarch64_opnd_info *opnd, bool sp_allowed_p)
Couldn't this use operand_maybe_stack_pointer instead of taking
an sp_allowed_p parameter?
> +{
> + enum aarch64_operand_class opnd_class;
> + unsigned int dw2reg_num = 0;
> +
> + opnd_class = aarch64_get_operand_class (opnd->type);
> +
> + switch (opnd_class)
> + {
> + case AARCH64_OPND_CLASS_FP_REG:
> + dw2reg_num = opnd->reg.regno + 64;
> + break;
> + case AARCH64_OPND_CLASS_SVE_REGLIST:
> + dw2reg_num = opnd->reglist.first_regno + 64;
> + break;
> + case AARCH64_OPND_CLASS_MODIFIED_REG:
> + case AARCH64_OPND_CLASS_INT_REG:
> + case AARCH64_OPND_CLASS_ADDRESS:
> + /* Use a dummy register value in case of WZR, else this will be an
> + incorrect dependency on REG_SP. */
> + if (!sp_allowed_p && opnd->reg.regno == REG_SP)
> + dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
> + else
> + /* For GPRs of our interest (callee-saved regs, SP, FP, LR),
> + DWARF register number is the same as AArch64 register number. */
> + dw2reg_num = opnd->reg.regno;
> + break;
I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
instead. AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
> + case AARCH64_OPND_CLASS_SYSTEM:
> + /* For prfm etc., where a opnd->type AARCH64_OPND_PRFOP is seen. */
> + dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
> + break;
Hopefully this goes away if we treat PRFM as "other".
> + default:
> + as_bad ("Unexpected value in ginsn_dw2_regnum");
> + break;
> + }
> +
> + return dw2reg_num;
> +}
> +
> +/* Generate ginsn for addsub instructions with immediate opnd. */
> +
> +static ginsnS *
> +aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
> +{
> + ginsnS *ginsn = NULL;
> + bool add_p, sub_p;
> + offsetT src_imm = 0;
> + unsigned int dst_reg, opnd_reg;
> + aarch64_opnd_info *dst, *opnd;
> + ginsnS *(*ginsn_func) (const symbolS *, bool,
> + enum ginsn_src_type, unsigned int, offsetT,
> + enum ginsn_src_type, unsigned int, offsetT,
> + enum ginsn_dst_type, unsigned int, offsetT);
> +
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> +
> + add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
> + sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
> + gas_assert (add_p || sub_p);
> + ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
> +
> + gas_assert (aarch64_num_of_operands (opcode) == 3);
> + dst = &base->operands[0];
> + opnd = &base->operands[1];
> +
> + dst_reg = ginsn_dw2_regnum (dst, true);
> +
> + if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
> + src_imm = inst.reloc.exp.X_add_number;
> + /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
> + and handle via aarch64_ginsn_unhandled () code path. */
> + else if (inst.reloc.type != BFD_RELOC_UNUSED)
> + return ginsn;
> + /* FIXME - verify the understanding and remove assert. */
> + else
> + gas_assert (0);
> +
> + opnd_reg = ginsn_dw2_regnum (opnd, true);
> +
> + ginsn = ginsn_func (insn_end_sym, true,
> + GINSN_SRC_REG, opnd_reg, 0,
> + GINSN_SRC_IMM, 0, src_imm,
> + GINSN_DST_REG, dst_reg, 0);
> + ginsn_set_where (ginsn);
> +
> + return ginsn;
> +}
> +
> +/* Generate ginsn for addsub instructions with reg opnd. */
> +
> +static ginsnS *
> +aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
> +{
> + ginsnS *ginsn = NULL;
> + bool add_p, sub_p;
> + unsigned int dst_reg, src1_reg, src2_reg;
> + aarch64_opnd_info *dst, *src1, *src2;
> + ginsnS *(*ginsn_func) (const symbolS *, bool,
> + enum ginsn_src_type, unsigned int, offsetT,
> + enum ginsn_src_type, unsigned int, offsetT,
> + enum ginsn_dst_type, unsigned int, offsetT);
> +
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> +
> + add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
> + sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
> + gas_assert (add_p || sub_p);
> + ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
> +
> + gas_assert (aarch64_num_of_operands (opcode) == 3);
> + dst = &base->operands[0];
> + src1 = &base->operands[1];
> + src2 = &base->operands[2];
> +
> + dst_reg = ginsn_dw2_regnum (dst, true);
> + src1_reg = ginsn_dw2_regnum (src1, true);
> + src2_reg = ginsn_dw2_regnum (src2, false);
> +
> + ginsn = ginsn_func (insn_end_sym, true,
> + GINSN_SRC_REG, src1_reg, 0,
> + GINSN_SRC_REG, src2_reg, 0,
> + GINSN_DST_REG, dst_reg, 0);
> + ginsn_set_where (ginsn);
It looks like this ignores any shift that is applied to src2_reg.
> +
> + return ginsn;
> +}
> +
> +/* Generate ginsn for the load pair and store pair instructions. */
> +
> +static ginsnS *
> +aarch64_ginsn_ldstp (const symbolS *insn_end_sym)
> +{
> + ginsnS *ginsn = NULL;
> + ginsnS *ginsn_ind = NULL;
> + ginsnS *ginsn_mem1 = NULL;
> + ginsnS *ginsn_mem2 = NULL;
> + unsigned int opnd_reg, addr_reg;
> + offsetT offset, mem_offset;
> + unsigned int width = 8;
> + bool store_p = false;
> +
> + aarch64_opnd_info *opnd1, *opnd2, *addr;
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> +
> + /* This function is for handling ldp / stp ops only. */
> + gas_assert (opcode->iclass == ldstpair_indexed
> + || opcode->iclass == ldstpair_off);
> + gas_assert (aarch64_num_of_operands (opcode) == 3);
> +
> + opnd1 = &base->operands[0];
> + opnd2 = &base->operands[1];
> + addr = &base->operands[2];
> + store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
> +
> + addr_reg = ginsn_dw2_regnum (addr, true);
> + gas_assert (!addr->addr.offset.is_reg);
> + mem_offset = addr->addr.offset.imm;
> +
> + /* ldstp may load or store two 32-bit words or two 64-bit doublewords. */
> + if (opnd1->qualifier == AARCH64_OPND_QLF_W
> + || opnd1->qualifier == AARCH64_OPND_QLF_S_S)
> + width = 4;
> +
> + /* Handle address calculation. */
> + if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
> + {
> + /* Pre-indexed store, e.g., stp x29, x30, [sp, -128]!
> + Pre-indexed addressing is like offset addressing, except that
> + the base pointer is updated as a result of the instruction.
> +
> + Post-indexed store, e.g., stp x29, x30, [sp],128
> + Post-index addressing is useful for popping off the stack. The
> + instruction loads the value from the location pointed at by the stack
> + pointer, and then moves the stack pointer on to the next full location
> + in the stack. */
> + ginsn_ind = ginsn_new_add (insn_end_sym, false,
> + GINSN_SRC_REG, addr_reg, 0,
> + GINSN_SRC_IMM, 0, mem_offset,
> + GINSN_DST_REG, addr_reg, 0);
> + ginsn_set_where (ginsn_ind);
> + }
> +
> + /* Save / restore of WZR is not of interest for SCFI. However, the address
> + processing component may have updated the stack pointer. At least, emit
> + that ginsn and return. PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
> + now; Check explicitly the regno for WZR. Also note,
> + TBD_GINSN_GEN_NOT_SCFI. */
> + if (opnd1->reg.regno == REG_SP /* WZR. */)
> + return ginsn_ind;
> +
> + /* With post-index addressing, the value is loaded from the
> + address in the base pointer, and then the pointer is updated.
> + With pre-index addressing, the addr computation has already
> + been explicitly done. */
> + offset = mem_offset;
> + if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
> + offset = 0;
I guess this is personal taste, but IMO it would be easier to follow if
this were combined with the "if" above, so that the compensating action
of ginsn_ind is next to the creation of ginsn_ind itself.
> +
> + if (opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
> + {
> + width = 16;
> + if (target_big_endian)
> + offset += 8;
> + }
> +
> + opnd_reg = ginsn_dw2_regnum (opnd1, false);
> + if (store_p)
> + {
> + ginsn_mem1 = ginsn_new_store (insn_end_sym, false,
> + GINSN_SRC_REG, opnd_reg,
> + GINSN_DST_INDIRECT, addr_reg, offset);
> + ginsn_set_where (ginsn_mem1);
> +
> + opnd_reg = ginsn_dw2_regnum (opnd2, false);
> + ginsn_mem2 = ginsn_new_store (insn_end_sym, false,
> + GINSN_SRC_REG, opnd_reg,
> + GINSN_DST_INDIRECT, addr_reg,
> + offset + width);
> + ginsn_set_where (ginsn_mem2);
> + }
> + else
> + {
> + opnd_reg = ginsn_dw2_regnum (opnd1, false);
> + ginsn_mem1 = ginsn_new_load (insn_end_sym, false,
> + GINSN_SRC_INDIRECT, addr_reg, offset,
> + GINSN_DST_REG, opnd_reg);
> + ginsn_set_where (ginsn_mem1);
> +
> + opnd_reg = ginsn_dw2_regnum (opnd2, false);
> + ginsn_mem2 = ginsn_new_load (insn_end_sym, false,
> + GINSN_SRC_INDIRECT, addr_reg, offset + width,
> + GINSN_DST_REG, opnd_reg);
> + ginsn_set_where (ginsn_mem2);
> + }
> +
> + /* Link the list of ginsns created. */
> + if (addr->addr.preind && addr->addr.writeback)
> + gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem1));
> +
> + gas_assert (!ginsn_link_next (ginsn_mem1, ginsn_mem2));
> +
> + if (addr->addr.postind && addr->addr.writeback)
> + gas_assert (!ginsn_link_next (ginsn_mem2, ginsn_ind));
> +
> + /* Make note of the first instruction in the list. */
> + ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem1;
> + return ginsn;
> +}
> +
> +/* Generate ginsn for load and store instructions. */
> +
> +static ginsnS *
> +aarch64_ginsn_ldstr (const symbolS *insn_end_sym)
> +{
> + ginsnS *ginsn = NULL;
> + ginsnS *ginsn_ind = NULL;
> + ginsnS *ginsn_mem = NULL;
> + unsigned int opnd_reg, addr_reg;
> + offsetT offset, mem_offset;
> + bool store_p = false;
> +
> + aarch64_opnd_info *opnd1, *addr;
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> +
> + /* This function is for handling ldr, str ops only. */
> + gas_assert (opcode->iclass == ldst_imm9 || opcode->iclass == ldst_pos);
> + gas_assert (aarch64_num_of_operands (opcode) == 2);
> +
> + opnd1 = &base->operands[0];
> + addr = &base->operands[1];
> + store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
> +
> + addr_reg = ginsn_dw2_regnum (addr, true);
> +
> + /* STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}].
> + LDR <Xt>, [<Xn|SP>], #<simm>. */
> + opnd_reg = ginsn_dw2_regnum (opnd1, false);
> +
> + if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
> + mem_offset = inst.reloc.exp.X_add_number;
> + else
> + {
> + gas_assert (!addr->addr.offset.is_reg);
> + mem_offset = addr->addr.offset.imm;
> + }
> +
> + /* Handle address calculation. */
> + if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
> + {
> + ginsn_ind = ginsn_new_add (insn_end_sym, false,
> + GINSN_SRC_REG, addr_reg, 0,
> + GINSN_SRC_IMM, 0, mem_offset,
> + GINSN_DST_REG, addr_reg, 0);
> + ginsn_set_where (ginsn_ind);
> + }
> +
> + /* Save / restore of WZR is not of interest for SCFI. However, the address
> + processing component may have updated the stack pointer. At least, emit
> + that ginsn and return. PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
> + now; Check explicitly the regno for WZR. Also note,
> + TBD_GINSN_GEN_NOT_SCFI. */
> + if (opnd1->reg.regno == REG_SP /* WZR. */)
> + return ginsn_ind;
> +
> + /* With post-index addressing, the value is loaded from the
> + address in the base pointer, and then the pointer is updated.
> + With pre-index addressing, the addr computation has already
> + been explicitly done. */
> + offset = mem_offset;
> + if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
> + offset = 0;
Same comment as above.
> + if (target_big_endian && opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
> + offset += 8;
> +
> + if (store_p)
> + ginsn_mem = ginsn_new_store (insn_end_sym, false,
> + GINSN_SRC_REG, opnd_reg,
> + GINSN_DST_INDIRECT, addr_reg, offset);
> + else
> + ginsn_mem = ginsn_new_load (insn_end_sym, false,
> + GINSN_SRC_INDIRECT, addr_reg, offset,
> + GINSN_DST_REG, opnd_reg);
> + ginsn_set_where (ginsn_mem);
> +
> + if (addr->addr.preind && addr->addr.writeback)
> + gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem));
> + else if (addr->addr.postind && addr->addr.writeback)
> + gas_assert (!ginsn_link_next (ginsn_mem, ginsn_ind));
> +
> + /* Make note of the first instruction in the list. */
> + ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem;
> +
> + return ginsn;
> +}
> +
> +/* Generate ginsn for unconditional branch instructions. */
> +
> +static ginsnS *
> +aarch64_ginsn_branch_uncond (const symbolS *insn_end_sym)
> +{
> + ginsnS *ginsn = NULL;
> + const symbolS *src_symbol = NULL;
> + enum ginsn_src_type src_type = GINSN_SRC_UNKNOWN;
> + unsigned int src_reg = 0;
> +
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> +
> + if (opcode->iclass == branch_imm)
> + {
> + /* b or bl. opcode 0x14000000 or 0x94000000. */
> + gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_CALL26
> + || inst.reloc.type == BFD_RELOC_AARCH64_JUMP26);
It's possible to specify an immediate operand too:
b 4
> + src_symbol = inst.reloc.exp.X_add_symbol;
> + src_type = GINSN_SRC_SYMBOL;
> + }
> + else if (aarch64_num_of_operands (opcode) >= 1)
> + {
> + gas_assert (opcode->iclass == branch_reg);
> + /* Some insns (e.g., braa, blraa etc.) may have > 1 operands. For
> + current SCFI implementation, it suffices however to simply pass
> + the information about the first source. Although, strictly speaking,
> + (if reg) the source info is currently of no material use either. */
> + src_type = GINSN_SRC_REG;
> + src_reg = ginsn_dw2_regnum (&base->operands[0], false);
> + }
> +
> + if (aarch64_opcode_subclass_p (opcode, F_BRANCH_CALL))
> + {
> + gas_assert (src_type != GINSN_SRC_UNKNOWN);
> + ginsn = ginsn_new_call (insn_end_sym, true,
> + src_type, src_reg, src_symbol);
> + }
> + else if (aarch64_opcode_subclass_p (opcode, F_BRANCH_RET))
> + /* TBD_GINSN_REPRESENTATION_LIMIT. The following function to create a
> + GINSN_TYPE_RETURN does not allow src info ATM. */
> + ginsn = ginsn_new_return (insn_end_sym, true);
> + else
> + ginsn = ginsn_new_jump (insn_end_sym, true,
> + src_type, src_reg, src_symbol);
> +
> + ginsn_set_where (ginsn);
> +
> + return ginsn;
> +}
> +
> +/* Generate ginsn for conditional branch instructions. */
> +
> +static ginsnS *
> +aarch64_ginsn_branch_cond (const symbolS *insn_end_sym)
> +{
> + ginsnS *ginsn;
> + const symbolS *src_symbol;
> + enum ginsn_src_type src_type;
> +
> + gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_BRANCH19
> + || inst.reloc.type == BFD_RELOC_AARCH64_TSTBR14);
Similarly here, it's possible to write:
cbz x0, 4
> +
> + src_symbol = inst.reloc.exp.X_add_symbol;
> + src_type = GINSN_SRC_SYMBOL;
> + ginsn = ginsn_new_jump_cond (insn_end_sym, true, src_type, 0, src_symbol);
> + ginsn_set_where (ginsn);
> +
> + return ginsn;
> +}
> +
> +/* Generate ginsn for mov instructions. */
> +
> +static ginsnS *
> +aarch64_ginsn_mov (const symbolS *insn_end_sym)
> +{
> + ginsnS *ginsn = NULL;
> + unsigned int src_reg = 0, dst_reg;
> + aarch64_opnd_info *src, *dst;
> + offsetT src_imm = 0;
> + enum ginsn_src_type src_type;
> +
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> +
> + gas_assert (aarch64_num_of_operands (opcode) == 2);
> +
> + dst = &base->operands[0];
> + src = &base->operands[1];
> +
> + dst_reg = ginsn_dw2_regnum (dst, true);
> +
> + /* For some mov ops, e.g., movn, movk, or movz, there may optionally be more
> + work than just a simple mov. Skip handling these mov altogether and let
> + the aarch64_ginsn_unhandled () alert if these insns affect SCFI
> + correctness. TBD_GINSN_GEN_NOT_SCFI. */
> + if (src->type == AARCH64_OPND_HALF)
> + return ginsn;
> +
> + if (src->type == AARCH64_OPND_IMM_MOV
> + && aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
> + {
> + src_imm = inst.reloc.exp.X_add_number;
> + src_type = GINSN_SRC_IMM;
> + }
> + else
> + {
> + /* mov x27, sp. */
> + src_reg = ginsn_dw2_regnum (src, true);
> + src_type = GINSN_SRC_REG;
> + }
The condition makes it seem like we could enter the "else" for
src->type == AARCH64_OPND_IMM_MOV, although the code only accepts
registers.
It might be better to put the immediate and register cases in
separate functions, as for add/sub. It's probably safer to punt
for the immediate else case, since it is possible in principle
to have a relocated MOV.
> +
> + ginsn = ginsn_new_mov (insn_end_sym, false,
> + src_type, src_reg, src_imm,
> + GINSN_DST_REG, dst_reg, 0);
> + ginsn_set_where (ginsn);
> +
> + return ginsn;
> +}
> +
> +/* Check if an instruction is whitelisted.
> +
> + An instruction is a candidate for whitelisting if not generating ginsn for
> + it, does not affect SCFI correctness.
> +
> + TBD_GINSN_GEN_NOT_SCFI. This function assumes GINSN_GEN_SCFI is in effect.
> + When other ginsn_gen_mode are added, this will need fixing. */
> +
> +static bool
> +aarch64_ginsn_safe_to_skip_p (void)
> +{
> + bool skip_p = false;
> + aarch64_opnd_info *opnd = NULL;
> + unsigned int dw2_regnum;
> + unsigned int opnd_reg;
> + int num_opnds = 0;
> +
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> +
> + /* ATM, whitelisting operations with no operands does not seem to be
> + necessary. */
> + num_opnds = aarch64_num_of_operands (opcode);
> + if (!num_opnds)
> + return skip_p;
Things like ERET show that this would be dangerous, so it might be better
to make the false return explicit (and adjust the comment).
> +
> + opnd = &base->operands[0];
> +
> + switch (opcode->iclass)
> + {
> + case ldst_regoff:
> + /* It is not expected to have reg offset based ld/st ops to be used
> + for reg save and restore operations. Warn the user though. */
> + opnd_reg = ginsn_dw2_regnum (opnd, false);
> + if (aarch64_scfi_callee_saved_p (opnd_reg))
> + {
> + skip_p = true;
> + as_warn ("SCFI: ignored probable save/restore op with reg offset");
> + }
> + break;
> +
> + case dp_2src:
> + /* irg insn needs to be explicitly whitelisted. This is because the
> + dest is Rd_SP, but irg insn affects the tag only. To detect irg
> + insn, avoid an opcode-based check, however. */
I think we should check specifically for IRG (via subclasses).
Admittedly none of the others do anything sensible for SP, but other
instructions could be added in future.
> + if (opnd->type == AARCH64_OPND_Rd_SP)
> + {
> + dw2_regnum = ginsn_dw2_regnum (opnd, true);
> + if (dw2_regnum == REG_SP)
> + skip_p = true;
> + }
> + break;
> +
> + default:
> + break;
> + }
> +
> + return skip_p;
> +}
> +
> +#define AARCH64_GINSN_UNHANDLED_NONE 0
> +#define AARCH64_GINSN_UNHANDLED_DEST_REG 1
> +#define AARCH64_GINSN_UNHANDLED_CFG 2
> +#define AARCH64_GINSN_UNHANDLED_STACKOP 3
> +#define AARCH64_GINSN_UNHANDLED_UNEXPECTED 4
> +
> +/* Check the input insn for its impact on the correctness of the synthesized
> + CFI. Returns an error code to the caller. */
> +
> +static int
> +aarch64_ginsn_unhandled (void)
> +{
> + int err = AARCH64_GINSN_UNHANDLED_NONE;
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> + aarch64_opnd_info *dest = &base->operands[0];
> + int num_opnds = aarch64_num_of_operands (opcode);
> + aarch64_opnd_info *addr;
> + unsigned int dw2_regnum;
> + unsigned int addr_reg;
> + aarch64_opnd_info *opnd = NULL;
> + unsigned int opnd_reg;
> + bool sp_allowed_p = false;
> +
> + /* All change of flow instructions are important for SCFI. */
> + if (opcode->iclass == condbranch
> + || opcode->iclass == compbranch
> + || opcode->iclass == testbranch
> + || opcode->iclass == branch_imm
> + || opcode->iclass == branch_reg)
> + err = AARCH64_GINSN_UNHANDLED_CFG;
> + /* Also, any memory instructions that may involve an update to the stack
> + pointer or save/restore of callee-saved registers must not be skipped.
> + Note that, some iclasses cannot be used to push or pop stack because of
> + disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
> + loadlit, ldstnapair_offs. FIXME double-check.
> + Also, these iclasses do not seem to be amenable to being used for
> + save/restore ops either. FIXME double-check. */
> + else if (opcode->iclass == ldstpair_off
> + || opcode->iclass == ldstpair_indexed
> + || opcode->iclass == ldst_imm9
> + || opcode->iclass == ldst_imm10
> + || opcode->iclass == ldst_pos
> + /* STR Zn are especially complicated as they do not store in the same byte
> + order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
> + whereas STR Zn stores as a stream of bytes (LSB first). FIXME Simply punt
> + on the big-endian and little-endian SVE PCS case for now. */
> + || opcode->iclass == sve_misc)
> + {
> + opnd = &base->operands[0];
> + addr = &base->operands[num_opnds - 1];
> + addr_reg = ginsn_dw2_regnum (addr, true);
> + opnd_reg = ginsn_dw2_regnum (opnd, false);
> + /* For all skipped memory operations, check if an update to REG_SP or
> + REG_FP is involved. */
> + if ((addr_reg == REG_SP || addr_reg == REG_FP)
> + && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
> + || aarch64_scfi_callee_saved_p (opnd_reg)))
> +
> + err = AARCH64_GINSN_UNHANDLED_STACKOP;
The way I'd imagined this working is that we'd use two-directional data
flow to record which callee-saved registers are "protected" at which
instructions. That is, for saves we'd walk the cfg forward from the
entry point, recording which registers have been saved earlier in the walk
(and being conservatively correct for cycles). And for restores we'd
walk the cfg backwards from the exit points, recording which registers
are restored later in the walk. If a register is both "saved ealier" and
"restored later" for a given instruction, it wouldn't matter what the
instruction does with that register.
(For infinite loops we would pretend that all registers are restored later.)
It seems like instead, we'd generate a warning for:
...
str d8, [sp, #...]
...
ld1d z8.b, p0/z, [sp, #...]
...
ldr d8, [sp, #...]
...
ret
even though that should be ok (even without interpreting SVE instructions).
On the other hand, any read or write of a callee-saved register is suspicious
if it isn't saved earlier or isn't restored later.
In other words, it seems like this information should be context-dependent,
or used in a context-dependent way. Whether a particular register matters
depends on whether the register might still contain the caller's data.
Thanks,
Richard
> + }
> + /* Finally, irrespective of the iclass, check if the missed instructions are
> + affecting REG_SP or REG_FP. */
> + else if (dest && (dest->type == AARCH64_OPND_Rd
> + || dest->type == AARCH64_OPND_Rd_SP))
> + {
> + sp_allowed_p = (dest->type == AARCH64_OPND_Rd_SP) ? true : false;
> + dw2_regnum = ginsn_dw2_regnum (dest, sp_allowed_p);
> +
> + if (dw2_regnum == REG_SP || dw2_regnum == REG_FP)
> + err = AARCH64_GINSN_UNHANDLED_DEST_REG;
> + }
> +
> + return err;
> +}
> +
> +/* Generate one or more generic GAS instructions, a.k.a, ginsns for the
> + current machine instruction.
> +
> + Returns the head of linked list of ginsn(s) added, if success; Returns NULL
> + if failure.
> +
> + The input ginsn_gen_mode GMODE determines the set of minimal necessary
> + ginsns necessary for correctness of any passes applicable for that mode.
> + For supporting the GINSN_GEN_SCFI generation mode, following is the list of
> + machine instructions that must be translated into the corresponding ginsns
> + to ensure correctness of SCFI:
> + - All instructions affecting the two registers that could potentially
> + be used as the base register for CFA tracking. For SCFI, the base
> + register for CFA tracking is limited to REG_SP and REG_FP only.
> + - All change of flow instructions: conditional and unconditional
> + branches, call and return from functions.
> + - All instructions that can potentially be a register save / restore
> + operations.
> + - All instructions that may update the stack pointer: pre-indexed and
> + post-indexed stack operations with writeback.
> +
> + The function currently supports GINSN_GEN_SCFI ginsn generation mode only.
> + To support other generation modes will require work on this target-specific
> + process of creation of ginsns:
> + - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
> + possible starting points.
> + - Also note that ginsn representation may need enhancements. Specifically,
> + note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers.
> + */
> +
> +static ginsnS *
> +aarch64_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode)
> +{
> + int err = 0;
> + ginsnS *ginsn = NULL;
> + unsigned int dw2_regnum;
> + aarch64_opnd_info *dest = NULL;
> + bool sp_allowed_p = false;
> + aarch64_inst *base = &inst.base;
> + const aarch64_opcode *opcode = base->opcode;
> +
> + /* Currently supports generation of selected ginsns, sufficient for
> + the use-case of SCFI only. To remove this condition will require
> + work on this target-specific process of creation of ginsns. Some
> + of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
> + examples. */
> + if (gmode != GINSN_GEN_SCFI)
> + return ginsn;
> +
> + switch (opcode->iclass)
> + {
> + case addsub_ext:
> + /* TBD_GINSN_GEN_NOT_SCFI: other insns are not of interest for SCFI. */
> + if (aarch64_opcode_subclass_p (opcode, F_ARITH_ADD)
> + || aarch64_opcode_subclass_p (opcode, F_ARITH_SUB))
> + ginsn = aarch64_ginsn_addsub_reg (insn_end_sym);
> + break;
> +
> + case addsub_imm:
> + if (aarch64_opcode_subclass_p (opcode, F_ARITH_MOV))
> + ginsn = aarch64_ginsn_mov (insn_end_sym);
> + else if (aarch64_opcode_subclass_p (opcode, F_ARITH_ADD)
> + || aarch64_opcode_subclass_p (opcode, F_ARITH_SUB))
> + ginsn = aarch64_ginsn_addsub_imm (insn_end_sym);
> + break;
> +
> + case movewide:
> + ginsn = aarch64_ginsn_mov (insn_end_sym);
> + break;
> +
> + case ldst_imm9:
> + case ldst_pos:
> + ginsn = aarch64_ginsn_ldstr (insn_end_sym);
> + break;
> +
> + case ldstpair_indexed:
> + case ldstpair_off:
> + ginsn = aarch64_ginsn_ldstp (insn_end_sym);
> + break;
> +
> + case branch_imm:
> + case branch_reg:
> + ginsn = aarch64_ginsn_branch_uncond (insn_end_sym);
> + break;
> +
> + case compbranch:
> + /* Although cbz/cbnz has an additional operand and are functionally
> + distinct from conditional branches, it is fine to use the same ginsn
> + type for both from the perspective of SCFI. */
> + case testbranch:
> + case condbranch:
> + ginsn = aarch64_ginsn_branch_cond (insn_end_sym);
> + break;
> +
> + default:
> + /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for
> + GINSN_GEN_SCFI mode. */
> + break;
> + }
> +
> + if (!ginsn && !aarch64_ginsn_safe_to_skip_p ())
> + {
> + /* For all unhandled insns, check that they no not impact SCFI
> + correctness. */
> + err = aarch64_ginsn_unhandled ();
> + switch (err)
> + {
> + case AARCH64_GINSN_UNHANDLED_NONE:
> + break;
> + case AARCH64_GINSN_UNHANDLED_DEST_REG:
> + /* Not all writes to REG_FP are harmful in context of SCFI. Simply
> + generate a GINSN_TYPE_OTHER with destination set to the
> + appropriate register. The SCFI machinery will bail out if this
> + ginsn affects SCFI correctness. */
> + dest = &base->operands[0];
> + sp_allowed_p = (dest->type == AARCH64_OPND_Rd_SP) ? true : false;
> + dw2_regnum = ginsn_dw2_regnum (dest, sp_allowed_p);
> + ginsn = ginsn_new_other (insn_end_sym, true,
> + GINSN_SRC_IMM, 0,
> + GINSN_SRC_IMM, 0,
> + GINSN_DST_REG, dw2_regnum);
> + ginsn_set_where (ginsn);
> + break;
> + case AARCH64_GINSN_UNHANDLED_CFG:
> + case AARCH64_GINSN_UNHANDLED_STACKOP:
> + as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"),
> + opcode->opcode);
> + break;
> + case AARCH64_GINSN_UNHANDLED_UNEXPECTED:
> + as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"),
> + opcode->opcode);
> + break;
> + default:
> + abort ();
> + break;
> + }
> + }
> +
> + return ginsn;
> +}
> +
> +#endif /* OBJ_ELF. */
> +
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 5d15ee9fc02..4f4dd404551 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -33,6 +33,7 @@
> #include "dw2gencfi.h"
> #include "sframe.h"
> #include "gen-sframe.h"
> +#include "scfi.h"
> #endif
>
> #include "dw2gencfi.h"
> @@ -8591,6 +8592,10 @@ dump_opcode_operands (const aarch64_opcode *opcode)
> }
> #endif /* DEBUG_AARCH64 */
>
> +#ifdef OBJ_ELF
> +# include "tc-aarch64-ginsn.c"
> +#endif
> +
> /* This is the guts of the machine-dependent assembler. STR points to a
> machine dependent instruction. This function is supposed to emit
> the frags/bytes it assembles to. */
> @@ -8728,6 +8733,16 @@ md_assemble (char *str)
> output_inst (copy);
> }
>
> +#ifdef OBJ_ELF
> + if (flag_synth_cfi)
> + {
> + ginsnS *ginsn;
> + ginsn = aarch64_ginsn_new (symbol_temp_new_now (),
> + frch_ginsn_gen_mode ());
> + frch_ginsn_data_append (ginsn);
> + }
> +#endif
> +
> /* Issue non-fatal messages if any. */
> output_operand_error_report (str, true);
> return;
> diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
> index 1b8badad9fd..4906a6e7000 100644
> --- a/gas/config/tc-aarch64.h
> +++ b/gas/config/tc-aarch64.h
> @@ -263,6 +263,27 @@ extern void aarch64_after_parse_args (void);
>
> #ifdef OBJ_ELF
>
> +#define TARGET_USE_GINSN 1
> +/* Allow GAS to synthesize DWARF CFI for hand-written asm.
> + PS: TARGET_USE_CFIPOP is a pre-condition. */
> +#define TARGET_USE_SCFI 1
> +/* Identify the maximum DWARF register number of all the registers being
> + tracked for SCFI. This is the last DWARF register number of the set
> + of SP, FP, and all callee-saved registers. For Aarch64, this means 79
> + because FP/Advanced SIMD v8-v15 are also callee-saved registers. */
> +# define SCFI_MAX_REG_ID 79
> +/* Identify the DWARF register number of the frame-pointer register. */
> +# define REG_FP 29
> +/* Identify the DWARF register number of the link register. */
> +# define REG_LR 30
> +/* Identify the DWARF register number of the stack-pointer register. */
> +# define REG_SP 31
> +
> +#define SCFI_INIT_CFA_OFFSET 0
> +
> +#define SCFI_CALLEE_SAVED_REG_P(dw2reg) aarch64_scfi_callee_saved_p (dw2reg)
> +extern bool aarch64_scfi_callee_saved_p (uint32_t dw2reg_num);
> +
> /* Whether SFrame stack trace info is supported. */
> extern bool aarch64_support_sframe_p (void);
> #define support_sframe_p aarch64_support_sframe_p
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI
2024-07-01 19:49 ` Richard Sandiford
@ 2024-07-11 6:30 ` Indu Bhagat
2024-07-11 13:15 ` Richard Sandiford
0 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-11 6:30 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/1/24 12:49, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> [Changes in V4]
>> - Use data types uniformly. Use 'unsigned int' instead of 'uint32_t'
>> for DWARF register numbers. Use offsetT where applicable.
>> - Minor code restructuring in aarch64_ginsn_safe_to_skip_p (). Move
>> common code out of switch case.
>> - Add FP/Advanced SIMD registers to callee-saved registers too.
>> Updated commit log to include some of the details.
>> - Check for opnd type AARCH64_OPND_QLF_W or AARCH64_OPND_QLF_S_S in
>> aarch64_ginsn_ldstp () to detect 32-bit word operations.
>> - Skip generating ginsns for movk, movz, movn. These do more work than
>> just simple mov; Skip generating ginsn altogether for these.
>> - ginsn_dw2_regnum () is now switch case on opnd_class. Each case
>> exposed by the current set of ginsn creation logic is handled.
>> - Skip Z register usage altogether for now. Skip sve_misc iclass but
>> error out if callee-saved FP/Advanced SIMD registers or stack
>> management are involved.
>> [End of changes in V4]
>>
>> [No changes in V3]
>>
>> [Changes in V2]
>> - Factored out the ginsn creation functionality from tc-aarch64.c into
>> tc-aarch64-ginsn.c.
>> - The switch case in aarch64_ginsn_new now is based on iclass rather
>> than (earlier) opcode.
>> - Rename aarch64_ginsn_jump / aarch64_ginsn_jump_cond to
>> aarch64_ginsn_branch_uncond / aarch64_ginsn_branch_cond respectively.
>> - Explicitly whitelist irg insn.
>> - Other minor code comment and readability fixes.
>> [End of changes in V2]
>>
>> For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in
>> GAS works on the generic GAS insns (ginsns). This patch adds support in
>> the aarch64 backend to create ginsns for a subset of the supported
>> machine instructions. The subset includes the minimal necessary
>> instructions to ensure SCFI correctness:
>>
>> - Any potential register saves and unsaves. Hence, process instructions
>> belonging to a variety of iclasses involving str, ldr, stp, ldp.
>> - Any change of flow instructions. This includes all conditional and
>> unconditional branches, call (bl, blr, etc.) and return.
>> - Most importantly, any instruction that could affect the two registers
>> of interest: REG_SP, REG_FP. This set includes all pre-indexed and
>> post-indexed memory operations, with writeback, on the stack. This
>> set must also include other instructions (e.g., arithmetic insns)
>> where the destination register is one of the afore-mentioned registers.
>>
>> With respect to callee-saved registers in Aarch64, FP/Advanced SIMD
>> registers D8-D15 are included along with the relevant GPRs. Calculating
>> offsets for loads and stores especially for Q registers needs special
>> attention here.
>>
>> As an example,
>> str q8, [sp, #16]
>> On big-endian:
>> STR Qn stores as a 128-bit integer (MSB first), hence, should record
>> D8 as being saved at sp+24 rather than sp+16.
>> On little-endian:
>> should record D8 as being saved at sp+16
>>
>> D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used;
>> hence, they remain "interesting" for SCFI purposes in such cases. A CFI
>> save slot always represents the low 64 bits, regardless of whether a
>> save occurs on D, Q or Z registers. Currently, the ginsn creation
>> machinery can handle D and Q registers on little-endian and big-endian.
>>
>> Apart from creating ginsn, another key responsibility of the backend is
>> to make sure there are safeguards in place to detect and alert if an
>> instruction of interest may have been skipped. This is done via
>> aarch64_ginsn_unhandled () (similar to the x86 backend). This function
>> , hence, is also intended to alert when future ISA changes may otherwise
>> render SCFI results incorrect, because of missing ginsns for the newly
>> added machine instructions.
>>
>> At this time, becuase of the complexities wrt endianness in handling Z
>> register usage, skip sve_misc opclass altogether for now. The SCFI
>> machinery will error out (using the aarch64_ginsn_unhandled () code
>> path) though if Z register usage affects correctness.
>>
>> The current SCFI machinery does not currently synthesize the
>> PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame. The
>> support for this is planned for near future.
>>
>> SCFI is enabled for ELF targets only.
>>
>> gas/
>> * config/tc-aarch64-ginsn.c: New file.
>> * config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c
>> file. Invoke aarch64_ginsn_new.
>> * config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI
>> enablement.
>> (TARGET_USE_SCFI): Likewise.
>> (SCFI_MAX_REG_ID): New definition.
>> (REG_FP): Likewise.
>> (REG_LR): Likewise.
>> (REG_SP): Likewise.
>> (SCFI_INIT_CFA_OFFSET): Likewise.
>> (SCFI_CALLEE_SAVED_REG_P): Likewise.
>> (aarch64_scfi_callee_saved_p): New declaration.
>> ---
>> gas/config/tc-aarch64-ginsn.c | 797 ++++++++++++++++++++++++++++++++++
>> gas/config/tc-aarch64.c | 15 +
>> gas/config/tc-aarch64.h | 21 +
>> 3 files changed, 833 insertions(+)
>> create mode 100644 gas/config/tc-aarch64-ginsn.c
>>
>> diff --git a/gas/config/tc-aarch64-ginsn.c b/gas/config/tc-aarch64-ginsn.c
>> new file mode 100644
>> index 00000000000..dbee8df88b1
>> --- /dev/null
>> +++ b/gas/config/tc-aarch64-ginsn.c
>> @@ -0,0 +1,797 @@
>> +/* tc-aarch64-ginsn.c -- Ginsn generation for the AArch64 ISA
>> +
>> + Copyright (C) 2024 Free Software Foundation, Inc.
>> + Contributed by ARM Ltd.
>
> Not so :)
>
Removed the line.
>> +
>> + This file is part of GAS.
>> +
>> + GAS is free software; you can redistribute it and/or modify
>> + it under the terms of the GNU General Public License as published by
>> + the Free Software Foundation; either version 3 of the license, or
>> + (at your option) any later version.
>> +
>> + GAS is distributed in the hope that it will be useful,
>> + but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + GNU General Public License for more details.
>> +
>> + You should have received a copy of the GNU General Public License
>> + along with this program; see the file COPYING3. If not,
>> + see <http://www.gnu.org/licenses/>. */
>> +
>> +/* This file contains the implementation of the ginsn creation for aarch64
>> + instructions. Most functions will read the aarch64_instruction inst
>> + object, but none should need to modify it. */
>> +
>> +#ifdef OBJ_ELF
>> +
>> +/* DWARF register number for R1. Used as dummy value when WZR. */
>> +#define GINSN_DW2_REGNUM_R1_DUMMY 1
>> +
>> +/* Return whether the given register number is a callee-saved register for
>> + SCFI purposes.
>> +
>> + Apart from the callee-saved GPRs, SCFI always tracks SP, FP and LR
>> + additionally. As for the FP/Advanced SIMD registers, v8-v15 are
>> + callee-saved. */
>> +
>> +bool
>> +aarch64_scfi_callee_saved_p (unsigned int dw2reg_num)
>> +{
>> + /* PS: Ensure SCFI_MAX_REG_ID is the max DWARF register number to cover
>> + all the registers here. */
>> + if (dw2reg_num == REG_SP /* x31. */
>> + || dw2reg_num == REG_FP /* x29. */
>> + || dw2reg_num == REG_LR /* x30. */
>> + || (dw2reg_num >= 19 && dw2reg_num <= 28) /* x19 - x28. */
>> + || (dw2reg_num >= 72 && dw2reg_num <= 79) /* v8 - v15. */)
>> + return true;
>> +
>> + return false;
>> +}
>> +
>> +/* Get the DWARF register number for the given OPND.
>> + Whether 31 is used to encode WZR or SP is specified via SP_ALLOWED_P.
>> +
>> + The caller must decide the value of SP_ALLOWED_P based on the instruction
>> + encoding. */
>> +
>> +static unsigned int
>> +ginsn_dw2_regnum (aarch64_opnd_info *opnd, bool sp_allowed_p)
>
> Couldn't this use operand_maybe_stack_pointer instead of taking
> an sp_allowed_p parameter?
>
Thanks. I can get rid of sp_allowed_p arg altogether now, and simply use:
if (aarch64_zero_register_p (opnd))
dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
else
...
for appropriate opnd_class. The sp_allowed_p was only to detect WZR vs
REG_SP.
>> +{
>> + enum aarch64_operand_class opnd_class;
>> + unsigned int dw2reg_num = 0;
>> +
>> + opnd_class = aarch64_get_operand_class (opnd->type);
>> +
>> + switch (opnd_class)
>> + {
>> + case AARCH64_OPND_CLASS_FP_REG:
>> + dw2reg_num = opnd->reg.regno + 64;
>> + break;
>> + case AARCH64_OPND_CLASS_SVE_REGLIST:
>> + dw2reg_num = opnd->reglist.first_regno + 64;
>> + break;
>> + case AARCH64_OPND_CLASS_MODIFIED_REG:
>> + case AARCH64_OPND_CLASS_INT_REG:
>> + case AARCH64_OPND_CLASS_ADDRESS:
>> + /* Use a dummy register value in case of WZR, else this will be an
>> + incorrect dependency on REG_SP. */
>> + if (!sp_allowed_p && opnd->reg.regno == REG_SP)
>> + dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>> + else
>> + /* For GPRs of our interest (callee-saved regs, SP, FP, LR),
>> + DWARF register number is the same as AArch64 register number. */
>> + dw2reg_num = opnd->reg.regno;
>> + break;
>
> I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
> instead. AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
>
Made the correction for AARCH64_OPND_CLASS_ADDRESS.
But for AARCH64_OPND_CLASS_MODIFIED_REG, the register information is
still correct in opnd->reg.regno, IIUC. It seems to me that the only
information available in the opnd->shifter is how the register is
modified by additional work (shift, multiply etc.); This information is
not used by SCFI:
- an add/sub with two source register and destination REG_SP/ REG_FP
makes REG_SP/ REG_FP untraceable. So ignoring the shift amount etc does
not hurt SCFI correctness.
- Cant think of other operations where the shift amount will affect
SCFI correctness..
So I am not sure of the "AARCH64_OPND_CLASS_MODIFIED_REG should look at
opnd->shifter." of the review comment.
>> + case AARCH64_OPND_CLASS_SYSTEM:
>> + /* For prfm etc., where a opnd->type AARCH64_OPND_PRFOP is seen. */
>> + dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>> + break;
>
> Hopefully this goes away if we treat PRFM as "other".
>
There were workflows from aarch64_ginsn_unhandled () where we were
calling ginsn_dw2_regnum (). But I have now corrected that callsite to
first check for !aarch64_opcode_subclass_p (opcode, F_SUBCLASS_OTHER)
which was necessary to be checked anyway.
So, yes, this stub for AARCH64_OPND_CLASS_SYSTEM in ginsn_dw2_regnum ()
can now go away.
>> + default:
>> + as_bad ("Unexpected value in ginsn_dw2_regnum");
>> + break;
>> + }
>> +
>> + return dw2reg_num;
>> +}
>> +
>> +/* Generate ginsn for addsub instructions with immediate opnd. */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
>> +{
>> + ginsnS *ginsn = NULL;
>> + bool add_p, sub_p;
>> + offsetT src_imm = 0;
>> + unsigned int dst_reg, opnd_reg;
>> + aarch64_opnd_info *dst, *opnd;
>> + ginsnS *(*ginsn_func) (const symbolS *, bool,
>> + enum ginsn_src_type, unsigned int, offsetT,
>> + enum ginsn_src_type, unsigned int, offsetT,
>> + enum ginsn_dst_type, unsigned int, offsetT);
>> +
>> + aarch64_inst *base = &inst.base;
>> + const aarch64_opcode *opcode = base->opcode;
>> +
>> + add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>> + sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>> + gas_assert (add_p || sub_p);
>> + ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>> +
>> + gas_assert (aarch64_num_of_operands (opcode) == 3);
>> + dst = &base->operands[0];
>> + opnd = &base->operands[1];
>> +
>> + dst_reg = ginsn_dw2_regnum (dst, true);
>> +
>> + if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>> + src_imm = inst.reloc.exp.X_add_number;
>> + /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
>> + and handle via aarch64_ginsn_unhandled () code path. */
>> + else if (inst.reloc.type != BFD_RELOC_UNUSED)
>> + return ginsn;
>> + /* FIXME - verify the understanding and remove assert. */
>> + else
>> + gas_assert (0);
>> +
>> + opnd_reg = ginsn_dw2_regnum (opnd, true);
>> +
>> + ginsn = ginsn_func (insn_end_sym, true,
>> + GINSN_SRC_REG, opnd_reg, 0,
>> + GINSN_SRC_IMM, 0, src_imm,
>> + GINSN_DST_REG, dst_reg, 0);
>> + ginsn_set_where (ginsn);
>> +
>> + return ginsn;
>> +}
>> +
>> +/* Generate ginsn for addsub instructions with reg opnd. */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
>> +{
>> + ginsnS *ginsn = NULL;
>> + bool add_p, sub_p;
>> + unsigned int dst_reg, src1_reg, src2_reg;
>> + aarch64_opnd_info *dst, *src1, *src2;
>> + ginsnS *(*ginsn_func) (const symbolS *, bool,
>> + enum ginsn_src_type, unsigned int, offsetT,
>> + enum ginsn_src_type, unsigned int, offsetT,
>> + enum ginsn_dst_type, unsigned int, offsetT);
>> +
>> + aarch64_inst *base = &inst.base;
>> + const aarch64_opcode *opcode = base->opcode;
>> +
>> + add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>> + sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>> + gas_assert (add_p || sub_p);
>> + ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>> +
>> + gas_assert (aarch64_num_of_operands (opcode) == 3);
>> + dst = &base->operands[0];
>> + src1 = &base->operands[1];
>> + src2 = &base->operands[2];
>> +
>> + dst_reg = ginsn_dw2_regnum (dst, true);
>> + src1_reg = ginsn_dw2_regnum (src1, true);
>> + src2_reg = ginsn_dw2_regnum (src2, false);
>> +
>> + ginsn = ginsn_func (insn_end_sym, true,
>> + GINSN_SRC_REG, src1_reg, 0,
>> + GINSN_SRC_REG, src2_reg, 0,
>> + GINSN_DST_REG, dst_reg, 0);
>> + ginsn_set_where (ginsn);
>
> It looks like this ignores any shift that is applied to src2_reg.
>
Yes. An add/sub operation with two source registers makes REG_SP/REG_FP
untraceable (if dest is REG_SP/REG_FP), so any further information
carried forward in the ginsn is of little use for SCFI.
For a usecase apart from SCFI, yes, this may amount to loss of vital
information. I will add a TBD_GINSN_INFO_LOSS comment.
>> +
>> + return ginsn;
>> +}
>> +
>> +/* Generate ginsn for the load pair and store pair instructions. */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_ldstp (const symbolS *insn_end_sym)
>> +{
>> + ginsnS *ginsn = NULL;
>> + ginsnS *ginsn_ind = NULL;
>> + ginsnS *ginsn_mem1 = NULL;
>> + ginsnS *ginsn_mem2 = NULL;
>> + unsigned int opnd_reg, addr_reg;
>> + offsetT offset, mem_offset;
>> + unsigned int width = 8;
>> + bool store_p = false;
>> +
>> + aarch64_opnd_info *opnd1, *opnd2, *addr;
>> + aarch64_inst *base = &inst.base;
>> + const aarch64_opcode *opcode = base->opcode;
>> +
>> + /* This function is for handling ldp / stp ops only. */
>> + gas_assert (opcode->iclass == ldstpair_indexed
>> + || opcode->iclass == ldstpair_off);
>> + gas_assert (aarch64_num_of_operands (opcode) == 3);
>> +
>> + opnd1 = &base->operands[0];
>> + opnd2 = &base->operands[1];
>> + addr = &base->operands[2];
>> + store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
>> +
>> + addr_reg = ginsn_dw2_regnum (addr, true);
>> + gas_assert (!addr->addr.offset.is_reg);
>> + mem_offset = addr->addr.offset.imm;
>> +
>> + /* ldstp may load or store two 32-bit words or two 64-bit doublewords. */
>> + if (opnd1->qualifier == AARCH64_OPND_QLF_W
>> + || opnd1->qualifier == AARCH64_OPND_QLF_S_S)
>> + width = 4;
>> +
>> + /* Handle address calculation. */
>> + if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
>> + {
>> + /* Pre-indexed store, e.g., stp x29, x30, [sp, -128]!
>> + Pre-indexed addressing is like offset addressing, except that
>> + the base pointer is updated as a result of the instruction.
>> +
>> + Post-indexed store, e.g., stp x29, x30, [sp],128
>> + Post-index addressing is useful for popping off the stack. The
>> + instruction loads the value from the location pointed at by the stack
>> + pointer, and then moves the stack pointer on to the next full location
>> + in the stack. */
>> + ginsn_ind = ginsn_new_add (insn_end_sym, false,
>> + GINSN_SRC_REG, addr_reg, 0,
>> + GINSN_SRC_IMM, 0, mem_offset,
>> + GINSN_DST_REG, addr_reg, 0);
>> + ginsn_set_where (ginsn_ind);
>> + }
>> +
>> + /* Save / restore of WZR is not of interest for SCFI. However, the address
>> + processing component may have updated the stack pointer. At least, emit
>> + that ginsn and return. PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
>> + now; Check explicitly the regno for WZR. Also note,
>> + TBD_GINSN_GEN_NOT_SCFI. */
>> + if (opnd1->reg.regno == REG_SP /* WZR. */)
>> + return ginsn_ind;
>> +
>> + /* With post-index addressing, the value is loaded from the
>> + address in the base pointer, and then the pointer is updated.
>> + With pre-index addressing, the addr computation has already
>> + been explicitly done. */
>> + offset = mem_offset;
>> + if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>> + offset = 0;
>
> I guess this is personal taste, but IMO it would be easier to follow if
> this were combined with the "if" above, so that the compensating action
> of ginsn_ind is next to the creation of ginsn_ind itself.
>
Yes, makes it easier to parse. I have restructured the code a bit.
>> +
>> + if (opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
>> + {
>> + width = 16;
>> + if (target_big_endian)
>> + offset += 8;
>> + }
>> +
>> + opnd_reg = ginsn_dw2_regnum (opnd1, false);
>> + if (store_p)
>> + {
>> + ginsn_mem1 = ginsn_new_store (insn_end_sym, false,
>> + GINSN_SRC_REG, opnd_reg,
>> + GINSN_DST_INDIRECT, addr_reg, offset);
>> + ginsn_set_where (ginsn_mem1);
>> +
>> + opnd_reg = ginsn_dw2_regnum (opnd2, false);
>> + ginsn_mem2 = ginsn_new_store (insn_end_sym, false,
>> + GINSN_SRC_REG, opnd_reg,
>> + GINSN_DST_INDIRECT, addr_reg,
>> + offset + width);
>> + ginsn_set_where (ginsn_mem2);
>> + }
>> + else
>> + {
>> + opnd_reg = ginsn_dw2_regnum (opnd1, false);
>> + ginsn_mem1 = ginsn_new_load (insn_end_sym, false,
>> + GINSN_SRC_INDIRECT, addr_reg, offset,
>> + GINSN_DST_REG, opnd_reg);
>> + ginsn_set_where (ginsn_mem1);
>> +
>> + opnd_reg = ginsn_dw2_regnum (opnd2, false);
>> + ginsn_mem2 = ginsn_new_load (insn_end_sym, false,
>> + GINSN_SRC_INDIRECT, addr_reg, offset + width,
>> + GINSN_DST_REG, opnd_reg);
>> + ginsn_set_where (ginsn_mem2);
>> + }
>> +
>> + /* Link the list of ginsns created. */
>> + if (addr->addr.preind && addr->addr.writeback)
>> + gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem1));
>> +
>> + gas_assert (!ginsn_link_next (ginsn_mem1, ginsn_mem2));
>> +
>> + if (addr->addr.postind && addr->addr.writeback)
>> + gas_assert (!ginsn_link_next (ginsn_mem2, ginsn_ind));
>> +
>> + /* Make note of the first instruction in the list. */
>> + ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem1;
>> + return ginsn;
>> +}
>> +
>> +/* Generate ginsn for load and store instructions. */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_ldstr (const symbolS *insn_end_sym)
>> +{
>> + ginsnS *ginsn = NULL;
>> + ginsnS *ginsn_ind = NULL;
>> + ginsnS *ginsn_mem = NULL;
>> + unsigned int opnd_reg, addr_reg;
>> + offsetT offset, mem_offset;
>> + bool store_p = false;
>> +
>> + aarch64_opnd_info *opnd1, *addr;
>> + aarch64_inst *base = &inst.base;
>> + const aarch64_opcode *opcode = base->opcode;
>> +
>> + /* This function is for handling ldr, str ops only. */
>> + gas_assert (opcode->iclass == ldst_imm9 || opcode->iclass == ldst_pos);
>> + gas_assert (aarch64_num_of_operands (opcode) == 2);
>> +
>> + opnd1 = &base->operands[0];
>> + addr = &base->operands[1];
>> + store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
>> +
>> + addr_reg = ginsn_dw2_regnum (addr, true);
>> +
>> + /* STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}].
>> + LDR <Xt>, [<Xn|SP>], #<simm>. */
>> + opnd_reg = ginsn_dw2_regnum (opnd1, false);
>> +
>> + if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>> + mem_offset = inst.reloc.exp.X_add_number;
>> + else
>> + {
>> + gas_assert (!addr->addr.offset.is_reg);
>> + mem_offset = addr->addr.offset.imm;
>> + }
>> +
>> + /* Handle address calculation. */
>> + if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
>> + {
>> + ginsn_ind = ginsn_new_add (insn_end_sym, false,
>> + GINSN_SRC_REG, addr_reg, 0,
>> + GINSN_SRC_IMM, 0, mem_offset,
>> + GINSN_DST_REG, addr_reg, 0);
>> + ginsn_set_where (ginsn_ind);
>> + }
>> +
>> + /* Save / restore of WZR is not of interest for SCFI. However, the address
>> + processing component may have updated the stack pointer. At least, emit
>> + that ginsn and return. PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
>> + now; Check explicitly the regno for WZR. Also note,
>> + TBD_GINSN_GEN_NOT_SCFI. */
>> + if (opnd1->reg.regno == REG_SP /* WZR. */)
>> + return ginsn_ind;
>> +
>> + /* With post-index addressing, the value is loaded from the
>> + address in the base pointer, and then the pointer is updated.
>> + With pre-index addressing, the addr computation has already
>> + been explicitly done. */
>> + offset = mem_offset;
>> + if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>> + offset = 0;
>
> Same comment as above.
>
Done.
>> + if (target_big_endian && opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
>> + offset += 8;
>> +
>> + if (store_p)
>> + ginsn_mem = ginsn_new_store (insn_end_sym, false,
>> + GINSN_SRC_REG, opnd_reg,
>> + GINSN_DST_INDIRECT, addr_reg, offset);
>> + else
>> + ginsn_mem = ginsn_new_load (insn_end_sym, false,
>> + GINSN_SRC_INDIRECT, addr_reg, offset,
>> + GINSN_DST_REG, opnd_reg);
>> + ginsn_set_where (ginsn_mem);
>> +
>> + if (addr->addr.preind && addr->addr.writeback)
>> + gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem));
>> + else if (addr->addr.postind && addr->addr.writeback)
>> + gas_assert (!ginsn_link_next (ginsn_mem, ginsn_ind));
>> +
>> + /* Make note of the first instruction in the list. */
>> + ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem;
>> +
>> + return ginsn;
>> +}
>> +
>> +/* Generate ginsn for unconditional branch instructions. */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_branch_uncond (const symbolS *insn_end_sym)
>> +{
>> + ginsnS *ginsn = NULL;
>> + const symbolS *src_symbol = NULL;
>> + enum ginsn_src_type src_type = GINSN_SRC_UNKNOWN;
>> + unsigned int src_reg = 0;
>> +
>> + aarch64_inst *base = &inst.base;
>> + const aarch64_opcode *opcode = base->opcode;
>> +
>> + if (opcode->iclass == branch_imm)
>> + {
>> + /* b or bl. opcode 0x14000000 or 0x94000000. */
>> + gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_CALL26
>> + || inst.reloc.type == BFD_RELOC_AARCH64_JUMP26);
>
> It's possible to specify an immediate operand too:
>
> b 4
>
I should explicitly skip these instructions and error out. These
instructions make CFG creation not easy.
The same behaviour should be done for "b symbol+1", i.e., symbol+addend.
>> + src_symbol = inst.reloc.exp.X_add_symbol;
>> + src_type = GINSN_SRC_SYMBOL;
>> + }
>> + else if (aarch64_num_of_operands (opcode) >= 1)
>> + {
>> + gas_assert (opcode->iclass == branch_reg);
>> + /* Some insns (e.g., braa, blraa etc.) may have > 1 operands. For
>> + current SCFI implementation, it suffices however to simply pass
>> + the information about the first source. Although, strictly speaking,
>> + (if reg) the source info is currently of no material use either. */
>> + src_type = GINSN_SRC_REG;
>> + src_reg = ginsn_dw2_regnum (&base->operands[0], false);
>> + }
>> +
>> + if (aarch64_opcode_subclass_p (opcode, F_BRANCH_CALL))
>> + {
>> + gas_assert (src_type != GINSN_SRC_UNKNOWN);
>> + ginsn = ginsn_new_call (insn_end_sym, true,
>> + src_type, src_reg, src_symbol);
>> + }
>> + else if (aarch64_opcode_subclass_p (opcode, F_BRANCH_RET))
>> + /* TBD_GINSN_REPRESENTATION_LIMIT. The following function to create a
>> + GINSN_TYPE_RETURN does not allow src info ATM. */
>> + ginsn = ginsn_new_return (insn_end_sym, true);
>> + else
>> + ginsn = ginsn_new_jump (insn_end_sym, true,
>> + src_type, src_reg, src_symbol);
>> +
>> + ginsn_set_where (ginsn);
>> +
>> + return ginsn;
>> +}
>> +
>> +/* Generate ginsn for conditional branch instructions. */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_branch_cond (const symbolS *insn_end_sym)
>> +{
>> + ginsnS *ginsn;
>> + const symbolS *src_symbol;
>> + enum ginsn_src_type src_type;
>> +
>> + gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_BRANCH19
>> + || inst.reloc.type == BFD_RELOC_AARCH64_TSTBR14);
>
> Similarly here, it's possible to write:
>
> cbz x0, 4
>
Thank you for bringing these up. I will need to explicitly skip these
instructions and error out. These instructions make CFG creation not easy.
>> +
>> + src_symbol = inst.reloc.exp.X_add_symbol;
>> + src_type = GINSN_SRC_SYMBOL;
>> + ginsn = ginsn_new_jump_cond (insn_end_sym, true, src_type, 0, src_symbol);
>> + ginsn_set_where (ginsn);
>> +
>> + return ginsn;
>> +}
>> +
>> +/* Generate ginsn for mov instructions. */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_mov (const symbolS *insn_end_sym)
>> +{
>> + ginsnS *ginsn = NULL;
>> + unsigned int src_reg = 0, dst_reg;
>> + aarch64_opnd_info *src, *dst;
>> + offsetT src_imm = 0;
>> + enum ginsn_src_type src_type;
>> +
>> + aarch64_inst *base = &inst.base;
>> + const aarch64_opcode *opcode = base->opcode;
>> +
>> + gas_assert (aarch64_num_of_operands (opcode) == 2);
>> +
>> + dst = &base->operands[0];
>> + src = &base->operands[1];
>> +
>> + dst_reg = ginsn_dw2_regnum (dst, true);
>> +
>> + /* For some mov ops, e.g., movn, movk, or movz, there may optionally be more
>> + work than just a simple mov. Skip handling these mov altogether and let
>> + the aarch64_ginsn_unhandled () alert if these insns affect SCFI
>> + correctness. TBD_GINSN_GEN_NOT_SCFI. */
>> + if (src->type == AARCH64_OPND_HALF)
>> + return ginsn;
>> +
>> + if (src->type == AARCH64_OPND_IMM_MOV
>> + && aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>> + {
>> + src_imm = inst.reloc.exp.X_add_number;
>> + src_type = GINSN_SRC_IMM;
>> + }
>> + else
>> + {
>> + /* mov x27, sp. */
>> + src_reg = ginsn_dw2_regnum (src, true);
>> + src_type = GINSN_SRC_REG;
>> + }
>
> The condition makes it seem like we could enter the "else" for
> src->type == AARCH64_OPND_IMM_MOV, although the code only accepts
> registers.
>
> It might be better to put the immediate and register cases in
> separate functions, as for add/sub. It's probably safer to punt
> for the immediate else case, since it is possible in principle
> to have a relocated MOV.
>
Okay. I have created two versions of the mov functions:
- aarch64_ginsn_mov_imm
- aarch64_ginsn_mov_reg
>> +
>> + ginsn = ginsn_new_mov (insn_end_sym, false,
>> + src_type, src_reg, src_imm,
>> + GINSN_DST_REG, dst_reg, 0);
>> + ginsn_set_where (ginsn);
>> +
>> + return ginsn;
>> +}
>> +
>> +/* Check if an instruction is whitelisted.
>> +
>> + An instruction is a candidate for whitelisting if not generating ginsn for
>> + it, does not affect SCFI correctness.
>> +
>> + TBD_GINSN_GEN_NOT_SCFI. This function assumes GINSN_GEN_SCFI is in effect.
>> + When other ginsn_gen_mode are added, this will need fixing. */
>> +
>> +static bool
>> +aarch64_ginsn_safe_to_skip_p (void)
>> +{
>> + bool skip_p = false;
>> + aarch64_opnd_info *opnd = NULL;
>> + unsigned int dw2_regnum;
>> + unsigned int opnd_reg;
>> + int num_opnds = 0;
>> +
>> + aarch64_inst *base = &inst.base;
>> + const aarch64_opcode *opcode = base->opcode;
>> +
>> + /* ATM, whitelisting operations with no operands does not seem to be
>> + necessary. */
>> + num_opnds = aarch64_num_of_operands (opcode);
>> + if (!num_opnds)
>> + return skip_p;
>
> Things like ERET show that this would be dangerous, so it might be better
> to make the false return explicit (and adjust the comment).
>
I am not sure I understand the "make false return explicit". I have
adjusted the code and comment:
/* ATM, whitelisting operations with no operands does not seem to be
necessary. In fact, whitelisting insns like ERET will be
dangerous for
SCFI. So, return false now and bar any such insns from being
whitelisted
altogether. */
num_opnds = aarch64_num_of_operands (opcode);
if (!num_opnds)
return false;
Is this what you meant ?
>> +
>> + opnd = &base->operands[0];
>> +
>> + switch (opcode->iclass)
>> + {
>> + case ldst_regoff:
>> + /* It is not expected to have reg offset based ld/st ops to be used
>> + for reg save and restore operations. Warn the user though. */
>> + opnd_reg = ginsn_dw2_regnum (opnd, false);
>> + if (aarch64_scfi_callee_saved_p (opnd_reg))
>> + {
>> + skip_p = true;
>> + as_warn ("SCFI: ignored probable save/restore op with reg offset");
>> + }
>> + break;
>> +
>> + case dp_2src:
>> + /* irg insn needs to be explicitly whitelisted. This is because the
>> + dest is Rd_SP, but irg insn affects the tag only. To detect irg
>> + insn, avoid an opcode-based check, however. */
>
> I think we should check specifically for IRG (via subclasses).
> Admittedly none of the others do anything sensible for SP, but other
> instructions could be added in future.
>
True.
I added a new patch that adds subclass flags for the dp_2src insns:
- F_DP_TAG_ONLY for irg (How suitable is the name ?)
- F_SUBCLASS_OTHER for all other insns of iclass dp_2src
Now the above check looks for irg via that subclass flag.
>> + if (opnd->type == AARCH64_OPND_Rd_SP)
>> + {
>> + dw2_regnum = ginsn_dw2_regnum (opnd, true);
>> + if (dw2_regnum == REG_SP)
>> + skip_p = true;
>> + }
>> + break;
>> +
>> + default:
>> + break;
>> + }
>> +
>> + return skip_p;
>> +}
>> +
>> +#define AARCH64_GINSN_UNHANDLED_NONE 0
>> +#define AARCH64_GINSN_UNHANDLED_DEST_REG 1
>> +#define AARCH64_GINSN_UNHANDLED_CFG 2
>> +#define AARCH64_GINSN_UNHANDLED_STACKOP 3
>> +#define AARCH64_GINSN_UNHANDLED_UNEXPECTED 4
>> +
>> +/* Check the input insn for its impact on the correctness of the synthesized
>> + CFI. Returns an error code to the caller. */
>> +
>> +static int
>> +aarch64_ginsn_unhandled (void)
>> +{
>> + int err = AARCH64_GINSN_UNHANDLED_NONE;
>> + aarch64_inst *base = &inst.base;
>> + const aarch64_opcode *opcode = base->opcode;
>> + aarch64_opnd_info *dest = &base->operands[0];
>> + int num_opnds = aarch64_num_of_operands (opcode);
>> + aarch64_opnd_info *addr;
>> + unsigned int dw2_regnum;
>> + unsigned int addr_reg;
>> + aarch64_opnd_info *opnd = NULL;
>> + unsigned int opnd_reg;
>> + bool sp_allowed_p = false;
>> +
>> + /* All change of flow instructions are important for SCFI. */
>> + if (opcode->iclass == condbranch
>> + || opcode->iclass == compbranch
>> + || opcode->iclass == testbranch
>> + || opcode->iclass == branch_imm
>> + || opcode->iclass == branch_reg)
>> + err = AARCH64_GINSN_UNHANDLED_CFG;
>> + /* Also, any memory instructions that may involve an update to the stack
>> + pointer or save/restore of callee-saved registers must not be skipped.
>> + Note that, some iclasses cannot be used to push or pop stack because of
>> + disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
>> + loadlit, ldstnapair_offs. FIXME double-check.
>> + Also, these iclasses do not seem to be amenable to being used for
>> + save/restore ops either. FIXME double-check. */
>> + else if (opcode->iclass == ldstpair_off
>> + || opcode->iclass == ldstpair_indexed
>> + || opcode->iclass == ldst_imm9
>> + || opcode->iclass == ldst_imm10
>> + || opcode->iclass == ldst_pos
>> + /* STR Zn are especially complicated as they do not store in the same byte
>> + order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
>> + whereas STR Zn stores as a stream of bytes (LSB first). FIXME Simply punt
>> + on the big-endian and little-endian SVE PCS case for now. */
>> + || opcode->iclass == sve_misc)
>> + {
>> + opnd = &base->operands[0];
>> + addr = &base->operands[num_opnds - 1];
>> + addr_reg = ginsn_dw2_regnum (addr, true);
>> + opnd_reg = ginsn_dw2_regnum (opnd, false);
>> + /* For all skipped memory operations, check if an update to REG_SP or
>> + REG_FP is involved. */
>> + if ((addr_reg == REG_SP || addr_reg == REG_FP)
>> + && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>> + || aarch64_scfi_callee_saved_p (opnd_reg)))
>> +
>> + err = AARCH64_GINSN_UNHANDLED_STACKOP;
>
> The way I'd imagined this working is that we'd use two-directional data
> flow to record which callee-saved registers are "protected" at which
> instructions. That is, for saves we'd walk the cfg forward from the
> entry point, recording which registers have been saved earlier in the walk
> (and being conservatively correct for cycles). And for restores we'd
> walk the cfg backwards from the exit points, recording which registers
> are restored later in the walk. If a register is both "saved ealier" and
> "restored later" for a given instruction, it wouldn't matter what the
> instruction does with that register.
>
> (For infinite loops we would pretend that all registers are restored later.)
>
> It seems like instead, we'd generate a warning for:
>
> ...
> str d8, [sp, #...]
> ...
> ld1d z8.b, p0/z, [sp, #...]
> ...
> ldr d8, [sp, #...]
> ...
> ret
>
> even though that should be ok (even without interpreting SVE instructions).
>
> On the other hand, any read or write of a callee-saved register is suspicious
> if it isn't saved earlier or isn't restored later.
>
> In other words, it seems like this information should be context-dependent,
> or used in a context-dependent way. Whether a particular register matters
> depends on whether the register might still contain the caller's data.
>
We do something similar for non-memory ops:
- In the aarch64_ginsn_unhandled () codepath, if the destination is of
interest (REG_SP, REG_FP), synthesize a GINSN_TYPE_OTHER with the
appropriate destination register if no ginsn has been generated.
- The SCFI machinery checks if this instruction affects SCFI correctness.
- If it does, only then the insn is issued a complaint for and brought
to attention.
What you suggest is take a similar approach for memory operations too.
I think it makes sense. It needs some work now to accommodate this, but
I think we can re-evaluate after some basic handling for Z registers is
in place ? I plan to work on adding handling for Z registers after this
series is merged. (I have renamed an old testcase involving Z registers
to "scfi-unsupported-2.s" to keep track of the currently unsupported
cases to be worked on in near future, so I dont lose track of this..).
Thanks
Indu
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI
2024-07-11 6:30 ` Indu Bhagat
@ 2024-07-11 13:15 ` Richard Sandiford
2024-07-11 19:07 ` Indu Bhagat
0 siblings, 1 reply; 29+ messages in thread
From: Richard Sandiford @ 2024-07-11 13:15 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> On 7/1/24 12:49, Richard Sandiford wrote:
>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>> +{
>>> + enum aarch64_operand_class opnd_class;
>>> + unsigned int dw2reg_num = 0;
>>> +
>>> + opnd_class = aarch64_get_operand_class (opnd->type);
>>> +
>>> + switch (opnd_class)
>>> + {
>>> + case AARCH64_OPND_CLASS_FP_REG:
>>> + dw2reg_num = opnd->reg.regno + 64;
>>> + break;
>>> + case AARCH64_OPND_CLASS_SVE_REGLIST:
>>> + dw2reg_num = opnd->reglist.first_regno + 64;
>>> + break;
>>> + case AARCH64_OPND_CLASS_MODIFIED_REG:
>>> + case AARCH64_OPND_CLASS_INT_REG:
>>> + case AARCH64_OPND_CLASS_ADDRESS:
>>> + /* Use a dummy register value in case of WZR, else this will be an
>>> + incorrect dependency on REG_SP. */
>>> + if (!sp_allowed_p && opnd->reg.regno == REG_SP)
>>> + dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>>> + else
>>> + /* For GPRs of our interest (callee-saved regs, SP, FP, LR),
>>> + DWARF register number is the same as AArch64 register number. */
>>> + dw2reg_num = opnd->reg.regno;
>>> + break;
>>
>> I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
>> instead. AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
>>
>
> Made the correction for AARCH64_OPND_CLASS_ADDRESS.
>
> But for AARCH64_OPND_CLASS_MODIFIED_REG, the register information is
> still correct in opnd->reg.regno, IIUC. It seems to me that the only
> information available in the opnd->shifter is how the register is
> modified by additional work (shift, multiply etc.); This information is
> not used by SCFI:
> - an add/sub with two source register and destination REG_SP/ REG_FP
> makes REG_SP/ REG_FP untraceable. So ignoring the shift amount etc does
> not hurt SCFI correctness.
> - Cant think of other operations where the shift amount will affect
> SCFI correctness..
>
> So I am not sure of the "AARCH64_OPND_CLASS_MODIFIED_REG should look at
> opnd->shifter." of the review comment.
It's more about type correctness. "shifter" is the data associated with
AARCH64_OPND_CLASS_MODIFIED_REG and "reg" is the data associated with
AARCH64_OPND_CLASS_INT_REG etc. I think it's mostly a coincidence
that the "reg" and "shifter" alternatives of the union put the register
at the same byte offset from the start of the structure.
>>> + default:
>>> + as_bad ("Unexpected value in ginsn_dw2_regnum");
>>> + break;
>>> + }
>>> +
>>> + return dw2reg_num;
>>> +}
>>> +
>>> +/* Generate ginsn for addsub instructions with immediate opnd. */
>>> +
>>> +static ginsnS *
>>> +aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
>>> +{
>>> + ginsnS *ginsn = NULL;
>>> + bool add_p, sub_p;
>>> + offsetT src_imm = 0;
>>> + unsigned int dst_reg, opnd_reg;
>>> + aarch64_opnd_info *dst, *opnd;
>>> + ginsnS *(*ginsn_func) (const symbolS *, bool,
>>> + enum ginsn_src_type, unsigned int, offsetT,
>>> + enum ginsn_src_type, unsigned int, offsetT,
>>> + enum ginsn_dst_type, unsigned int, offsetT);
>>> +
>>> + aarch64_inst *base = &inst.base;
>>> + const aarch64_opcode *opcode = base->opcode;
>>> +
>>> + add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>>> + sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>>> + gas_assert (add_p || sub_p);
>>> + ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>>> +
>>> + gas_assert (aarch64_num_of_operands (opcode) == 3);
>>> + dst = &base->operands[0];
>>> + opnd = &base->operands[1];
>>> +
>>> + dst_reg = ginsn_dw2_regnum (dst, true);
>>> +
>>> + if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>>> + src_imm = inst.reloc.exp.X_add_number;
>>> + /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
>>> + and handle via aarch64_ginsn_unhandled () code path. */
>>> + else if (inst.reloc.type != BFD_RELOC_UNUSED)
>>> + return ginsn;
>>> + /* FIXME - verify the understanding and remove assert. */
>>> + else
>>> + gas_assert (0);
>>> +
>>> + opnd_reg = ginsn_dw2_regnum (opnd, true);
>>> +
>>> + ginsn = ginsn_func (insn_end_sym, true,
>>> + GINSN_SRC_REG, opnd_reg, 0,
>>> + GINSN_SRC_IMM, 0, src_imm,
>>> + GINSN_DST_REG, dst_reg, 0);
>>> + ginsn_set_where (ginsn);
>>> +
>>> + return ginsn;
>>> +}
>>> +
>>> +/* Generate ginsn for addsub instructions with reg opnd. */
>>> +
>>> +static ginsnS *
>>> +aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
>>> +{
>>> + ginsnS *ginsn = NULL;
>>> + bool add_p, sub_p;
>>> + unsigned int dst_reg, src1_reg, src2_reg;
>>> + aarch64_opnd_info *dst, *src1, *src2;
>>> + ginsnS *(*ginsn_func) (const symbolS *, bool,
>>> + enum ginsn_src_type, unsigned int, offsetT,
>>> + enum ginsn_src_type, unsigned int, offsetT,
>>> + enum ginsn_dst_type, unsigned int, offsetT);
>>> +
>>> + aarch64_inst *base = &inst.base;
>>> + const aarch64_opcode *opcode = base->opcode;
>>> +
>>> + add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>>> + sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>>> + gas_assert (add_p || sub_p);
>>> + ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>>> +
>>> + gas_assert (aarch64_num_of_operands (opcode) == 3);
>>> + dst = &base->operands[0];
>>> + src1 = &base->operands[1];
>>> + src2 = &base->operands[2];
>>> +
>>> + dst_reg = ginsn_dw2_regnum (dst, true);
>>> + src1_reg = ginsn_dw2_regnum (src1, true);
>>> + src2_reg = ginsn_dw2_regnum (src2, false);
>>> +
>>> + ginsn = ginsn_func (insn_end_sym, true,
>>> + GINSN_SRC_REG, src1_reg, 0,
>>> + GINSN_SRC_REG, src2_reg, 0,
>>> + GINSN_DST_REG, dst_reg, 0);
>>> + ginsn_set_where (ginsn);
>>
>> It looks like this ignores any shift that is applied to src2_reg.
>>
>
> Yes. An add/sub operation with two source registers makes REG_SP/REG_FP
> untraceable (if dest is REG_SP/REG_FP), so any further information
> carried forward in the ginsn is of little use for SCFI.
>
> For a usecase apart from SCFI, yes, this may amount to loss of vital
> information. I will add a TBD_GINSN_INFO_LOSS comment.
If SCFI doesn't handle add/sub of two registers, then do we still
need this code for correctness? I would have expected SCFI to handle
unrecognised writes to SP in a conservative way, even if there is no
ginsn type defined for the instruction that sets SP.
>>> +
>>> + ginsn = ginsn_new_mov (insn_end_sym, false,
>>> + src_type, src_reg, src_imm,
>>> + GINSN_DST_REG, dst_reg, 0);
>>> + ginsn_set_where (ginsn);
>>> +
>>> + return ginsn;
>>> +}
>>> +
>>> +/* Check if an instruction is whitelisted.
>>> +
>>> + An instruction is a candidate for whitelisting if not generating ginsn for
>>> + it, does not affect SCFI correctness.
>>> +
>>> + TBD_GINSN_GEN_NOT_SCFI. This function assumes GINSN_GEN_SCFI is in effect.
>>> + When other ginsn_gen_mode are added, this will need fixing. */
>>> +
>>> +static bool
>>> +aarch64_ginsn_safe_to_skip_p (void)
>>> +{
>>> + bool skip_p = false;
>>> + aarch64_opnd_info *opnd = NULL;
>>> + unsigned int dw2_regnum;
>>> + unsigned int opnd_reg;
>>> + int num_opnds = 0;
>>> +
>>> + aarch64_inst *base = &inst.base;
>>> + const aarch64_opcode *opcode = base->opcode;
>>> +
>>> + /* ATM, whitelisting operations with no operands does not seem to be
>>> + necessary. */
>>> + num_opnds = aarch64_num_of_operands (opcode);
>>> + if (!num_opnds)
>>> + return skip_p;
>>
>> Things like ERET show that this would be dangerous, so it might be better
>> to make the false return explicit (and adjust the comment).
>>
>
> I am not sure I understand the "make false return explicit". I have
> adjusted the code and comment:
>
> /* ATM, whitelisting operations with no operands does not seem to be
> necessary. In fact, whitelisting insns like ERET will be
> dangerous for
> SCFI. So, return false now and bar any such insns from being
> whitelisted
> altogether. */
> num_opnds = aarch64_num_of_operands (opcode);
> if (!num_opnds)
> return false;
>
> Is this what you meant ?
Yes, thanks.
>>> + if (opnd->type == AARCH64_OPND_Rd_SP)
>>> + {
>>> + dw2_regnum = ginsn_dw2_regnum (opnd, true);
>>> + if (dw2_regnum == REG_SP)
>>> + skip_p = true;
>>> + }
>>> + break;
>>> +
>>> + default:
>>> + break;
>>> + }
>>> +
>>> + return skip_p;
>>> +}
>>> +
>>> +#define AARCH64_GINSN_UNHANDLED_NONE 0
>>> +#define AARCH64_GINSN_UNHANDLED_DEST_REG 1
>>> +#define AARCH64_GINSN_UNHANDLED_CFG 2
>>> +#define AARCH64_GINSN_UNHANDLED_STACKOP 3
>>> +#define AARCH64_GINSN_UNHANDLED_UNEXPECTED 4
>>> +
>>> +/* Check the input insn for its impact on the correctness of the synthesized
>>> + CFI. Returns an error code to the caller. */
>>> +
>>> +static int
>>> +aarch64_ginsn_unhandled (void)
>>> +{
>>> + int err = AARCH64_GINSN_UNHANDLED_NONE;
>>> + aarch64_inst *base = &inst.base;
>>> + const aarch64_opcode *opcode = base->opcode;
>>> + aarch64_opnd_info *dest = &base->operands[0];
>>> + int num_opnds = aarch64_num_of_operands (opcode);
>>> + aarch64_opnd_info *addr;
>>> + unsigned int dw2_regnum;
>>> + unsigned int addr_reg;
>>> + aarch64_opnd_info *opnd = NULL;
>>> + unsigned int opnd_reg;
>>> + bool sp_allowed_p = false;
>>> +
>>> + /* All change of flow instructions are important for SCFI. */
>>> + if (opcode->iclass == condbranch
>>> + || opcode->iclass == compbranch
>>> + || opcode->iclass == testbranch
>>> + || opcode->iclass == branch_imm
>>> + || opcode->iclass == branch_reg)
>>> + err = AARCH64_GINSN_UNHANDLED_CFG;
>>> + /* Also, any memory instructions that may involve an update to the stack
>>> + pointer or save/restore of callee-saved registers must not be skipped.
>>> + Note that, some iclasses cannot be used to push or pop stack because of
>>> + disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
>>> + loadlit, ldstnapair_offs. FIXME double-check.
>>> + Also, these iclasses do not seem to be amenable to being used for
>>> + save/restore ops either. FIXME double-check. */
>>> + else if (opcode->iclass == ldstpair_off
>>> + || opcode->iclass == ldstpair_indexed
>>> + || opcode->iclass == ldst_imm9
>>> + || opcode->iclass == ldst_imm10
>>> + || opcode->iclass == ldst_pos
>>> + /* STR Zn are especially complicated as they do not store in the same byte
>>> + order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
>>> + whereas STR Zn stores as a stream of bytes (LSB first). FIXME Simply punt
>>> + on the big-endian and little-endian SVE PCS case for now. */
>>> + || opcode->iclass == sve_misc)
>>> + {
>>> + opnd = &base->operands[0];
>>> + addr = &base->operands[num_opnds - 1];
>>> + addr_reg = ginsn_dw2_regnum (addr, true);
>>> + opnd_reg = ginsn_dw2_regnum (opnd, false);
>>> + /* For all skipped memory operations, check if an update to REG_SP or
>>> + REG_FP is involved. */
>>> + if ((addr_reg == REG_SP || addr_reg == REG_FP)
>>> + && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>>> + || aarch64_scfi_callee_saved_p (opnd_reg)))
>>> +
>>> + err = AARCH64_GINSN_UNHANDLED_STACKOP;
>>
>> The way I'd imagined this working is that we'd use two-directional data
>> flow to record which callee-saved registers are "protected" at which
>> instructions. That is, for saves we'd walk the cfg forward from the
>> entry point, recording which registers have been saved earlier in the walk
>> (and being conservatively correct for cycles). And for restores we'd
>> walk the cfg backwards from the exit points, recording which registers
>> are restored later in the walk. If a register is both "saved ealier" and
>> "restored later" for a given instruction, it wouldn't matter what the
>> instruction does with that register.
>>
>> (For infinite loops we would pretend that all registers are restored later.)
>>
>> It seems like instead, we'd generate a warning for:
>>
>> ...
>> str d8, [sp, #...]
>> ...
>> ld1d z8.b, p0/z, [sp, #...]
>> ...
>> ldr d8, [sp, #...]
>> ...
>> ret
>>
>> even though that should be ok (even without interpreting SVE instructions).
>>
>> On the other hand, any read or write of a callee-saved register is suspicious
>> if it isn't saved earlier or isn't restored later.
>>
>> In other words, it seems like this information should be context-dependent,
>> or used in a context-dependent way. Whether a particular register matters
>> depends on whether the register might still contain the caller's data.
>>
>
> We do something similar for non-memory ops:
> - In the aarch64_ginsn_unhandled () codepath, if the destination is of
> interest (REG_SP, REG_FP), synthesize a GINSN_TYPE_OTHER with the
> appropriate destination register if no ginsn has been generated.
> - The SCFI machinery checks if this instruction affects SCFI correctness.
> - If it does, only then the insn is issued a complaint for and brought
> to attention.
>
> What you suggest is take a similar approach for memory operations too.
> I think it makes sense. It needs some work now to accommodate this, but
> I think we can re-evaluate after some basic handling for Z registers is
> in place ? I plan to work on adding handling for Z registers after this
> series is merged. (I have renamed an old testcase involving Z registers
> to "scfi-unsupported-2.s" to keep track of the currently unsupported
> cases to be worked on in near future, so I dont lose track of this..).
Yeah, leaving it till later sounds ok. But I don't think this should
depend on recognising Z loads and stores. It should just depend on
processing Z registers in the operand lists, and recognising that the
low 64 bits of Z8-Z15 are the same as D8-D15.
In other words, I imagined the set-up would be:
(1) the operand list should tell us whether a register is referenced
(2) recognising 8-byte+ loads and stores, plus support arithmetic,
lets us recognise instructions that would function as a save or
restore (and at what offset)
(3) dataflow analysis based on (2) tells us, for a given instruction,
which registers might have caller data
(4) A reference to possible caller data triggers a warning
(references detected by (1), caller data by (3))
Is that roughly how it works?
Thanks,
Richard
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI
2024-07-11 13:15 ` Richard Sandiford
@ 2024-07-11 19:07 ` Indu Bhagat
2024-07-11 20:10 ` Richard Sandiford
0 siblings, 1 reply; 29+ messages in thread
From: Indu Bhagat @ 2024-07-11 19:07 UTC (permalink / raw)
To: binutils, Richard.Earnshaw, richard.sandiford
On 7/11/24 06:15, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> On 7/1/24 12:49, Richard Sandiford wrote:
>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>> +{
>>>> + enum aarch64_operand_class opnd_class;
>>>> + unsigned int dw2reg_num = 0;
>>>> +
>>>> + opnd_class = aarch64_get_operand_class (opnd->type);
>>>> +
>>>> + switch (opnd_class)
>>>> + {
>>>> + case AARCH64_OPND_CLASS_FP_REG:
>>>> + dw2reg_num = opnd->reg.regno + 64;
>>>> + break;
>>>> + case AARCH64_OPND_CLASS_SVE_REGLIST:
>>>> + dw2reg_num = opnd->reglist.first_regno + 64;
>>>> + break;
>>>> + case AARCH64_OPND_CLASS_MODIFIED_REG:
>>>> + case AARCH64_OPND_CLASS_INT_REG:
>>>> + case AARCH64_OPND_CLASS_ADDRESS:
>>>> + /* Use a dummy register value in case of WZR, else this will be an
>>>> + incorrect dependency on REG_SP. */
>>>> + if (!sp_allowed_p && opnd->reg.regno == REG_SP)
>>>> + dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>>>> + else
>>>> + /* For GPRs of our interest (callee-saved regs, SP, FP, LR),
>>>> + DWARF register number is the same as AArch64 register number. */
>>>> + dw2reg_num = opnd->reg.regno;
>>>> + break;
>>>
>>> I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
>>> instead. AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
>>>
>>
>> Made the correction for AARCH64_OPND_CLASS_ADDRESS.
>>
>> But for AARCH64_OPND_CLASS_MODIFIED_REG, the register information is
>> still correct in opnd->reg.regno, IIUC. It seems to me that the only
>> information available in the opnd->shifter is how the register is
>> modified by additional work (shift, multiply etc.); This information is
>> not used by SCFI:
>> - an add/sub with two source register and destination REG_SP/ REG_FP
>> makes REG_SP/ REG_FP untraceable. So ignoring the shift amount etc does
>> not hurt SCFI correctness.
>> - Cant think of other operations where the shift amount will affect
>> SCFI correctness..
>>
>> So I am not sure of the "AARCH64_OPND_CLASS_MODIFIED_REG should look at
>> opnd->shifter." of the review comment.
>
> It's more about type correctness. "shifter" is the data associated with
> AARCH64_OPND_CLASS_MODIFIED_REG and "reg" is the data associated with
> AARCH64_OPND_CLASS_INT_REG etc. I think it's mostly a coincidence
> that the "reg" and "shifter" alternatives of the union put the register
> at the same byte offset from the start of the structure.
>
The shifter struct is out of the union in struct aarch64_opnd_info.
>>>> + default:
>>>> + as_bad ("Unexpected value in ginsn_dw2_regnum");
>>>> + break;
>>>> + }
>>>> +
>>>> + return dw2reg_num;
>>>> +}
>>>> +
>>>> +/* Generate ginsn for addsub instructions with immediate opnd. */
>>>> +
>>>> +static ginsnS *
>>>> +aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
>>>> +{
>>>> + ginsnS *ginsn = NULL;
>>>> + bool add_p, sub_p;
>>>> + offsetT src_imm = 0;
>>>> + unsigned int dst_reg, opnd_reg;
>>>> + aarch64_opnd_info *dst, *opnd;
>>>> + ginsnS *(*ginsn_func) (const symbolS *, bool,
>>>> + enum ginsn_src_type, unsigned int, offsetT,
>>>> + enum ginsn_src_type, unsigned int, offsetT,
>>>> + enum ginsn_dst_type, unsigned int, offsetT);
>>>> +
>>>> + aarch64_inst *base = &inst.base;
>>>> + const aarch64_opcode *opcode = base->opcode;
>>>> +
>>>> + add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>>>> + sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>>>> + gas_assert (add_p || sub_p);
>>>> + ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>>>> +
>>>> + gas_assert (aarch64_num_of_operands (opcode) == 3);
>>>> + dst = &base->operands[0];
>>>> + opnd = &base->operands[1];
>>>> +
>>>> + dst_reg = ginsn_dw2_regnum (dst, true);
>>>> +
>>>> + if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>>>> + src_imm = inst.reloc.exp.X_add_number;
>>>> + /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
>>>> + and handle via aarch64_ginsn_unhandled () code path. */
>>>> + else if (inst.reloc.type != BFD_RELOC_UNUSED)
>>>> + return ginsn;
>>>> + /* FIXME - verify the understanding and remove assert. */
>>>> + else
>>>> + gas_assert (0);
>>>> +
>>>> + opnd_reg = ginsn_dw2_regnum (opnd, true);
>>>> +
>>>> + ginsn = ginsn_func (insn_end_sym, true,
>>>> + GINSN_SRC_REG, opnd_reg, 0,
>>>> + GINSN_SRC_IMM, 0, src_imm,
>>>> + GINSN_DST_REG, dst_reg, 0);
>>>> + ginsn_set_where (ginsn);
>>>> +
>>>> + return ginsn;
>>>> +}
>>>> +
>>>> +/* Generate ginsn for addsub instructions with reg opnd. */
>>>> +
>>>> +static ginsnS *
>>>> +aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
>>>> +{
>>>> + ginsnS *ginsn = NULL;
>>>> + bool add_p, sub_p;
>>>> + unsigned int dst_reg, src1_reg, src2_reg;
>>>> + aarch64_opnd_info *dst, *src1, *src2;
>>>> + ginsnS *(*ginsn_func) (const symbolS *, bool,
>>>> + enum ginsn_src_type, unsigned int, offsetT,
>>>> + enum ginsn_src_type, unsigned int, offsetT,
>>>> + enum ginsn_dst_type, unsigned int, offsetT);
>>>> +
>>>> + aarch64_inst *base = &inst.base;
>>>> + const aarch64_opcode *opcode = base->opcode;
>>>> +
>>>> + add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>>>> + sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>>>> + gas_assert (add_p || sub_p);
>>>> + ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>>>> +
>>>> + gas_assert (aarch64_num_of_operands (opcode) == 3);
>>>> + dst = &base->operands[0];
>>>> + src1 = &base->operands[1];
>>>> + src2 = &base->operands[2];
>>>> +
>>>> + dst_reg = ginsn_dw2_regnum (dst, true);
>>>> + src1_reg = ginsn_dw2_regnum (src1, true);
>>>> + src2_reg = ginsn_dw2_regnum (src2, false);
>>>> +
>>>> + ginsn = ginsn_func (insn_end_sym, true,
>>>> + GINSN_SRC_REG, src1_reg, 0,
>>>> + GINSN_SRC_REG, src2_reg, 0,
>>>> + GINSN_DST_REG, dst_reg, 0);
>>>> + ginsn_set_where (ginsn);
>>>
>>> It looks like this ignores any shift that is applied to src2_reg.
>>>
>>
>> Yes. An add/sub operation with two source registers makes REG_SP/REG_FP
>> untraceable (if dest is REG_SP/REG_FP), so any further information
>> carried forward in the ginsn is of little use for SCFI.
>>
>> For a usecase apart from SCFI, yes, this may amount to loss of vital
>> information. I will add a TBD_GINSN_INFO_LOSS comment.
>
> If SCFI doesn't handle add/sub of two registers, then do we still
> need this code for correctness? I would have expected SCFI to handle
> unrecognised writes to SP in a conservative way, even if there is no
> ginsn type defined for the instruction that sets SP.
>
Correct, we dont need the two register ADD/SUB for SCFI correctness. A
placeholder insn like GINSN_TYPE_OTHER emitted via the
aarch64_ginsn_unhandled () code path should also be sufficient for SCFI.
>>>> + if (opnd->type == AARCH64_OPND_Rd_SP)
>>>> + {
>>>> + dw2_regnum = ginsn_dw2_regnum (opnd, true);
>>>> + if (dw2_regnum == REG_SP)
>>>> + skip_p = true;
>>>> + }
>>>> + break;
>>>> +
>>>> + default:
>>>> + break;
>>>> + }
>>>> +
>>>> + return skip_p;
>>>> +}
>>>> +
>>>> +#define AARCH64_GINSN_UNHANDLED_NONE 0
>>>> +#define AARCH64_GINSN_UNHANDLED_DEST_REG 1
>>>> +#define AARCH64_GINSN_UNHANDLED_CFG 2
>>>> +#define AARCH64_GINSN_UNHANDLED_STACKOP 3
>>>> +#define AARCH64_GINSN_UNHANDLED_UNEXPECTED 4
>>>> +
>>>> +/* Check the input insn for its impact on the correctness of the synthesized
>>>> + CFI. Returns an error code to the caller. */
>>>> +
>>>> +static int
>>>> +aarch64_ginsn_unhandled (void)
>>>> +{
>>>> + int err = AARCH64_GINSN_UNHANDLED_NONE;
>>>> + aarch64_inst *base = &inst.base;
>>>> + const aarch64_opcode *opcode = base->opcode;
>>>> + aarch64_opnd_info *dest = &base->operands[0];
>>>> + int num_opnds = aarch64_num_of_operands (opcode);
>>>> + aarch64_opnd_info *addr;
>>>> + unsigned int dw2_regnum;
>>>> + unsigned int addr_reg;
>>>> + aarch64_opnd_info *opnd = NULL;
>>>> + unsigned int opnd_reg;
>>>> + bool sp_allowed_p = false;
>>>> +
>>>> + /* All change of flow instructions are important for SCFI. */
>>>> + if (opcode->iclass == condbranch
>>>> + || opcode->iclass == compbranch
>>>> + || opcode->iclass == testbranch
>>>> + || opcode->iclass == branch_imm
>>>> + || opcode->iclass == branch_reg)
>>>> + err = AARCH64_GINSN_UNHANDLED_CFG;
>>>> + /* Also, any memory instructions that may involve an update to the stack
>>>> + pointer or save/restore of callee-saved registers must not be skipped.
>>>> + Note that, some iclasses cannot be used to push or pop stack because of
>>>> + disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
>>>> + loadlit, ldstnapair_offs. FIXME double-check.
>>>> + Also, these iclasses do not seem to be amenable to being used for
>>>> + save/restore ops either. FIXME double-check. */
>>>> + else if (opcode->iclass == ldstpair_off
>>>> + || opcode->iclass == ldstpair_indexed
>>>> + || opcode->iclass == ldst_imm9
>>>> + || opcode->iclass == ldst_imm10
>>>> + || opcode->iclass == ldst_pos
>>>> + /* STR Zn are especially complicated as they do not store in the same byte
>>>> + order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
>>>> + whereas STR Zn stores as a stream of bytes (LSB first). FIXME Simply punt
>>>> + on the big-endian and little-endian SVE PCS case for now. */
>>>> + || opcode->iclass == sve_misc)
>>>> + {
>>>> + opnd = &base->operands[0];
>>>> + addr = &base->operands[num_opnds - 1];
>>>> + addr_reg = ginsn_dw2_regnum (addr, true);
>>>> + opnd_reg = ginsn_dw2_regnum (opnd, false);
>>>> + /* For all skipped memory operations, check if an update to REG_SP or
>>>> + REG_FP is involved. */
>>>> + if ((addr_reg == REG_SP || addr_reg == REG_FP)
>>>> + && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>>>> + || aarch64_scfi_callee_saved_p (opnd_reg)))
>>>> +
>>>> + err = AARCH64_GINSN_UNHANDLED_STACKOP;
>>>
>>> The way I'd imagined this working is that we'd use two-directional data
>>> flow to record which callee-saved registers are "protected" at which
>>> instructions. That is, for saves we'd walk the cfg forward from the
>>> entry point, recording which registers have been saved earlier in the walk
>>> (and being conservatively correct for cycles). And for restores we'd
>>> walk the cfg backwards from the exit points, recording which registers
>>> are restored later in the walk. If a register is both "saved ealier" and
>>> "restored later" for a given instruction, it wouldn't matter what the
>>> instruction does with that register.
>>>
>>> (For infinite loops we would pretend that all registers are restored later.)
>>>
>>> It seems like instead, we'd generate a warning for:
>>>
>>> ...
>>> str d8, [sp, #...]
>>> ...
>>> ld1d z8.b, p0/z, [sp, #...]
>>> ...
>>> ldr d8, [sp, #...]
>>> ...
>>> ret
>>>
>>> even though that should be ok (even without interpreting SVE instructions).
>>>
>>> On the other hand, any read or write of a callee-saved register is suspicious
>>> if it isn't saved earlier or isn't restored later.
>>>
>>> In other words, it seems like this information should be context-dependent,
>>> or used in a context-dependent way. Whether a particular register matters
>>> depends on whether the register might still contain the caller's data.
>>>
>>
>> We do something similar for non-memory ops:
>> - In the aarch64_ginsn_unhandled () codepath, if the destination is of
>> interest (REG_SP, REG_FP), synthesize a GINSN_TYPE_OTHER with the
>> appropriate destination register if no ginsn has been generated.
>> - The SCFI machinery checks if this instruction affects SCFI correctness.
>> - If it does, only then the insn is issued a complaint for and brought
>> to attention.
>>
>> What you suggest is take a similar approach for memory operations too.
>> I think it makes sense. It needs some work now to accommodate this, but
>> I think we can re-evaluate after some basic handling for Z registers is
>> in place ? I plan to work on adding handling for Z registers after this
>> series is merged. (I have renamed an old testcase involving Z registers
>> to "scfi-unsupported-2.s" to keep track of the currently unsupported
>> cases to be worked on in near future, so I dont lose track of this..).
>
> Yeah, leaving it till later sounds ok. But I don't think this should
> depend on recognising Z loads and stores. It should just depend on
> processing Z registers in the operand lists, and recognising that the
> low 64 bits of Z8-Z15 are the same as D8-D15.
>
Yes it is orthogonal recognizing Z loads and stores. I just meant that
once we recognize Z loads and stores, the utility of such a workflow
(i.e., do not error out on unrecognised load/stores conservatively as
they may not be necessary for SCFI correctness at all) is reduced as
less code blocks will trigger that.
> In other words, I imagined the set-up would be:
>
> (1) the operand list should tell us whether a register is referenced
>
> (2) recognising 8-byte+ loads and stores, plus support arithmetic,
> lets us recognise instructions that would function as a save or
> restore (and at what offset)
>
> (3) dataflow analysis based on (2) tells us, for a given instruction,
> which registers might have caller data
>
> (4) A reference to possible caller data triggers a warning
> (references detected by (1), caller data by (3))
>
> Is that roughly how it works?
>
Roughly yes. I need to hook a few more things in (3) for the additional
warning.
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI
2024-07-11 19:07 ` Indu Bhagat
@ 2024-07-11 20:10 ` Richard Sandiford
0 siblings, 0 replies; 29+ messages in thread
From: Richard Sandiford @ 2024-07-11 20:10 UTC (permalink / raw)
To: Indu Bhagat; +Cc: binutils, Richard.Earnshaw
Indu Bhagat <indu.bhagat@oracle.com> writes:
> On 7/11/24 06:15, Richard Sandiford wrote:
>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>> On 7/1/24 12:49, Richard Sandiford wrote:
>>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>>> +{
>>>>> + enum aarch64_operand_class opnd_class;
>>>>> + unsigned int dw2reg_num = 0;
>>>>> +
>>>>> + opnd_class = aarch64_get_operand_class (opnd->type);
>>>>> +
>>>>> + switch (opnd_class)
>>>>> + {
>>>>> + case AARCH64_OPND_CLASS_FP_REG:
>>>>> + dw2reg_num = opnd->reg.regno + 64;
>>>>> + break;
>>>>> + case AARCH64_OPND_CLASS_SVE_REGLIST:
>>>>> + dw2reg_num = opnd->reglist.first_regno + 64;
>>>>> + break;
>>>>> + case AARCH64_OPND_CLASS_MODIFIED_REG:
>>>>> + case AARCH64_OPND_CLASS_INT_REG:
>>>>> + case AARCH64_OPND_CLASS_ADDRESS:
>>>>> + /* Use a dummy register value in case of WZR, else this will be an
>>>>> + incorrect dependency on REG_SP. */
>>>>> + if (!sp_allowed_p && opnd->reg.regno == REG_SP)
>>>>> + dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>>>>> + else
>>>>> + /* For GPRs of our interest (callee-saved regs, SP, FP, LR),
>>>>> + DWARF register number is the same as AArch64 register number. */
>>>>> + dw2reg_num = opnd->reg.regno;
>>>>> + break;
>>>>
>>>> I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
>>>> instead. AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
>>>>
>>>
>>> Made the correction for AARCH64_OPND_CLASS_ADDRESS.
>>>
>>> But for AARCH64_OPND_CLASS_MODIFIED_REG, the register information is
>>> still correct in opnd->reg.regno, IIUC. It seems to me that the only
>>> information available in the opnd->shifter is how the register is
>>> modified by additional work (shift, multiply etc.); This information is
>>> not used by SCFI:
>>> - an add/sub with two source register and destination REG_SP/ REG_FP
>>> makes REG_SP/ REG_FP untraceable. So ignoring the shift amount etc does
>>> not hurt SCFI correctness.
>>> - Cant think of other operations where the shift amount will affect
>>> SCFI correctness..
>>>
>>> So I am not sure of the "AARCH64_OPND_CLASS_MODIFIED_REG should look at
>>> opnd->shifter." of the review comment.
>>
>> It's more about type correctness. "shifter" is the data associated with
>> AARCH64_OPND_CLASS_MODIFIED_REG and "reg" is the data associated with
>> AARCH64_OPND_CLASS_INT_REG etc. I think it's mostly a coincidence
>> that the "reg" and "shifter" alternatives of the union put the register
>> at the same byte offset from the start of the structure.
>>
>
> The shifter struct is out of the union in struct aarch64_opnd_info.
Oops, yes, I shouldn't have relied on memory. Sorry for the noise.
Richard
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH,V4 8/8] gas: aarch64: testsuite: add new tests for SCFI
2024-07-01 2:53 [PATCH,V4 0/8] Add SCFI support for aarch64 Indu Bhagat
` (6 preceding siblings ...)
2024-07-01 2:54 ` [PATCH,V4 7/8] gas: aarch64: add experimental support for SCFI Indu Bhagat
@ 2024-07-01 2:54 ` Indu Bhagat
7 siblings, 0 replies; 29+ messages in thread
From: Indu Bhagat @ 2024-07-01 2:54 UTC (permalink / raw)
To: binutils; +Cc: richard.sandiford, Richard.Earnshaw, Indu Bhagat
[Changes in V4]
- New testcases for FP callee-saved registers.
scfi-callee-saved-fp-1.s uses D registers, scfi-callee-saved-fp-2.s
uses Q registers and is run with -mbig-endian.
- Added new ops (movk, prfm) to ginsn-misc-1. These ops are not
relevant for SCFI correctness; this testcase merely
ensures graceful handling of ginsn creation for such insns.
- Fixed ginsn-ldst-1 as it included some load / store ops with D
registers, which we now handle. Also added some insns using W and S
registers.
- Added a new test scfi-diag-3 where SCFI machinery reports the
following error when it sees an SVE memory op with callee-saved
register:
"Error: SCFI: unhandled op 0xe5e0e000 may cause incorrect CFI"
[End of changes in V4]
[No changes in V3]
[Changes in V2]
- new testcase scfi-cfg-4.s for the changes in cmp_scfi_state.
- new testcase ginsn-arith-1.s for ginsn creation for various add sub insns.
- removed redundant insns from ginsn-misc-1.s, some of those insns are
now in ginsn-arith-1.s.
- added more ld st opts in ginsn-ldst-1.s testcase.
[End of changes in V2]
Similar to the x86_64 testcases, some .s files contain the corresponding
CFI directives. This helps in validating the synthesized CFI by running
those tests with and without the --scfi=experimental command line
option.
GAS issues some diagnostics, enabled by default, with
--scfi=experimental. The diagnostics have been added with an intent to
help user correct inadvertent errors in their hand-written asm. An
error is issued when GAS finds that input asm is not amenable to
accurate CFI synthesis. The existing scfi-diag-*.s tests in the
gas/testsuite/gas/scfi/x86_64 directory test some SCFI diagnostics
already:
- (#1) "Warning: SCFI: Asymetrical register restore"
- (#2) "Error: SCFI: usage of REG_FP as scratch not supported"
- (#3) "Error: SCFI: unsupported stack manipulation pattern"
- (#4) "Error: untraceable control flow for func 'XXX'"
In the newly added aarch64 testsuite, further tests for additional
diagnostics have been added:
- scfi-diag-1.s in this patch highlights an aarch64-specific diagnostic:
(#5) "Warning: SCFI: ignored probable save/restore op with reg offset"
Additionally, some testcases are added to showcase the (currently)
unsupported patterns, e.g., scfi-unsupported-1.s
mov x16, 4384
sub sp, sp, x16
gas/testsuite/:
* gas/scfi/README: Update comment to include aarch64.
* gas/scfi/aarch64/scfi-aarch64.exp: New file.
* gas/scfi/aarch64/ginsn-arith-1.l: New test.
* gas/scfi/aarch64/ginsn-arith-1.s: New test.
* gas/scfi/aarch64/ginsn-cofi-1.l: New test.
* gas/scfi/aarch64/ginsn-cofi-1.s: New test.
* gas/scfi/aarch64/ginsn-ldst-1.l: New test.
* gas/scfi/aarch64/ginsn-ldst-1.s: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-1.d: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-1.l: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-1.s: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-2.d: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-2.l: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-2.s: New test.
* gas/scfi/aarch64/scfi-cb-1.d: New test.
* gas/scfi/aarch64/scfi-cb-1.l: New test.
* gas/scfi/aarch64/scfi-cb-1.s: New test.
* gas/scfi/aarch64/scfi-cfg-1.d: New test.
* gas/scfi/aarch64/scfi-cfg-1.l: New test.
* gas/scfi/aarch64/scfi-cfg-1.s: New test.
* gas/scfi/aarch64/scfi-cfg-2.d: New test.
* gas/scfi/aarch64/scfi-cfg-2.l: New test.
* gas/scfi/aarch64/scfi-cfg-2.s: New test.
* gas/scfi/aarch64/scfi-cfg-3.d: New test.
* gas/scfi/aarch64/scfi-cfg-3.l: New test.
* gas/scfi/aarch64/scfi-cfg-3.s: New test.
* gas/scfi/aarch64/scfi-cfg-4.l: New test.
* gas/scfi/aarch64/scfi-cfg-4.s: New test.
* gas/scfi/aarch64/scfi-cond-br-1.d: New test.
* gas/scfi/aarch64/scfi-cond-br-1.l: New test.
* gas/scfi/aarch64/scfi-cond-br-1.s: New test.
* gas/scfi/aarch64/scfi-diag-1.l: New test.
* gas/scfi/aarch64/scfi-diag-1.s: New test.
* gas/scfi/aarch64/scfi-diag-2.l: New test.
* gas/scfi/aarch64/scfi-diag-2.s: New test.
* gas/scfi/aarch64/scfi-diag-3.l: New test.
* gas/scfi/aarch64/scfi-diag-3.s: New test.
* gas/scfi/aarch64/scfi-ldrp-1.d: New test.
* gas/scfi/aarch64/scfi-ldrp-1.l: New test.
* gas/scfi/aarch64/scfi-ldrp-1.s: New test.
* gas/scfi/aarch64/scfi-ldrp-2.d: New test.
* gas/scfi/aarch64/scfi-ldrp-2.l: New test.
* gas/scfi/aarch64/scfi-ldrp-2.s: New test.
* gas/scfi/aarch64/scfi-strp-1.d: New test.
* gas/scfi/aarch64/scfi-strp-1.l: New test.
* gas/scfi/aarch64/scfi-strp-1.s: New test.
* gas/scfi/aarch64/scfi-strp-2.d: New test.
* gas/scfi/aarch64/scfi-strp-2.l: New test.
* gas/scfi/aarch64/scfi-strp-2.s: New test.
* gas/scfi/aarch64/scfi-unsupported-1.l: New test.
* gas/scfi/aarch64/scfi-unsupported-1.s: New test.
---
gas/testsuite/gas/scfi/README | 2 +-
.../gas/scfi/aarch64/ginsn-arith-1.l | 35 +++++++++
.../gas/scfi/aarch64/ginsn-arith-1.s | 16 ++++
gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.l | 30 +++++++
gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.s | 16 ++++
gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.l | 78 +++++++++++++++++++
gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.s | 34 ++++++++
gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.l | 27 +++++++
gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.s | 13 ++++
.../gas/scfi/aarch64/scfi-aarch64.exp | 70 +++++++++++++++++
.../gas/scfi/aarch64/scfi-callee-saved-fp-1.d | 57 ++++++++++++++
.../gas/scfi/aarch64/scfi-callee-saved-fp-1.l | 2 +
.../gas/scfi/aarch64/scfi-callee-saved-fp-1.s | 50 ++++++++++++
.../gas/scfi/aarch64/scfi-callee-saved-fp-2.d | 57 ++++++++++++++
.../gas/scfi/aarch64/scfi-callee-saved-fp-2.l | 2 +
.../gas/scfi/aarch64/scfi-callee-saved-fp-2.s | 50 ++++++++++++
gas/testsuite/gas/scfi/aarch64/scfi-cb-1.d | 20 +++++
gas/testsuite/gas/scfi/aarch64/scfi-cb-1.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-cb-1.s | 14 ++++
gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.d | 31 ++++++++
gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.s | 46 +++++++++++
gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.d | 40 ++++++++++
gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.s | 42 ++++++++++
gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.d | 32 ++++++++
gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.s | 34 ++++++++
gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.d | 41 ++++++++++
gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.s | 41 ++++++++++
.../gas/scfi/aarch64/scfi-cond-br-1.d | 20 +++++
.../gas/scfi/aarch64/scfi-cond-br-1.l | 2 +
.../gas/scfi/aarch64/scfi-cond-br-1.s | 13 ++++
gas/testsuite/gas/scfi/aarch64/scfi-diag-1.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-diag-1.s | 6 ++
gas/testsuite/gas/scfi/aarch64/scfi-diag-2.l | 3 +
gas/testsuite/gas/scfi/aarch64/scfi-diag-2.s | 25 ++++++
gas/testsuite/gas/scfi/aarch64/scfi-diag-3.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-diag-3.s | 8 ++
gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.d | 59 ++++++++++++++
gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.s | 52 +++++++++++++
gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.d | 33 ++++++++
gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.s | 26 +++++++
gas/testsuite/gas/scfi/aarch64/scfi-strp-1.d | 39 ++++++++++
gas/testsuite/gas/scfi/aarch64/scfi-strp-1.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-strp-1.s | 37 +++++++++
gas/testsuite/gas/scfi/aarch64/scfi-strp-2.d | 35 +++++++++
gas/testsuite/gas/scfi/aarch64/scfi-strp-2.l | 2 +
gas/testsuite/gas/scfi/aarch64/scfi-strp-2.s | 30 +++++++
.../gas/scfi/aarch64/scfi-unsupported-1.l | 4 +
.../gas/scfi/aarch64/scfi-unsupported-1.s | 31 ++++++++
54 files changed, 1324 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/scfi/aarch64/ginsn-arith-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/ginsn-arith-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-aarch64.exp
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cb-1.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cb-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cb-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-diag-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-diag-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-diag-2.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-diag-2.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-diag-3.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-diag-3.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-strp-1.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-strp-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-strp-1.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-strp-2.d
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-strp-2.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-strp-2.s
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-unsupported-1.l
create mode 100644 gas/testsuite/gas/scfi/aarch64/scfi-unsupported-1.s
diff --git a/gas/testsuite/gas/scfi/README b/gas/testsuite/gas/scfi/README
index 91191634769..44b09177e84 100644
--- a/gas/testsuite/gas/scfi/README
+++ b/gas/testsuite/gas/scfi/README
@@ -1,6 +1,6 @@
Notes on the SCFI testsuite in GAS:
-* At this time, SCFI machinery is only supported for x86_64.
+* At this time, SCFI machinery is only supported for x86_64 and aarch64.
* When adding more tests, please keep CFI annotations updated in the .s files.
Ideally the test should be run with and without --scfi (as is done currently
diff --git a/gas/testsuite/gas/scfi/aarch64/ginsn-arith-1.l b/gas/testsuite/gas/scfi/aarch64/ginsn-arith-1.l
new file mode 100644
index 00000000000..8c3eef057ad
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/ginsn-arith-1.l
@@ -0,0 +1,35 @@
+.*: Assembler messages:
+.*:13: Error: SCFI: unsupported stack manipulation pattern
+.*:16: Error: SCFI: forward pass failed for func 'foo'
+
+AARCH64 GAS .*
+
+
+ 1 # Testcase for a variety of arith instructions
+ 2 .text
+ 3 .align 2
+ 4 .global foo
+ 5 .type foo, %function
+ 5 ginsn: SYM FUNC_BEGIN
+ 6 foo:
+ 6 ginsn: SYM foo
+ 7 \?\?\?\? FF830091 add sp, sp, 32
+ 7 ginsn: ADD %r31, 32, %r31
+ 8 \?\?\?\? FD5B21B1 adds x29, sp, 2134
+ 8 ginsn: ADD %r31, 2134, %r29
+ 9 \?\?\?\? FF8300D1 sub sp, sp, 32
+ 9 ginsn: SUB %r31, 32, %r31
+ 10 \?\?\?\? FD5B21F1 subs x29, sp, 2134
+ 10 ginsn: SUB %r31, 2134, %r29
+ 11 \?\?\?\? FD63228B add x29, sp, x2
+ 11 ginsn: ADD %r31, %r2, %r29
+ 12 \?\?\?\? FD6323CB sub x29, sp, x3
+ 12 ginsn: SUB %r31, %r3, %r29
+ 13 \?\?\?\? BF63238B add sp, x29, x3
+ 13 ginsn: ADD %r29, %r3, %r31
+ 14 \?\?\?\? BF6322CB sub sp, x29, x2
+ 14 ginsn: SUB %r29, %r2, %r31
+ 15 \?\?\?\? C0035FD6 ret
+ 15 ginsn: RET
+ 16 .size foo, .-foo
+ 16 ginsn: SYM FUNC_END
diff --git a/gas/testsuite/gas/scfi/aarch64/ginsn-arith-1.s b/gas/testsuite/gas/scfi/aarch64/ginsn-arith-1.s
new file mode 100644
index 00000000000..749a51a70b4
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/ginsn-arith-1.s
@@ -0,0 +1,16 @@
+# Testcase for a variety of arith instructions
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+ add sp, sp, 32
+ adds x29, sp, 2134
+ sub sp, sp, 32
+ subs x29, sp, 2134
+ add x29, sp, x2
+ sub x29, sp, x3
+ add sp, x29, x3
+ sub sp, x29, x2
+ ret
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.l b/gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.l
new file mode 100644
index 00000000000..d05e19d059d
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.l
@@ -0,0 +1,30 @@
+.*: Assembler messages:
+.*:16: Error: untraceable control flow for func 'foo'
+
+AARCH64 GAS .*
+
+ 1 # Testcase for a variety of change of flow instructions
+ 2 # Because some of these are indirect branches, SCFI will bail out
+ 3 # with an error. This test merely checks that the ginsn creation
+ 4 # process can handle these insns gracefully.
+ 5 .text
+ 6 .align 2
+ 7 .global foo
+ 8 .type foo, %function
+ 8 ginsn: SYM FUNC_BEGIN
+ 9 foo:
+ 9 ginsn: SYM foo
+ 10 \?\?\?\? 00000094 bl dump_bt
+ 10 ginsn: CALL
+ 11 \?\?\?\? 02000014 b .L3
+ 11 ginsn: JMP
+ 12 \?\?\?\? 20021FD6 br x17
+ 12 ginsn: JMP %r17,
+ 13 .L3:
+ 13 ginsn: SYM .L3
+ 14 \?\?\?\? 60003FD6 blr x3
+ 14 ginsn: CALL
+ 15 \?\?\?\? C0035FD6 ret
+ 15 ginsn: RET
+ 16 .size foo, .-foo
+ 16 ginsn: SYM FUNC_END
diff --git a/gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.s b/gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.s
new file mode 100644
index 00000000000..bbcbe4e02a4
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/ginsn-cofi-1.s
@@ -0,0 +1,16 @@
+# Testcase for a variety of change of flow instructions
+# Because some of these are indirect branches, SCFI will bail out
+# with an error. This test merely checks that the ginsn creation
+# process can handle these insns gracefully.
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+ bl dump_bt
+ b .L3
+ br x17
+.L3:
+ blr x3
+ ret
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.l b/gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.l
new file mode 100644
index 00000000000..c71310d558f
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.l
@@ -0,0 +1,78 @@
+AARCH64 GAS .*
+
+ 1 # Testcase for a variety of ld st instructions
+ 2 .text
+ 3 .align 2
+ 4 .global foo
+ 5 .type foo, %function
+ 5 ginsn: SYM FUNC_BEGIN
+ 6 foo:
+ 6 ginsn: SYM foo
+ 7 # ldstpair_indexed
+ 8 0000 FF7F8629 stp wzr, wzr, \[sp, 48\]!
+ 8 ginsn: ADD %r31, 48, %r31
+ 9 0004 E00782A9 stp x0, x1, \[sp, 32\]!
+ 9 ginsn: ADD %r31, 32, %r31
+ 9 ginsn: STORE %r0, \[%r31\+0\]
+ 9 ginsn: STORE %r1, \[%r31\+8\]
+ 10 0008 E827BC6D stp d8, d9, \[sp, -64\]!
+ 10 ginsn: ADD %r31, -64, %r31
+ 10 ginsn: STORE %r72, \[%r31\+0\]
+ 10 ginsn: STORE %r73, \[%r31\+8\]
+ 11 000c E827C46C ldp d8, d9, \[sp\], 64
+ 11 ginsn: LOAD \[%r31\+0\], %r72
+ 11 ginsn: LOAD \[%r31\+8\], %r73
+ 11 ginsn: ADD %r31, 64, %r31
+ 12 # 32-bit FP regs
+ 13 0010 E51BB42D stp s5, s6, \[sp, -96\]!
+ 13 ginsn: ADD %r31, -96, %r31
+ 13 ginsn: STORE %r69, \[%r31\+0\]
+ 13 ginsn: STORE %r70, \[%r31\+4\]
+ 14 0014 E51BCC2C ldp s5, s6, \[sp\], 96
+ 14 ginsn: LOAD \[%r31\+0\], %r69
+ 14 ginsn: LOAD \[%r31\+4\], %r70
+ 14 ginsn: ADD %r31, 96, %r31
+ 15 # 32-bit INT regs
+ 16 0018 E10BB029 stp w1, w2, \[sp, -128\]!
+ 16 ginsn: ADD %r31, -128, %r31
+ 16 ginsn: STORE %r1, \[%r31\+0\]
+ 16 ginsn: STORE %r2, \[%r31\+4\]
+ 17 001c E10BD028 ldp w1, w2, \[sp\], 128
+ 17 ginsn: LOAD \[%r31\+0\], %r1
+ 17 ginsn: LOAD \[%r31\+4\], %r2
+ 17 ginsn: ADD %r31, 128, %r31
+ 18 # ldstpair_off
+ 19 0020 E00702AD stp q0, q1, \[sp, 64\]
+ 19 ginsn: STORE %r64, \[%r31\+64\]
+ 19 ginsn: STORE %r65, \[%r31\+80\]
+ 20 0024 FF7F0629 stp wzr, wzr, \[sp, 48\]
+ 21 0028 1F7840AD ldp q31, q30, \[x0\]
+ 22 # ldst_imm9
+ 23 002c E78F4F38 ldrb w7, \[sp, 248\]!
+ 23 ginsn: ADD %r31, 248, %r31
+ 23 ginsn: LOAD \[%r31\+0\], %r7
+ 24 0030 FD0FC33C ldr q29, \[sp, 48\]!
+ 24 ginsn: ADD %r31, 48, %r31
+ 24 ginsn: LOAD \[%r31\+0\], %r93
+ 25 0034 FF0F42B8 ldr wzr, \[sp, 32\]!
+ 25 ginsn: ADD %r31, 32, %r31
+ 26 0038 E30742F8 ldr x3, \[sp\], 32
+\fAARCH64 GAS .*
+
+
+ 26 ginsn: LOAD \[%r31\+0\], %r3
+ 26 ginsn: ADD %r31, 32, %r31
+ 27 # 32-bit ldr
+ 28 003c E10744BC ldr s1, \[sp\], 64
+ 28 ginsn: LOAD \[%r31\+0\], %r65
+ 28 ginsn: ADD %r31, 64, %r31
+ 29 #ldst_pos
+ 30 0040 FF3340B9 ldr wzr, \[sp, 48\]
+ 31 0044 FD1300F9 str x29, \[sp, 32\]
+ 31 ginsn: STORE %r29, \[%r31\+32\]
+ 32 0048 FD1340F9 ldr x29, \[sp, 32\]
+ 32 ginsn: LOAD \[%r31\+32\], %r29
+ 33 004c C0035FD6 ret
+ 33 ginsn: RET
+ 34 .size foo, .-foo
+ 34 ginsn: SYM FUNC_END
diff --git a/gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.s b/gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.s
new file mode 100644
index 00000000000..22a6fea28d0
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/ginsn-ldst-1.s
@@ -0,0 +1,34 @@
+# Testcase for a variety of ld st instructions
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+# ldstpair_indexed
+ stp wzr, wzr, [sp, 48]!
+ stp x0, x1, [sp, 32]!
+ stp d8, d9, [sp, -64]!
+ ldp d8, d9, [sp], 64
+# 32-bit FP regs
+ stp s5, s6, [sp, -96]!
+ ldp s5, s6, [sp], 96
+# 32-bit INT regs
+ stp w1, w2, [sp, -128]!
+ ldp w1, w2, [sp], 128
+# ldstpair_off
+ stp q0, q1, [sp, 64]
+ stp wzr, wzr, [sp, 48]
+ ldp q31, q30, [x0]
+# ldst_imm9
+ ldrb w7, [sp, 248]!
+ ldr q29, [sp, 48]!
+ ldr wzr, [sp, 32]!
+ ldr x3, [sp], 32
+# 32-bit ldr
+ ldr s1, [sp], 64
+#ldst_pos
+ ldr wzr, [sp, 48]
+ str x29, [sp, 32]
+ ldr x29, [sp, 32]
+ ret
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.l b/gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.l
new file mode 100644
index 00000000000..310245bd947
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.l
@@ -0,0 +1,27 @@
+.*: Assembler messages:
+.*:9: Error: SCFI: unsupported stack manipulation pattern
+.*:13: Error: SCFI: forward pass failed for func 'foo'
+
+AARCH64 GAS .*
+
+
+ 1 # Testcase for a variety of misc instructions
+ 2 # Ensure graceful handling, irrespective of ginsn generation
+ 3 symbol:
+ 4 \?\?\?\? 7700 .string "w"
+ 5
+ 6 .type foo, %function
+ 6 ginsn: SYM FUNC_BEGIN
+ 7 foo:
+ 7 ginsn: SYM foo
+ 8 \?\?\?\? 00000000 adrp x0, symbol
+ 8 0090
+ 9 \?\?\?\? 1F000091 add sp, x0, :lo12:symbol
+ 9 ginsn: OTH 0, 0, %r31
+ 10 \?\?\?\? 2000A0F2 movk x0, 0x1, lsl 16
+ 11 \?\?\?\? E10380F9 prfm PLDL1STRM, \[sp\]
+ 11 ginsn: LOAD \[%r31\+0\], %r1
+ 12 \?\?\?\? C0035FD6 ret
+ 12 ginsn: RET
+ 13 .size foo,.-foo
+ 13 ginsn: SYM FUNC_END
diff --git a/gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.s b/gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.s
new file mode 100644
index 00000000000..e1b31c113ad
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/ginsn-misc-1.s
@@ -0,0 +1,13 @@
+# Testcase for a variety of misc instructions
+# Ensure graceful handling, irrespective of ginsn generation
+symbol:
+ .string "w"
+
+ .type foo, %function
+foo:
+ adrp x0, symbol
+ add sp, x0, :lo12:symbol
+ movk x0, 0x1, lsl 16
+ prfm PLDL1STRM, [sp]
+ ret
+ .size foo,.-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-aarch64.exp b/gas/testsuite/gas/scfi/aarch64/scfi-aarch64.exp
new file mode 100644
index 00000000000..d53e136d7f1
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-aarch64.exp
@@ -0,0 +1,70 @@
+# Copyright (C) 2022-2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+if { ![is_elf_format] } then {
+ return
+}
+
+# common tests
+if { ([istarget "aarch64-*-*"]) } then {
+
+ global ASFLAGS
+ set old_ASFLAGS "$ASFLAGS"
+
+ run_list_test "ginsn-arith-1" "--scfi=experimental -ali --warn"
+ run_list_test "ginsn-cofi-1" "--scfi=experimental -ali --warn"
+ run_list_test "ginsn-ldst-1" "--scfi=experimental -ali --warn"
+ run_list_test "ginsn-misc-1" "--scfi=experimental -ali --warn"
+
+ run_list_test "scfi-diag-1" "--scfi=experimental"
+ run_list_test "scfi-diag-2" "--scfi=experimental"
+ run_list_test "scfi-diag-3" "--scfi=experimental"
+
+ run_list_test "scfi-unsupported-1" "--scfi=experimental"
+
+ run_dump_test "scfi-callee-saved-fp-1"
+ run_list_test "scfi-callee-saved-fp-1" "--scfi=experimental --warn"
+ run_dump_test "scfi-callee-saved-fp-2"
+ run_list_test "scfi-callee-saved-fp-2" "--scfi=experimental --warn"
+
+ run_dump_test "scfi-ldrp-1"
+ run_list_test "scfi-ldrp-1" "--scfi=experimental --warn"
+ run_dump_test "scfi-ldrp-2"
+ run_list_test "scfi-ldrp-2" "--scfi=experimental --warn"
+
+ run_dump_test "scfi-strp-1"
+ run_list_test "scfi-strp-1" "--scfi=experimental --warn"
+ run_dump_test "scfi-strp-2"
+ run_list_test "scfi-strp-2" "--scfi=experimental --warn"
+
+ run_dump_test "scfi-cb-1"
+ run_list_test "scfi-cb-1" "--scfi=experimental --warn"
+ run_dump_test "scfi-cond-br-1"
+ run_list_test "scfi-cond-br-1" "--scfi=experimental --warn"
+
+ run_dump_test "scfi-cfg-1"
+ run_list_test "scfi-cfg-1" "--scfi=experimental --warn"
+
+ run_dump_test "scfi-cfg-2"
+ run_list_test "scfi-cfg-2" "--scfi=experimental --warn"
+
+ run_dump_test "scfi-cfg-3"
+ run_list_test "scfi-cfg-3" "--scfi=experimental --warn"
+
+ run_dump_test "scfi-cfg-4"
+ run_list_test "scfi-cfg-4" "--scfi=experimental --warn"
+
+}
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.d b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.d
new file mode 100644
index 00000000000..da4b8a0bee0
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.d
@@ -0,0 +1,57 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for callee-saved FP regs I
+#...
+Contents of the .eh_frame section:
+
+00000000 0+0010 00000000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+00000014 0+[0-9a-f]+ 0+0018 FDE cie=00000000 pc=0+0000..0+0040
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 128
+ DW_CFA_offset: r29 \(x29\) at cfa-128
+ DW_CFA_offset: r30 \(x30\) at cfa-120
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 4 to 0+000c
+ DW_CFA_offset_extended: r72 \(v8\) at cfa-112
+ DW_CFA_advance_loc: 4 to 0+0010
+ DW_CFA_offset_extended: r73 \(v9\) at cfa-104
+ DW_CFA_advance_loc: 4 to 0+0014
+ DW_CFA_offset_extended: r74 \(v10\) at cfa-96
+ DW_CFA_offset_extended: r75 \(v11\) at cfa-88
+ DW_CFA_advance_loc: 4 to 0+0018
+ DW_CFA_offset_extended: r76 \(v12\) at cfa-80
+ DW_CFA_offset_extended: r77 \(v13\) at cfa-72
+ DW_CFA_advance_loc: 4 to 0+001c
+ DW_CFA_offset_extended: r78 \(v14\) at cfa-64
+ DW_CFA_offset_extended: r79 \(v15\) at cfa-56
+ DW_CFA_advance_loc: 8 to 0+0024
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_advance_loc: 4 to 0+0028
+ DW_CFA_restore_extended: r72 \(v8\)
+ DW_CFA_advance_loc: 4 to 0+002c
+ DW_CFA_restore_extended: r73 \(v9\)
+ DW_CFA_advance_loc: 4 to 0+0030
+ DW_CFA_restore_extended: r74 \(v10\)
+ DW_CFA_restore_extended: r75 \(v11\)
+ DW_CFA_advance_loc: 4 to 0+0034
+ DW_CFA_restore_extended: r76 \(v12\)
+ DW_CFA_restore_extended: r77 \(v13\)
+ DW_CFA_advance_loc: 4 to 0+0038
+ DW_CFA_restore_extended: r78 \(v14\)
+ DW_CFA_restore_extended: r79 \(v15\)
+ DW_CFA_advance_loc: 4 to 0+003c
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.l b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.l
new file mode 100644
index 00000000000..5ff6048bef0
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*8: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.s b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.s
new file mode 100644
index 00000000000..0f7afe278fc
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-1.s
@@ -0,0 +1,50 @@
+# Testcase for callee-saved FP registers.
+# Uses a combination of str/stp and ldr/ldp
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+ stp x29, x30, [sp, -128]!
+ .cfi_def_cfa_offset 128
+ .cfi_offset 29, -128
+ .cfi_offset 30, -120
+ mov x29, sp
+ .cfi_def_cfa_register 29
+ str d8, [sp, 16]
+ .cfi_offset 72, -112
+ str d9, [sp, 24]
+ .cfi_offset 73, -104
+ stp d10, d11, [sp, 32]
+ .cfi_offset 74, -96
+ .cfi_offset 75, -88
+ stp d12, d13, [sp, 48]
+ .cfi_offset 76, -80
+ .cfi_offset 77, -72
+ stp d14, d15, [sp, 64]
+ .cfi_offset 78, -64
+ .cfi_offset 79, -56
+ mov w0, 0
+ mov sp, x29
+ .cfi_def_cfa_register 31
+ ldr d8, [sp, 16]
+ .cfi_restore 72
+ ldr d9, [sp, 24]
+ .cfi_restore 73
+ ldp d10, d11, [sp, 32]
+ .cfi_restore 74
+ .cfi_restore 75
+ ldp d12, d13, [sp, 48]
+ .cfi_restore 76
+ .cfi_restore 77
+ ldp d14, d15, [sp, 64]
+ .cfi_restore 78
+ .cfi_restore 79
+ ldp x29, x30, [sp], 128
+ .cfi_restore 29
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.d b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.d
new file mode 100644
index 00000000000..0e3de4c2ffb
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.d
@@ -0,0 +1,57 @@
+#as: --scfi=experimental -W -mbig-endian
+#objdump: -Wf
+#name: Synthesize CFI for callee-saved FP regs BE II
+#...
+Contents of the .eh_frame section:
+
+00000000 0+0010 00000000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+00000014 0+[0-9a-f]+ 0+0018 FDE cie=00000000 pc=0+0000..0+0040
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 256
+ DW_CFA_offset: r29 \(x29\) at cfa-256
+ DW_CFA_offset: r30 \(x30\) at cfa-248
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 4 to 0+000c
+ DW_CFA_offset_extended: r72 \(v8\) at cfa-232
+ DW_CFA_advance_loc: 4 to 0+0010
+ DW_CFA_offset_extended: r73 \(v9\) at cfa-216
+ DW_CFA_advance_loc: 4 to 0+0014
+ DW_CFA_offset_extended: r74 \(v10\) at cfa-184
+ DW_CFA_offset_extended: r75 \(v11\) at cfa-168
+ DW_CFA_advance_loc: 4 to 0+0018
+ DW_CFA_offset_extended: r76 \(v12\) at cfa-152
+ DW_CFA_offset_extended: r77 \(v13\) at cfa-136
+ DW_CFA_advance_loc: 4 to 0+001c
+ DW_CFA_offset_extended: r78 \(v14\) at cfa-120
+ DW_CFA_offset_extended: r79 \(v15\) at cfa-104
+ DW_CFA_advance_loc: 8 to 0+0024
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_advance_loc: 4 to 0+0028
+ DW_CFA_restore_extended: r72 \(v8\)
+ DW_CFA_advance_loc: 4 to 0+002c
+ DW_CFA_restore_extended: r73 \(v9\)
+ DW_CFA_advance_loc: 4 to 0+0030
+ DW_CFA_restore_extended: r74 \(v10\)
+ DW_CFA_restore_extended: r75 \(v11\)
+ DW_CFA_advance_loc: 4 to 0+0034
+ DW_CFA_restore_extended: r76 \(v12\)
+ DW_CFA_restore_extended: r77 \(v13\)
+ DW_CFA_advance_loc: 4 to 0+0038
+ DW_CFA_restore_extended: r78 \(v14\)
+ DW_CFA_restore_extended: r79 \(v15\)
+ DW_CFA_advance_loc: 4 to 0+003c
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.l b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.l
new file mode 100644
index 00000000000..5ff6048bef0
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*8: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.s b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.s
new file mode 100644
index 00000000000..4204daf736d
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-callee-saved-fp-2.s
@@ -0,0 +1,50 @@
+# Testcase for callee-saved FP registers.
+# Use Q registers
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+ stp x29, x30, [sp, -256]!
+ .cfi_def_cfa_offset 256
+ .cfi_offset 29, -256
+ .cfi_offset 30, -248
+ mov x29, sp
+ .cfi_def_cfa_register 29
+ str q8, [sp, 16]
+ .cfi_offset 72, -232
+ str q9, [sp, 32]
+ .cfi_offset 73, -216
+ stp q10, q11, [sp, 64]
+ .cfi_offset 74, -184
+ .cfi_offset 75, -168
+ stp q12, q13, [sp, 96]
+ .cfi_offset 76, -152
+ .cfi_offset 77, -136
+ stp q14, q15, [sp, 128]
+ .cfi_offset 78, -120
+ .cfi_offset 79, -104
+ mov w0, 0
+ mov sp, x29
+ .cfi_def_cfa_register 31
+ ldr q8, [sp, 16]
+ .cfi_restore 72
+ ldr q9, [sp, 32]
+ .cfi_restore 73
+ ldp q10, q11, [sp, 64]
+ .cfi_restore 74
+ .cfi_restore 75
+ ldp q12, q13, [sp, 96]
+ .cfi_restore 76
+ .cfi_restore 77
+ ldp q14, q15, [sp, 128]
+ .cfi_restore 78
+ .cfi_restore 79
+ ldp x29, x30, [sp], 256
+ .cfi_restore 29
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.d b/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.d
new file mode 100644
index 00000000000..87583c58b3f
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.d
@@ -0,0 +1,20 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for comp branch 1
+#...
+Contents of the .eh_frame section:
+
+
+0+0000 0+0010 0+0000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+0+0014 0+0010 00000018 FDE cie=00000000 pc=0+0000..0+0014
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.l b/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.l
new file mode 100644
index 00000000000..abca835a642
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*5: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.s b/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.s
new file mode 100644
index 00000000000..1fa7de7639a
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cb-1.s
@@ -0,0 +1,14 @@
+ .text
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+.L7:
+ add w4, w3, w1
+ cbnz w4, .L7
+ cbz w4, .L10
+ tbnz w0, #31, .L7
+.L10:
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.d b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.d
new file mode 100644
index 00000000000..9dca6efaad7
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.d
@@ -0,0 +1,31 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for cfg 1
+#...
+Contents of the .eh_frame section:
+
+
+0+0000 0+0010 0+0000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+0+0014 0+0020 0+0018 FDE cie=00000000 pc=0+0000..0+0068
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 48
+ DW_CFA_offset: r29 \(x29\) at cfa-48
+ DW_CFA_offset: r30 \(x30\) at cfa-40
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 92 to 0+0064
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.l b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.l
new file mode 100644
index 00000000000..bcf3095a9bb
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*6: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.s b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.s
new file mode 100644
index 00000000000..6925a8f7e38
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-1.s
@@ -0,0 +1,46 @@
+# Testcase for forward flow of SCFI information
+# and CFG creation as well. This testcase has two backward edges
+# (one of which is a loop) and one exit path.
+ .type foo, %function
+foo:
+ .cfi_startproc
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ mov x29, sp
+ .cfi_def_cfa_register 29
+ str x0, [sp, 24]
+ adrp x0, :got:xyz
+ str x0, [sp, 40]
+ b .L7
+.L10:
+ ldr x0, [sp, 40]
+ ldr x0, [x0]
+ mov x1, x0
+ ldr x0, [sp, 24]
+ bl strcmp
+ cmp w0, 0
+ bne .L8
+ ldr x0, [sp, 40]
+ ldr w0, [x0, 8]
+ b .L9
+.L8:
+ ldr x0, [sp, 40]
+ add x0, x0, 24
+ str x0, [sp, 40]
+.L7:
+ ldr x0, [sp, 40]
+ ldr w0, [x0, 8]
+ cmp w0, 0
+ bne .L10
+ mov w0, 0
+.L9:
+ ldp x29, x30, [sp], 48
+ .cfi_def_cfa_register 31
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.d b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.d
new file mode 100644
index 00000000000..af21fc14b4c
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.d
@@ -0,0 +1,40 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for cfg 2
+#...
+Contents of the .eh_frame section:
+
+
+0+0000 0+0010 0+0000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+0+0014 0+[0-9a-f]+ 0+0018 FDE cie=00000000 pc=0+0000..0+0028
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 48
+ DW_CFA_offset: r29 \(x29\) at cfa-48
+ DW_CFA_offset: r30 \(x30\) at cfa-40
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 8 to 0+0010
+ DW_CFA_remember_state
+ DW_CFA_advance_loc: 8 to 0+0018
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_advance_loc: 4 to 0+001c
+ DW_CFA_restore_state
+ DW_CFA_advance_loc: 8 to 0+0024
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.l b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.l
new file mode 100644
index 00000000000..e9bde339b1e
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*13: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.s b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.s
new file mode 100644
index 00000000000..eef82b4ad24
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-2.s
@@ -0,0 +1,42 @@
+# Testcase for backward flow of SCFI state.
+# The cfg has two exit paths, with epilogue duplicated in
+# the two.
+#
+# SCFI must synthesize the remember_state / restore_state pair.
+# Note how SCFI does not necessary generate the least number of
+# CFI directives (.cfi_remember_state can possibly be clubbed
+# together with other immediately following CFI directives).
+# This is not a correctness issue, however.
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ mov x29, sp
+ .cfi_def_cfa_register 29
+ cmp w4, w19
+ bge .L1
+
+.L2:
+ .cfi_remember_state
+ bl bar
+ ldp x29, x30, [sp], 48
+ .cfi_def_cfa_register 31
+ .cfi_restore 29
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+.L1:
+ .cfi_restore_state
+ cbz w3, .L2
+ ldp x29, x30, [sp], 48
+ .cfi_def_cfa_register 31
+ .cfi_restore 29
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.d b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.d
new file mode 100644
index 00000000000..4d17ee4a475
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.d
@@ -0,0 +1,32 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for cfg 3
+#...
+Contents of the .eh_frame section:
+
+
+0+0000 0+0010 0+0000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+0+0014 0+0020 0+0018 FDE cie=00000000 pc=0+0000..0+002c
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 32
+ DW_CFA_offset: r29 \(x29\) at cfa-32
+ DW_CFA_offset: r30 \(x30\) at cfa-24
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 32 to 0+0028
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_nop
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.l b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.l
new file mode 100644
index 00000000000..23ca73422b5
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*9: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.s b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.s
new file mode 100644
index 00000000000..2782e11f6d3
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-3.s
@@ -0,0 +1,34 @@
+# Testcase for cfg creation.
+# There is at least one bb here with a single GINSN_TYPE_SYMBOL instruction
+# for a user-defined label. This ginsn is visited in the fallthrough path of
+# another bb.
+ .text
+ .global main
+ .type main, %function
+main:
+ .cfi_startproc
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ mov x29, sp
+ .cfi_def_cfa_register 29
+ cmp w0, 0
+ bne .L2
+# ldr x0, [sp, 24]
+# bl fclose
+ cmp w0, 0
+ beq .L3
+.L2:
+ mov w0, 1
+ b .L5
+.L3:
+ mov w0, 0
+.L5:
+ ldp x29, x30, [sp], 32
+ .cfi_def_cfa_register 31
+ .cfi_restore 29
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.d b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.d
new file mode 100644
index 00000000000..6a23818ad6f
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.d
@@ -0,0 +1,41 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for cfg 4
+#...
+Contents of the .eh_frame section:
+
+
+0+0000 0+0010 0+0000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+0+0014 0+[0-9a-f]+ 0+0018 FDE cie=00000000 pc=0+0000..0+002c
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 32
+ DW_CFA_offset: r29 \(x29\) at cfa-32
+ DW_CFA_offset: r30 \(x30\) at cfa-24
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 8 to 0+0010
+ DW_CFA_offset: r19 \(x19\) at cfa-16
+ DW_CFA_advance_loc: 4 to 0+0014
+ DW_CFA_remember_state
+ DW_CFA_advance_loc: 4 to 0+0018
+ DW_CFA_restore: r19 \(x19\)
+ DW_CFA_advance_loc: 8 to 0+0020
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_advance_loc: 4 to 0+0024
+ DW_CFA_restore_state
+ DW_CFA_advance_loc: 4 to 0+0028
+ DW_CFA_restore: r19 \(x19\)
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.l b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.l
new file mode 100644
index 00000000000..6ec24387b8c
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*7: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.s b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.s
new file mode 100644
index 00000000000..499278ddcb8
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cfg-4.s
@@ -0,0 +1,41 @@
+# Testcase for forward flow of SCFI information.
+# This testcase has two paths landing at the exit basic block,
+# where only one of the exit paths has a save/restore of x19
+# (while the other does not).
+ .type foo, %function
+foo:
+ .cfi_startproc
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ mov x29, sp
+ .cfi_def_cfa_register 29
+# do some work ...
+ cbz x0, .L2
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+# do some other work ...
+ cbz w0, .L3
+ ldr x19, [sp, 16]
+ .cfi_restore 19
+.L2:
+ mov w0, 1
+.L1:
+ ldp x29, x30, [sp], 32
+ .cfi_def_cfa_register 31
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa_offset 0
+ ret
+.L3:
+ .cfi_def_cfa_offset 32
+ .cfi_offset 19, -16
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+# do yet some other work before return
+ ldr x19, [sp, 16]
+ .cfi_restore 19
+ b .L1
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.d b/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.d
new file mode 100644
index 00000000000..dc656c78038
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.d
@@ -0,0 +1,20 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for conditional br 1
+#...
+Contents of the .eh_frame section:
+
+
+0+0000 0+0010 0+0000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+0+0014 0+0010 00000018 FDE cie=00000000 pc=0+0000..0+0010
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.l b/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.l
new file mode 100644
index 00000000000..bcf3095a9bb
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*6: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.s b/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.s
new file mode 100644
index 00000000000..03c330df04a
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-cond-br-1.s
@@ -0,0 +1,13 @@
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+ bge .L10
+ ble .L10
+ bne .L10
+.L10:
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-diag-1.l b/gas/testsuite/gas/scfi/aarch64/scfi-diag-1.l
new file mode 100644
index 00000000000..5a8e36923a7
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-diag-1.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*5: Warning: SCFI: ignored probable save/restore op with reg offset
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-diag-1.s b/gas/testsuite/gas/scfi/aarch64/scfi-diag-1.s
new file mode 100644
index 00000000000..a6eac51998e
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-diag-1.s
@@ -0,0 +1,6 @@
+ .text
+ .globl foo
+ .type foo, @function
+foo:
+ str x19, [sp, x1]
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-diag-2.l b/gas/testsuite/gas/scfi/aarch64/scfi-diag-2.l
new file mode 100644
index 00000000000..03a5f4fb908
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-diag-2.l
@@ -0,0 +1,3 @@
+.*Assembler messages:
+.*7: Warning: SCFI ignores most user-specified CFI directives
+.*16: Warning: GINSN: found unreachable code in func 'foo'
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-diag-2.s b/gas/testsuite/gas/scfi/aarch64/scfi-diag-2.s
new file mode 100644
index 00000000000..7464fa9efee
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-diag-2.s
@@ -0,0 +1,25 @@
+# Testcase that triggers a diagnostic for unreachable code for
+# the block of code after label .L2. This also serves as a testcase
+# for cfg creation, as the said code block should not have been
+# included in the CFG (and hence the warning).
+ .type foo, %function
+foo:
+ .cfi_startproc
+ ldr w1, [x0]
+ cmp w1, 8
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, 16
+ .cfi_offset 20, 24
+ b .L1
+.L2:
+ mov w0, w1
+ ret
+.L1:
+ mov w0, w1
+ ldp x19, x20, [sp, 16]
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-diag-3.l b/gas/testsuite/gas/scfi/aarch64/scfi-diag-3.l
new file mode 100644
index 00000000000..f1b960449ae
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-diag-3.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*7: Error: SCFI: unhandled op 0xe5e0e000 may cause incorrect CFI
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-diag-3.s b/gas/testsuite/gas/scfi/aarch64/scfi-diag-3.s
new file mode 100644
index 00000000000..dee87f30b08
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-diag-3.s
@@ -0,0 +1,8 @@
+# Testcase with an SVE instruction with Z register usage
+# of a callee-saved register. Currently these are not handled
+# and the SCFI machinery must error out.
+ .arch armv8-a+sve
+ .type foo, %function
+foo:
+ st1d z8.d, p2, [sp, #1, mul vl]
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.d b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.d
new file mode 100644
index 00000000000..ce8fab5813a
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.d
@@ -0,0 +1,59 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for ldp ldr instructions
+#...
+Contents of the .eh_frame section:
+
+00000000 0+0010 00000000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+00000014 0+0048 00000018 FDE cie=00000000 pc=0+0000..0+0040
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 128
+ DW_CFA_offset: r29 \(x29\) at cfa-128
+ DW_CFA_offset: r30 \(x30\) at cfa-120
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 4 to 0+000c
+ DW_CFA_offset: r19 \(x19\) at cfa-112
+ DW_CFA_offset: r20 \(x20\) at cfa-104
+ DW_CFA_advance_loc: 4 to 0+0010
+ DW_CFA_offset: r21 \(x21\) at cfa-96
+ DW_CFA_offset: r22 \(x22\) at cfa-88
+ DW_CFA_advance_loc: 4 to 0+0014
+ DW_CFA_offset: r23 \(x23\) at cfa-80
+ DW_CFA_offset: r24 \(x24\) at cfa-72
+ DW_CFA_advance_loc: 4 to 0+0018
+ DW_CFA_offset: r25 \(x25\) at cfa-64
+ DW_CFA_offset: r26 \(x26\) at cfa-56
+ DW_CFA_advance_loc: 4 to 0+001c
+ DW_CFA_offset: r27 \(x27\) at cfa-48
+ DW_CFA_advance_loc: 8 to 0+0024
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_advance_loc: 4 to 0+0028
+ DW_CFA_restore: r19 \(x19\)
+ DW_CFA_restore: r20 \(x20\)
+ DW_CFA_advance_loc: 4 to 0+002c
+ DW_CFA_restore: r21 \(x21\)
+ DW_CFA_restore: r22 \(x22\)
+ DW_CFA_advance_loc: 4 to 0+0030
+ DW_CFA_restore: r23 \(x23\)
+ DW_CFA_restore: r24 \(x24\)
+ DW_CFA_advance_loc: 4 to 0+0034
+ DW_CFA_restore: r25 \(x25\)
+ DW_CFA_restore: r26 \(x26\)
+ DW_CFA_advance_loc: 4 to 0+0038
+ DW_CFA_restore: r27 \(x27\)
+ DW_CFA_advance_loc: 4 to 0+003c
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.l b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.l
new file mode 100644
index 00000000000..5ff6048bef0
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*8: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.s b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.s
new file mode 100644
index 00000000000..4226d71b3b3
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-1.s
@@ -0,0 +1,52 @@
+# Testcase for various ldp / ldr instructions.
+# This test also serves for checking callee-saved regs.
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+ stp x29, x30, [sp, -128]!
+ .cfi_def_cfa_offset 128
+ .cfi_offset 29, -128
+ .cfi_offset 30, -120
+ mov x29, sp
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -112
+ .cfi_offset 20, -104
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -96
+ .cfi_offset 22, -88
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -80
+ .cfi_offset 24, -72
+ stp x25, x26, [sp, 64]
+ .cfi_offset 25, -64
+ .cfi_offset 26, -56
+ str x27, [sp, 80]
+ .cfi_offset 27, -48
+ mov w0, 0
+ mov sp, x29
+ .cfi_def_cfa_register 31
+ ldp x19, x20, [sp, 16]
+ .cfi_restore 19
+ .cfi_restore 20
+ ldp x21, x22, [sp, 32]
+ .cfi_restore 21
+ .cfi_restore 22
+ ldp x23, x24, [sp, 48]
+ .cfi_restore 23
+ .cfi_restore 24
+ ldp x25, x26, [sp, 64]
+ .cfi_restore 25
+ .cfi_restore 26
+ ldr x27, [sp, 80]
+ .cfi_restore 27
+ ldp x29, x30, [sp], 128
+ .cfi_restore 29
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.d b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.d
new file mode 100644
index 00000000000..2a0fdb60e0e
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.d
@@ -0,0 +1,33 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for ldr insns 2
+#...
+Contents of the .eh_frame section:
+
+00000000 0+0010 00000000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+00000014 0+[0-9a-f]+ 00000018 FDE cie=00000000 pc=0+0000..0+0018
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 128
+ DW_CFA_offset: r29 \(x29\) at cfa-128
+ DW_CFA_offset: r30 \(x30\) at cfa-120
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 4 to 0+000c
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_advance_loc: 4 to 0+0010
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_def_cfa_offset: 120
+ DW_CFA_advance_loc: 4 to 0+0014
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.l b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.l
new file mode 100644
index 00000000000..6ec24387b8c
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*7: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.s b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.s
new file mode 100644
index 00000000000..ac4ad6836ed
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-ldrp-2.s
@@ -0,0 +1,26 @@
+# Testcase for various ldp / ldr instructions
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+ stp x29, x30, [sp, -128]!
+ .cfi_def_cfa_offset 128
+ .cfi_offset 29, -128
+ .cfi_offset 30, -120
+ mov x29, sp
+ .cfi_def_cfa_register 29
+ mov sp, x29
+ .cfi_def_cfa_register 31
+# Post-indexed ldr
+ ldr x29, [sp], 8
+ .cfi_restore 29
+ .cfi_def_cfa_offset 120
+# Post-indexed ldr
+ ldr x30, [sp], 120
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.d b/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.d
new file mode 100644
index 00000000000..cebd254aa00
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.d
@@ -0,0 +1,39 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for str stp insns 1
+#...
+Contents of the .eh_frame section:
+
+00000000 0+0010 00000000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+00000014 0+0030 00000018 FDE cie=00000000 pc=0+0000..0+002c
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 128
+ DW_CFA_offset: r29 \(x29\) at cfa-128
+ DW_CFA_offset: r30 \(x30\) at cfa-120
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 4 to 0+000c
+ DW_CFA_offset: r19 \(x19\) at cfa-112
+ DW_CFA_offset: r20 \(x20\) at cfa-104
+ DW_CFA_advance_loc: 4 to 0+0010
+ DW_CFA_offset: r21 \(x21\) at cfa-96
+ DW_CFA_offset: r22 \(x22\) at cfa-88
+ DW_CFA_advance_loc: 4 to 0+0014
+ DW_CFA_offset: r23 \(x23\) at cfa-80
+ DW_CFA_offset: r24 \(x24\) at cfa-72
+ DW_CFA_advance_loc: 4 to 0+0018
+ DW_CFA_offset: r25 \(x25\) at cfa-64
+ DW_CFA_offset: r26 \(x26\) at cfa-56
+ DW_CFA_advance_loc: 4 to 0+001c
+ DW_CFA_offset: r27 \(x27\) at cfa-48
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.l b/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.l
new file mode 100644
index 00000000000..bcf3095a9bb
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*6: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.s b/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.s
new file mode 100644
index 00000000000..932ca4ad705
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-strp-1.s
@@ -0,0 +1,37 @@
+## Testcase with a variety of str/stp instructions
+ .text
+ .globl foo
+ .type foo, @function
+foo:
+ .cfi_startproc
+# Pre-indexed addressing is like offset addressing, except that
+# the base pointer is updated as a result of the instruction.
+ stp x29, x30, [sp, -128]!
+ .cfi_def_cfa_offset 128
+ .cfi_offset 29, -128
+ .cfi_offset 30, -120
+ mov x29, sp
+ .cfi_def_cfa_register 29
+# Offset addressing mode is when ann offset can be applied optionally to the
+# base address.
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -112
+ .cfi_offset 20, -104
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -96
+ .cfi_offset 22, -88
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -80
+ .cfi_offset 24, -72
+ stp x25, x26, [sp, 64]
+ .cfi_offset 25, -64
+ .cfi_offset 26, -56
+ str x27, [sp, 80]
+ .cfi_offset 27, -48
+# Stores non callee-saved register on stack.
+ str w0, [x29, 124]
+ str wzr, [x29, 120]
+ str w0, [x29, 120]
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.d b/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.d
new file mode 100644
index 00000000000..d69ba0dfa5a
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.d
@@ -0,0 +1,35 @@
+#as: --scfi=experimental -W
+#objdump: -Wf
+#name: Synthesize CFI for str insns 2
+#...
+Contents of the .eh_frame section:
+
+00000000 0+0010 00000000 CIE
+ Version: 1
+ Augmentation: "zR"
+ Code alignment factor: 4
+ Data alignment factor: -8
+ Return address column: 30
+ Augmentation data: 1b
+ DW_CFA_def_cfa: r31 \(sp\) ofs 0
+
+00000014 0+0028 00000018 FDE cie=00000000 pc=0+0000..0+001c
+ DW_CFA_advance_loc: 4 to 0+0004
+ DW_CFA_def_cfa_offset: 128
+ DW_CFA_offset: r29 \(x29\) at cfa-128
+ DW_CFA_offset: r30 \(x30\) at cfa-120
+ DW_CFA_advance_loc: 4 to 0+0008
+ DW_CFA_def_cfa_register: r29 \(x29\)
+ DW_CFA_advance_loc: 4 to 0+000c
+ DW_CFA_offset: r27 \(x27\) at cfa-128
+ DW_CFA_advance_loc: 4 to 0+0010
+ DW_CFA_def_cfa_register: r31 \(sp\)
+ DW_CFA_advance_loc: 4 to 0+0014
+ DW_CFA_restore: r29 \(x29\)
+ DW_CFA_def_cfa_offset: 120
+ DW_CFA_advance_loc: 4 to 0+0018
+ DW_CFA_restore: r30 \(x30\)
+ DW_CFA_def_cfa_offset: 0
+ DW_CFA_nop
+
+#pass
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.l b/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.l
new file mode 100644
index 00000000000..6ec24387b8c
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*7: Warning: SCFI ignores most user-specified CFI directives
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.s b/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.s
new file mode 100644
index 00000000000..1792697dffa
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-strp-2.s
@@ -0,0 +1,30 @@
+# Testcase for a variety of stp/str including a post-indexed store
+ .text
+ .align 2
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+ stp x29, x30, [sp, -128]!
+ .cfi_def_cfa_offset 128
+ .cfi_offset 29, -128
+ .cfi_offset 30, -120
+ mov x29, sp
+ .cfi_def_cfa_register 29
+# post-indexed store, a stack corrupting one which over-writes
+# x29! Only for testing purposes for now
+# This does not generate a .cfi_def_cfa_offset 208 because
+# CFA is REG_FP based
+ str x27, [sp], 80
+ .cfi_offset 27, -128
+ mov sp, x29
+ .cfi_def_cfa_register 31
+ ldr x29, [sp], 8
+ .cfi_restore 29
+ .cfi_def_cfa_offset 120
+ ldr x30, [sp], 120
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-unsupported-1.l b/gas/testsuite/gas/scfi/aarch64/scfi-unsupported-1.l
new file mode 100644
index 00000000000..de3ed86250b
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-unsupported-1.l
@@ -0,0 +1,4 @@
+.*Assembler messages:
+.*7: Warning: SCFI ignores most user-specified CFI directives
+.*9: Error: SCFI: unsupported stack manipulation pattern
+.*31: Error: SCFI: forward pass failed for func 'foo'
diff --git a/gas/testsuite/gas/scfi/aarch64/scfi-unsupported-1.s b/gas/testsuite/gas/scfi/aarch64/scfi-unsupported-1.s
new file mode 100644
index 00000000000..296aad890bf
--- /dev/null
+++ b/gas/testsuite/gas/scfi/aarch64/scfi-unsupported-1.s
@@ -0,0 +1,31 @@
+# Testcase where immediate used for stack allocation is a wide
+# one. Since SCFI does not currently have any data-flow
+# capabilities, this is currently not supported.
+ .global foo
+ .type foo, %function
+foo:
+ .cfi_startproc
+ mov x16, 4384
+ sub sp, sp, x16
+ .cfi_def_cfa_offset 4384
+ stp x29, x30, [sp]
+ .cfi_offset 29, -4384
+ .cfi_offset 30, -4376
+ mov x29, sp
+ str x0, [sp, 24]
+ str x1, [sp, 16]
+ add x0, sp, 4096
+ add x0, x0, 112
+ bl bar
+.L1:
+ str xzr, [sp, 4376]
+.L2:
+ ldp x29, x30, [sp]
+ mov x16, 4384
+ add sp, sp, x16
+ .cfi_restore 29
+ .cfi_restore 30
+ .cfi_def_cfa_offset 0
+ ret
+ .cfi_endproc
+ .size foo, .-foo
--
2.43.0
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