From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 6072E3858C5E for ; Mon, 3 Apr 2023 08:05:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6072E3858C5E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8626EFEC; Mon, 3 Apr 2023 01:06:43 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 983293F6C4; Mon, 3 Apr 2023 01:05:58 -0700 (PDT) From: Richard Sandiford To: Jan Beulich Mail-Followup-To: Jan Beulich ,binutils@sourceware.org, richard.sandiford@arm.com Cc: binutils@sourceware.org Subject: Re: [PATCH 00/31] aarch64: Add SME2 support References: <20230330102646.3327818-1-richard.sandiford@arm.com> Date: Mon, 03 Apr 2023 09:05:57 +0100 In-Reply-To: (Jan Beulich's message of "Sun, 2 Apr 2023 11:35:27 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-25.5 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Jan Beulich writes: > On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: >> Richard Sandiford (31): >> aarch64: Add +sme2 >> aarch64: Add a _10 suffix to FLD_imm3 >> aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array >> aarch64: Add support for vgx2 and vgx4 >> aarch64; Add support for vector offset ranges >> aarch64: Add support for predicate-as-counter registers >> aarch64: Add the SME2 MOVA instructions >> aarch64: Add the SME2 multivector LD1 and ST1 instructions > > Less than a 3rd of the patches in this series have made it to my mailbox > (and the list archives), so commenting on e.g. the one above is difficult. Yeah, they got held up in moderation due to the size. > Nevertheless - according to the documentation LD1x (scalar plus immediate, > consecutive registers) and their LDNT1x, ST1x, and STNT1x counterparts > are (unlike the strided forms) SVE2.1 insns, not SME2 ones (IOW it looks > as if the use of SME2_INSN() there is wrong, unless the documentation is > categorizing these incorrectly). They're both (but we haven't added SVE2p1 to binutils yet). E.g. see the pseudocode in: https://developer.arm.com/documentation/ddi0602/2022-12/SVE-Instructions/LD1B--scalar-plus-immediate--consecutive-registers---Contiguous-load-of-bytes-to-multiple-consecutive-vectors--immediate-index--?lang=en where the condition is: if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; Chronologically, SME2 predates SVE2p1. Thanks, Richard