Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[Jan Beulich]

>+      /* Check if slot 2 is NOP. Possible templates are MBB and BBB.
>+	 For BBB, slot 0 also has to be nop.b.  */
>+      if (!((template == 0x12				/* MBB */
>+	     && (s2 & 0x1e1f8000000LL) == 0x4000000000LL)
>+	    || (template == 0x16			/* BBB */
>+		&& (s0 & 0x1e1f8000000LL) == 0x4000000000LL
>+		&& (s2 & 0x1e1f8000000LL) == 0x4000000000LL)))
>+	return FALSE;
>...

I would think the code would become much better readable if the template values were symbolic (macros or enumeration values) and the nop checks would be hidden in macros.


>+      /* For BBB, we need to put nop.m in slot 0 and keep the original
>+	 predicate.  */
>+      t0 &= 0x7e0LL;

Why do you try to keep the predicate on a nop?

Jan

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Fri, May 13, 2005 at 09:40:46AM +0200, Jan Beulich wrote:
> >+      /* Check if slot 2 is NOP. Possible templates are MBB and BBB.
> >+	 For BBB, slot 0 also has to be nop.b.  */
> >+      if (!((template == 0x12				/* MBB */
> >+	     && (s2 & 0x1e1f8000000LL) == 0x4000000000LL)
> >+	    || (template == 0x16			/* BBB */
> >+		&& (s0 & 0x1e1f8000000LL) == 0x4000000000LL
> >+		&& (s2 & 0x1e1f8000000LL) == 0x4000000000LL)))
> >+	return FALSE;
> >...
> 
> I would think the code would become much better readable if the template values were symbolic (macros or enumeration values) and the nop checks would be hidden in macros.
> 

I will take a look.

> 
> >+      /* For BBB, we need to put nop.m in slot 0 and keep the original
> >+	 predicate.  */
> >+      t0 &= 0x7e0LL;
> 
> Why do you try to keep the predicate on a nop?

Because it was there before.



H.J.

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Fri, May 13, 2005 at 07:02:51AM -0700, H. J. Lu wrote:
> On Fri, May 13, 2005 at 09:40:46AM +0200, Jan Beulich wrote:
> > >+      /* Check if slot 2 is NOP. Possible templates are MBB and BBB.
> > >+	 For BBB, slot 0 also has to be nop.b.  */
> > >+      if (!((template == 0x12				/* MBB */
> > >+	     && (s2 & 0x1e1f8000000LL) == 0x4000000000LL)
> > >+	    || (template == 0x16			/* BBB */
> > >+		&& (s0 & 0x1e1f8000000LL) == 0x4000000000LL
> > >+		&& (s2 & 0x1e1f8000000LL) == 0x4000000000LL)))
> > >+	return FALSE;
> > >...
> > 
> > I would think the code would become much better readable if the template values were symbolic (macros or enumeration values) and the nop checks would be hidden in macros.
> > 
> 
> I will take a look.
> 

Here is the updated patch. I think it is quite readable with numbers
for template since there are only 5 bits.



H.J.
----
2005-05-13  H.J. Lu  <hongjiu.lu@intel.com>

	PR 834
	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
	(elfNN_ia64_relax_brl): Use it.

--- bfd/elfxx-ia64.c.br	2005-05-13 08:25:12.000000000 -0700
+++ bfd/elfxx-ia64.c	2005-05-13 09:06:07.000000000 -0700
@@ -681,6 +681,141 @@ bfd_elfNN_ia64_after_parse (int itanium)
   oor_branch_size = itanium ? sizeof (oor_ip) : sizeof (oor_brl);
 }
 
+#define BTYPE_SHIFT	6
+#define Y_SHIFT		26
+#define X6_SHIFT	27
+#define X4_SHIFT	27
+#define X3_SHIFT	33
+#define X2_SHIFT	31
+#define X_SHIFT		33
+#define OPCODE_SHIFT	37
+
+#define OPCODE_BITS	(0xfLL << OPCODE_SHIFT)
+#define X6_BITS		(0x3fLL << X6_SHIFT)
+#define X4_BITS		(0xfLL << X4_SHIFT)
+#define X3_BITS		(0x7LL << X3_SHIFT)
+#define X2_BITS		(0x3LL << X2_SHIFT)
+#define X_BITS		(0x1LL << X_SHIFT)
+#define Y_BITS		(0x1LL << Y_SHIFT)
+#define BTYPE_BITS	(0x7LL << BTYPE_SHIFT)
+#define PREDICATE_BITS	(0x3fLL)
+
+#define IS_NOP_B(i) \
+  (((i) & (OPCODE_BITS | X6_BITS)) == (2LL << OPCODE_SHIFT))
+#define IS_NOP_F(i) \
+  (((i) & (OPCODE_BITS | X_BITS | X6_BITS | Y_BITS)) \
+   == (0x1LL << X6_SHIFT))
+#define IS_NOP_I(i) \
+  (((i) & (OPCODE_BITS | X3_BITS | X6_BITS | Y_BITS)) \
+   == (0x1LL << X6_SHIFT))
+#define IS_NOP_M(i) \
+  (((i) & (OPCODE_BITS | X3_BITS | X2_BITS | X4_BITS | Y_BITS)) \
+   == (0x1LL << X4_SHIFT))
+#define IS_BR_COND(i) \
+  (((i) & (OPCODE_BITS | BTYPE_BITS)) == (0x4LL << OPCODE_SHIFT))
+#define IS_BR_CALL(i) \
+  (((i) & OPCODE_BITS) == (0x5LL << OPCODE_SHIFT))
+
+static bfd_boolean
+elfNN_ia64_relax_br (bfd_byte *contents, bfd_vma off)
+{
+  unsigned int template, mlx;
+  bfd_vma t0, t1, s0, s1, s2, br_code;
+  long br_slot;
+  bfd_byte *hit_addr;
+
+  hit_addr = (bfd_byte *) (contents + off);
+  br_slot = (long) hit_addr & 0x3;
+  hit_addr -= br_slot;
+  t0 = bfd_getl64 (hit_addr + 0);
+  t1 = bfd_getl64 (hit_addr + 8);
+
+  /* Check if we can turn br into brl.  A label is always at the start
+     of the bundle.  Even if there are predicates on NOPs, we still
+     perform this optimization.  */
+  template = t0 & 0x1e;
+  s0 = (t0 >> 5) & 0x1ffffffffffLL;
+  s1 = ((t0 >> 46) | (t1 << 18)) & 0x1ffffffffffLL;
+  s2 = (t1 >> 23) & 0x1ffffffffffLL;
+  switch (br_slot)
+    {
+    case 0:
+      /* Check if slot 1 and slot 2 are NOPs. Possible template is
+         BBB.  We only need to check nop.b.  */
+      if (!(IS_NOP_B (s1) && IS_NOP_B (s2)))
+	return FALSE;
+      br_code = s0;
+      break;
+    case 1:
+      /* Check if slot 2 is NOP. Possible templates are MBB and BBB.
+	 For BBB, slot 0 also has to be nop.b.  */
+      if (!((template == 0x12				/* MBB */
+	     && IS_NOP_B (s2))
+	    || (template == 0x16			/* BBB */
+		&& IS_NOP_B (s0)
+		&& IS_NOP_B (s2))))
+	return FALSE;
+      br_code = s1;
+      break;
+    case 2:
+      /* Check if slot 1 is NOP. Possible templates are MIB, MBB, BBB,
+	 MMB and MFB. For BBB, slot 0 also has to be nop.b.  */
+      if (!((template == 0x10				/* MIB */
+	     && IS_NOP_I (s1))
+	    || (template == 0x12			/* MBB */
+		&& IS_NOP_B (s1))
+	    || (template == 0x16			/* BBB */
+		&& IS_NOP_B (s0)
+		&& IS_NOP_B (s1))
+	    || (template == 0x18			/* MMB */
+		&& IS_NOP_M (s1))
+	    || (template == 0x1c			/* MFB */
+		&& IS_NOP_F (s1))))
+	return FALSE;
+      br_code = s2;
+      break;
+    default:
+      /* It should never happen.  */
+      abort ();
+    }
+  
+  /* We can turn br.cond/br.call into brl.cond/brl.call.  */
+  if (!(IS_BR_COND (br_code) || IS_BR_CALL (br_code)))
+    return FALSE;
+
+  /* Turn br into brl by setting bit 40.  */
+  br_code |= 0x1LL << 40;
+
+  /* Turn the old bundle into a MLX bundle with the same stop-bit
+     variety.  */
+  if (t0 & 0x1)
+    mlx = 0x5;
+  else
+    mlx = 0x4;
+
+  if (template == 0x16)
+    {
+      /* For BBB, we need to put nop.m in slot 0 and keep the original
+	 predicate.  */
+      t0 &= PREDICATE_BITS << 5;
+      t0 |= 0x1LL << (X4_SHIFT + 5);
+    }
+  else
+    {
+      /* Keep the original instruction in slot 0.  */
+      t0 &= 0x1ffffffffffLL << 5;
+    }
+
+  t0 |= mlx;
+
+  /* Put brl in slot 1.  */
+  t1 = br_code << 23;
+
+  bfd_putl64 (t0, hit_addr);
+  bfd_putl64 (t1, hit_addr + 8);
+  return TRUE;
+}
+
 static void
 elfNN_ia64_relax_brl (bfd_byte *contents, bfd_vma off)
 {
@@ -979,6 +1114,16 @@ elfNN_ia64_relax_section (abfd, sec, lin
 	    }
 	  else if (r_type == R_IA64_PCREL60B)
 	    continue;
+	  else if (elfNN_ia64_relax_br (contents, roff))
+	    {
+	      irel->r_info
+		= ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info),
+				R_IA64_PCREL60B);
+
+	      /* Make the relocation offset point to slot 1.  */
+	      irel->r_offset = (irel->r_offset & ~((bfd_vma) 0x3)) + 1;
+	      continue;
+	    }
 
 	  /* We can't put a trampoline in a .init/.fini section. Issue
 	     an error.  */

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[Richard Henderson]

On Fri, May 13, 2005 at 07:02:51AM -0700, H. J. Lu wrote:
> Because it was there before.

It's a nop.  What are you hoping to achieve?


r~

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Fri, May 13, 2005 at 11:15:01AM -0700, Richard Henderson wrote:
> On Fri, May 13, 2005 at 07:02:51AM -0700, H. J. Lu wrote:
> > Because it was there before.
> 
> It's a nop.  What are you hoping to achieve?
> 

I am not trying to second guess what the programmer wants. If she/he
puts a predicate on a nop, I will leave it there. If we really want
to strip predicate on nop, the assembler should do it, not the linker.


H.J.

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[Richard Henderson]

On Fri, May 13, 2005 at 09:19:54AM -0700, H. J. Lu wrote:
> 	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
> 	(elfNN_ia64_relax_brl): Use it.

This is ok, but I think you really shouldn't keep the nop predicate.
You claimed you didn't want to change the user's code; what do you
think you're doing here?!?  Both stances make no sense.


r~

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Tue, May 17, 2005 at 10:18:25AM -0700, Richard Henderson wrote:
> On Tue, May 17, 2005 at 08:53:13AM -0700, H. J. Lu wrote:
> > > I guess the most reasonable thing to do here is to keep the predicate if the slot wasn't modified (i.e. was a nop before), but to strip it if the branch was actually moved out of that slot (and with it the predicate).
> > > 
> > 
> > That makes sense. Here is the patch.
> 
> Ok to both patches.
> 
> 

I checked them in. I also checked in

http://sourceware.org/ml/binutils/2005-05/msg00445.html

as an obvious fix since bfd_vma for ia64 is 8 byte.

Thanks.


H.J.

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[Richard Henderson]

On Tue, May 17, 2005 at 08:53:13AM -0700, H. J. Lu wrote:
> > I guess the most reasonable thing to do here is to keep the predicate if the slot wasn't modified (i.e. was a nop before), but to strip it if the branch was actually moved out of that slot (and with it the predicate).
> > 
> 
> That makes sense. Here is the patch.

Ok to both patches.


r~

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Tue, May 17, 2005 at 11:38:41AM +0200, Jan Beulich wrote:
> >>> Richard Henderson <rth@redhat.com> 16.05.05 19:43:45 >>>
> >On Fri, May 13, 2005 at 09:19:54AM -0700, H. J. Lu wrote:
> >> 	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
> >> 	(elfNN_ia64_relax_brl): Use it.
> >
> >This is ok, but I think you really shouldn't keep the nop predicate.
> >You claimed you didn't want to change the user's code; what do you
> >think you're doing here?!?  Both stances make no sense.
> 
> I guess the most reasonable thing to do here is to keep the predicate if the slot wasn't modified (i.e. was a nop before), but to strip it if the branch was actually moved out of that slot (and with it the predicate).
> 

That makes sense. Here is the patch.


H.J.
----
2005-05-17  H.J. Lu  <hongjiu.lu@intel.com>

	* elfxx-ia64.c (elfNN_ia64_relax_br): Keep the original
	predicate on slot 0 only if slot 0 isn't br.

--- bfd/elfxx-ia64.c.nop	2005-05-17 08:33:53.000000000 -0700
+++ bfd/elfxx-ia64.c	2005-05-17 08:46:27.000000000 -0700
@@ -795,9 +795,12 @@ elfNN_ia64_relax_br (bfd_byte *contents,
 
   if (template == 0x16)
     {
-      /* For BBB, we need to put nop.m in slot 0 and keep the original
-	 predicate.  */
-      t0 &= PREDICATE_BITS << 5;
+      /* For BBB, we need to put nop.m in slot 0.  We keep the original
+	 predicate only if slot 0 isn't br.  */
+      if (br_slot == 0)
+	t0 = 0LL;
+      else
+	t0 &= PREDICATE_BITS << 5;
       t0 |= 0x1LL << (X4_SHIFT + 5);
     }
   else

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[Jan Beulich]

>>> Richard Henderson <rth@redhat.com> 16.05.05 19:43:45 >>>
>On Fri, May 13, 2005 at 09:19:54AM -0700, H. J. Lu wrote:
>> 	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
>> 	(elfNN_ia64_relax_brl): Use it.
>
>This is ok, but I think you really shouldn't keep the nop predicate.
>You claimed you didn't want to change the user's code; what do you
>think you're doing here?!?  Both stances make no sense.

I guess the most reasonable thing to do here is to keep the predicate if the slot wasn't modified (i.e. was a nop before), but to strip it if the branch was actually moved out of that slot (and with it the predicate).

Jan

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Thu, May 12, 2005 at 05:58:18PM -0700, H. J. Lu wrote:
> On Thu, May 12, 2005 at 02:36:33PM -0700, Richard Henderson wrote:
> > On Thu, May 12, 2005 at 01:05:22PM -0700, H. J. Lu wrote:
> > > > I really wish you'd extract the three insns independently, rather
> > > > than extracting 3 words and using quite so many arbitrary masks.
> > > > It's not like we don't have a 64-bit type available.
> > > > 
> > > 
> > > I was thinking to use long long since long may be 32bit. But I am not
> > > sure if all compilers support it. I guess I can use
> > > 
> > > #if BFD_HOST_LONG_LONG
> > > long long ..
> > > #else
> > >   return FALSE;
> > > #endif
> > 
> > We already assume a 64-bit type, for instance in elfNN_ia64_install_value.
> > I see that elf32-ia64.lo is in BFD32_BACKENDS; that's probably a mistake.
> > 
> > I see no reason to complicate things by doing anything other than assuming
> > a 64-bit type is available when compiling for ia64.  Every reasonable
> > compiler does support such a type.
> > 
> > 
> 
> Here is the updated patch.
> 
> 

Added 40bit masks for instructions.


H.J.
---
2005-05-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR 834
	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
	(elfNN_ia64_relax_brl): Use it.

--- bfd/elfxx-ia64.c.brl	2005-05-07 06:58:12.000000000 -0700
+++ bfd/elfxx-ia64.c	2005-05-12 17:50:36.000000000 -0700
@@ -681,6 +681,108 @@ bfd_elfNN_ia64_after_parse (int itanium)
   oor_branch_size = itanium ? sizeof (oor_ip) : sizeof (oor_brl);
 }
 
+static bfd_boolean
+elfNN_ia64_relax_br (bfd_byte *contents, bfd_vma off)
+{
+  unsigned int template, mlx;
+  bfd_vma t0, t1, s0, s1, s2, br_code;
+  long br_slot;
+  bfd_byte *hit_addr;
+
+  hit_addr = (bfd_byte *) (contents + off);
+  br_slot = (long) hit_addr & 0x3;
+  hit_addr -= br_slot;
+  t0 = bfd_getl64 (hit_addr + 0);
+  t1 = bfd_getl64 (hit_addr + 8);
+
+  /* Check if we can turn br into brl.  A label is always at the start
+     of the bundle.  Even if there are predicates on NOPs, we still
+     perform this optimization.  */
+  template = t0 & 0x1e;
+  s0 = (t0 >> 5) & 0x1ffffffffffLL;
+  s1 = ((t0 >> 46) | (t1 << 18)) & 0x1ffffffffffLL;
+  s2 = (t1 >> 23) & 0x1ffffffffffLL;
+  switch (br_slot)
+    {
+    case 0:
+      /* Check if slot 1 and slot 2 are NOPs. Possible template is
+         BBB.  We only need to check nop.b.  */
+      if (!((s1 & 0x1e1f8000000LL) == 0x4000000000LL
+	    && (s2 & 0x1e1f8000000LL) == 0x4000000000LL))
+	return FALSE;
+      br_code = s0;
+      break;
+    case 1:
+      /* Check if slot 2 is NOP. Possible templates are MBB and BBB.
+	 For BBB, slot 0 also has to be nop.b.  */
+      if (!((template == 0x12				/* MBB */
+	     && (s2 & 0x1e1f8000000LL) == 0x4000000000LL)
+	    || (template == 0x16			/* BBB */
+		&& (s0 & 0x1e1f8000000LL) == 0x4000000000LL
+		&& (s2 & 0x1e1f8000000LL) == 0x4000000000LL)))
+	return FALSE;
+      br_code = s1;
+      break;
+    case 2:
+      /* Check if slot 1 is NOP. Possible templates are MIB, MBB, BBB,
+	 MMB and MFB. For BBB, slot 0 also has to be nop.b.  */
+      if (!((template == 0x10				/* MIB */
+	     && (s1 & 0x1effc000000LL) == 0x8000000LL)
+	    || (template == 0x12			/* MBB */
+		&& (s1 & 0x1e1f8000000LL) == 0x4000000000LL)
+	    || (template == 0x16			/* BBB */
+		&& (s0 & 0x1e1f8000000LL) == 0x4000000000LL
+		&& (s1 & 0x1e1f8000000LL) == 0x4000000000LL)
+	    || (template == 0x18			/* MMB */
+		&& (s1 & 0x1effc000000LL) == 0x8000000LL)
+	    || (template == 0x1c			/* MFB */
+		&& (s1 & 0x1e3fc000000LL) == 0x8000000LL)))
+	return FALSE;
+      br_code = s2;
+      break;
+    default:
+      /* It should never happen.  */
+      abort ();
+    }
+  
+  /* We can turn br.cond/br.call into brl.cond/brl.call.  */
+  if (!(((br_code & 0x1e0000001c0LL) == 0x8000000000LL)
+	|| (br_code & 0x1e000000000LL) == 0xa000000000LL))
+    return FALSE;
+
+  /* Turn br into brl by setting bit 40.  */
+  br_code |= 0x10000000000LL;
+
+  /* Turn the old bundle into a MLX bundle with the same stop-bit
+     variety.  */
+  if (t0 & 0x1)
+    mlx = 0x5;
+  else
+    mlx = 0x4;
+
+  if (template == 0x16)
+    {
+      /* For BBB, we need to put nop.m in slot 0 and keep the original
+	 predicate.  */
+      t0 &= 0x7e0LL;
+      t0 |= 0x100000000LL;
+    }
+  else
+    {
+      /* Keep the original instruction in slot 0.  */
+      t0 &= 0x3fffffffffe0LL;
+    }
+
+  t0 |= mlx;
+
+  /* Put brl in slot 1.  */
+  t1 = br_code << 23;
+
+  bfd_putl64 (t0, hit_addr);
+  bfd_putl64 (t1, hit_addr + 8);
+  return TRUE;
+}
+
 static void
 elfNN_ia64_relax_brl (bfd_byte *contents, bfd_vma off)
 {
@@ -985,6 +1087,16 @@ elfNN_ia64_relax_section (abfd, sec, lin
 	    }
 	  else if (r_type == R_IA64_PCREL60B)
 	    continue;
+	  else if (elfNN_ia64_relax_br (contents, roff))
+	    {
+	      irel->r_info
+		= ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info),
+				R_IA64_PCREL60B);
+
+	      /* Make the relocation offset point to slot 1.  */
+	      irel->r_offset = (irel->r_offset & ~((bfd_vma) 0x3)) + 1;
+	      continue;
+	    }
 
 	  /* We can't put a trampoline in a .init/.fini section. Issue
 	     an error.  */

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Thu, May 12, 2005 at 02:36:33PM -0700, Richard Henderson wrote:
> On Thu, May 12, 2005 at 01:05:22PM -0700, H. J. Lu wrote:
> > > I really wish you'd extract the three insns independently, rather
> > > than extracting 3 words and using quite so many arbitrary masks.
> > > It's not like we don't have a 64-bit type available.
> > > 
> > 
> > I was thinking to use long long since long may be 32bit. But I am not
> > sure if all compilers support it. I guess I can use
> > 
> > #if BFD_HOST_LONG_LONG
> > long long ..
> > #else
> >   return FALSE;
> > #endif
> 
> We already assume a 64-bit type, for instance in elfNN_ia64_install_value.
> I see that elf32-ia64.lo is in BFD32_BACKENDS; that's probably a mistake.
> 
> I see no reason to complicate things by doing anything other than assuming
> a 64-bit type is available when compiling for ia64.  Every reasonable
> compiler does support such a type.
> 
> 

Here is the updated patch.


H.J.
----
2005-05-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR 834
	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
	(elfNN_ia64_relax_brl): Use it.

--- bfd/elfxx-ia64.c.brl	2005-05-07 06:58:12.000000000 -0700
+++ bfd/elfxx-ia64.c	2005-05-12 17:50:36.000000000 -0700
@@ -681,6 +681,108 @@ bfd_elfNN_ia64_after_parse (int itanium)
   oor_branch_size = itanium ? sizeof (oor_ip) : sizeof (oor_brl);
 }
 
+static bfd_boolean
+elfNN_ia64_relax_br (bfd_byte *contents, bfd_vma off)
+{
+  unsigned int template, mlx;
+  bfd_vma t0, t1, s0, s1, s2, br_code;
+  long br_slot;
+  bfd_byte *hit_addr;
+
+  hit_addr = (bfd_byte *) (contents + off);
+  br_slot = (long) hit_addr & 0x3;
+  hit_addr -= br_slot;
+  t0 = bfd_getl64 (hit_addr + 0);
+  t1 = bfd_getl64 (hit_addr + 8);
+
+  /* Check if we can turn br into brl.  A label is always at the start
+     of the bundle.  Even if there are predicates on NOPs, we still
+     perform this optimization.  */
+  template = t0 & 0x1e;
+  s0 = t0 >> 5;
+  s1 = (t0 >> 46 | t1 << 18) & 0x1ffffffffffLL;
+  s2 = t1 >> 23;
+  switch (br_slot)
+    {
+    case 0:
+      /* Check if slot 1 and slot 2 are NOPs. Possible template is
+         BBB.  We only need to check nop.b.  */
+      if (!((s1 & 0x1e1f8000000LL) == 0x4000000000LL
+	    && (s2 & 0x1e1f8000000LL) == 0x4000000000LL))
+	return FALSE;
+      br_code = s0;
+      break;
+    case 1:
+      /* Check if slot 2 is NOP. Possible templates are MBB and BBB.
+	 For BBB, slot 0 also has to be nop.b.  */
+      if (!((template == 0x12				/* MBB */
+	     && (s2 & 0x1e1f8000000LL) == 0x4000000000LL)
+	    || (template == 0x16			/* BBB */
+		&& (s0 & 0x1e1f8000000LL) == 0x4000000000LL
+		&& (s2 & 0x1e1f8000000LL) == 0x4000000000LL)))
+	return FALSE;
+      br_code = s1;
+      break;
+    case 2:
+      /* Check if slot 1 is NOP. Possible templates are MIB, MBB, BBB,
+	 MMB and MFB. For BBB, slot 0 also has to be nop.b.  */
+      if (!((template == 0x10				/* MIB */
+	     && (s1 & 0x1effc000000LL) == 0x8000000LL)
+	    || (template == 0x12			/* MBB */
+		&& (s1 & 0x1e1f8000000LL) == 0x4000000000LL)
+	    || (template == 0x16			/* BBB */
+		&& (s0 & 0x1e1f8000000LL) == 0x4000000000LL
+		&& (s1 & 0x1e1f8000000LL) == 0x4000000000LL)
+	    || (template == 0x18			/* MMB */
+		&& (s1 & 0x1effc000000LL) == 0x8000000LL)
+	    || (template == 0x1c			/* MFB */
+		&& (s1 & 0x1e3fc000000LL) == 0x8000000LL)))
+	return FALSE;
+      br_code = s2;
+      break;
+    default:
+      /* It should never happen.  */
+      abort ();
+    }
+  
+  /* We can turn br.cond/br.call into brl.cond/brl.call.  */
+  if (!(((br_code & 0x1e0000001c0LL) == 0x8000000000LL)
+	|| (br_code & 0x1e000000000LL) == 0xa000000000LL))
+    return FALSE;
+
+  /* Turn br into brl by setting bit 40.  */
+  br_code |= 0x10000000000LL;
+
+  /* Turn the old bundle into a MLX bundle with the same stop-bit
+     variety.  */
+  if (t0 & 0x1)
+    mlx = 0x5;
+  else
+    mlx = 0x4;
+
+  if (template == 0x16)
+    {
+      /* For BBB, we need to put nop.m in slot 0 and keep the original
+	 predicate.  */
+      t0 &= 0x7e0;
+      t0 |= 0x100000000LL;
+    }
+  else
+    {
+      /* Keep the original instruction in slot 0.  */
+      t0 &= 0x3fffffffffe0LL;
+    }
+
+  t0 |= mlx;
+
+  /* Put brl in slot 1.  */
+  t1 = br_code << 23;
+
+  bfd_putl64 (t0, hit_addr);
+  bfd_putl64 (t1, hit_addr + 8);
+  return TRUE;
+}
+
 static void
 elfNN_ia64_relax_brl (bfd_byte *contents, bfd_vma off)
 {
@@ -985,6 +1087,16 @@ elfNN_ia64_relax_section (abfd, sec, lin
 	    }
 	  else if (r_type == R_IA64_PCREL60B)
 	    continue;
+	  else if (elfNN_ia64_relax_br (contents, roff))
+	    {
+	      irel->r_info
+		= ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info),
+				R_IA64_PCREL60B);
+
+	      /* Make the relocation offset point to slot 1.  */
+	      irel->r_offset = (irel->r_offset & ~((bfd_vma) 0x3)) + 1;
+	      continue;
+	    }
 
 	  /* We can't put a trampoline in a .init/.fini section. Issue
 	     an error.  */

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Thu, May 12, 2005 at 04:31:24PM -0700, James E Wilson wrote:
> On Thu, 2005-05-12 at 16:08, Richard Henderson wrote:
> > On Thu, May 12, 2005 at 03:35:58PM -0700, James E Wilson wrote:
> > > HJ has mentioned that he would like to split elfxx-ia64.c into separate
> > > elf32-ia64.c and elf64-ia64.c files.
> > To what purpose?
> 
> I don't know the details.  I wasn't going to worry about it until I saw
> a patch.  I assume it is part of his work to try to get the ILP32 linker
> working.  Perhaps HJ can comment on this.

The code is duplicated when both ELF32 and ELF64 are configured.
Also it isn't easy to debug it. You need to handle both elfxx-ia64.c
and elf64-ia64.c. But it seems to too much effort to add elf32-ia64
add elf64-ia64.c. I gave it up.


H.J.

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[James E Wilson]

On Thu, 2005-05-12 at 16:08, Richard Henderson wrote:
> On Thu, May 12, 2005 at 03:35:58PM -0700, James E Wilson wrote:
> > HJ has mentioned that he would like to split elfxx-ia64.c into separate
> > elf32-ia64.c and elf64-ia64.c files.
> To what purpose?

I don't know the details.  I wasn't going to worry about it until I saw
a patch.  I assume it is part of his work to try to get the ILP32 linker
working.  Perhaps HJ can comment on this.
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[Richard Henderson]

On Thu, May 12, 2005 at 03:35:58PM -0700, James E Wilson wrote:
> I fixed that mistake about 6 weeks ago.

Oops.  Clearly the copy of the tree I looked at is out of date.

> HJ has mentioned that he would like to split elfxx-ia64.c into separate
> elf32-ia64.c and elf64-ia64.c files.

To what purpose?


r~

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[James E Wilson]

On Thu, 2005-05-12 at 14:36, Richard Henderson wrote:
> We already assume a 64-bit type, for instance in elfNN_ia64_install_value.
> I see that elf32-ia64.lo is in BFD32_BACKENDS; that's probably a mistake.

I fixed that mistake about 6 weeks ago.

> I see no reason to complicate things by doing anything other than assuming
> a 64-bit type is available when compiling for ia64.  Every reasonable
> compiler does support such a type.

HJ has mentioned that he would like to split elfxx-ia64.c into separate
elf32-ia64.c and elf64-ia64.c files.  If this is done, then the
elf32-ia64.c file probably should not require long long support. 
Otherwise, I agree with you.  All IA-64 machines are 64-bit machines,
and there should never be any need to avoid use of 64-bit types in the
current elfxx-ia64.c file, or the proposed elf64-ia64.c.

There is some 32-bit code in elfxx-ia64.c, but that was a mistake, and
was done before elf32-ia64.c was removed from BFD32_BACKENDS.
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[Richard Henderson]

On Thu, May 12, 2005 at 01:05:22PM -0700, H. J. Lu wrote:
> > I really wish you'd extract the three insns independently, rather
> > than extracting 3 words and using quite so many arbitrary masks.
> > It's not like we don't have a 64-bit type available.
> > 
> 
> I was thinking to use long long since long may be 32bit. But I am not
> sure if all compilers support it. I guess I can use
> 
> #if BFD_HOST_LONG_LONG
> long long ..
> #else
>   return FALSE;
> #endif

We already assume a 64-bit type, for instance in elfNN_ia64_install_value.
I see that elf32-ia64.lo is in BFD32_BACKENDS; that's probably a mistake.

I see no reason to complicate things by doing anything other than assuming
a 64-bit type is available when compiling for ia64.  Every reasonable
compiler does support such a type.



r~

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Thu, May 12, 2005 at 12:56:02PM -0700, Richard Henderson wrote:
> On Thu, May 12, 2005 at 09:37:32AM -0700, H. J. Lu wrote:
> > 	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
> > 	(elfNN_ia64_relax_brl): Use it.
> 
> I really wish you'd extract the three insns independently, rather
> than extracting 3 words and using quite so many arbitrary masks.
> It's not like we don't have a 64-bit type available.
> 

I was thinking to use long long since long may be 32bit. But I am not
sure if all compilers support it. I guess I can use

#if BFD_HOST_LONG_LONG
long long ..
#else
  return FALSE;
#endif


H.J.

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[Richard Henderson]

On Thu, May 12, 2005 at 09:37:32AM -0700, H. J. Lu wrote:
> 	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
> 	(elfNN_ia64_relax_brl): Use it.

I really wish you'd extract the three insns independently, rather
than extracting 3 words and using quite so many arbitrary masks.
It's not like we don't have a 64-bit type available.


r~

Re: PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

On Thu, May 12, 2005 at 09:11:41AM -0700, H. J. Lu wrote:
> This patch will try to turn br into brl when it is possible.
> 

Slot 0 has to be NOP only for BBB. Here is an update.


H.J.
----
2005-05-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR 834
	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
	(elfNN_ia64_relax_brl): Use it.

--- bfd/elfxx-ia64.c.brl	2005-05-07 06:58:12.000000000 -0700
+++ bfd/elfxx-ia64.c	2005-05-12 09:34:52.000000000 -0700
@@ -681,6 +681,114 @@ bfd_elfNN_ia64_after_parse (int itanium)
   oor_branch_size = itanium ? sizeof (oor_ip) : sizeof (oor_brl);
 }
 
+static bfd_boolean
+elfNN_ia64_relax_br (bfd_byte *contents, bfd_vma off)
+{
+  unsigned int template, t0, t1, t2, t3, br_code1, br_code2, mlx;
+  long br_slot;
+  bfd_byte *hit_addr;
+
+  hit_addr = (bfd_byte *) (contents + off);
+  br_slot = (long) hit_addr & 0x3;
+  hit_addr -= br_slot;
+  t0 = bfd_getl32 (hit_addr + 0);
+  t1 = bfd_getl32 (hit_addr + 4);
+  t2 = bfd_getl32 (hit_addr + 8);
+  t3 = bfd_getl32 (hit_addr + 12);
+
+  /* Check if we can turn br into brl.  A label is always at the start
+     of the bundle.  Even if there are predicates on NOPs, we still
+     perform this optimization.  */
+  template = t0 & 0x1e;
+  switch (br_slot)
+    {
+    case 0:
+      /* Check if slot 1 and slot 2 are NOPs. Possible template is
+         BBB.  We only need to check nop.b.  */
+      if (!((t2 & 0x787e00) == 0x100000
+	    && (t3 & 0xf0fc0000) == 0x20000000))
+	return FALSE;
+      br_code1 = (t0 & 0xffffffe0) >> 5 | (t1 & 0x1f) << 27;
+      br_code2 = (t1 & 0x3fe0) >> 5;
+      break;
+    case 1:
+      /* Check if slot 2 is NOP. Possible templates are MBB and BBB.
+	 For BBB, slot 0 also has to be nop.b.  */
+      if (!((template == 0x12				/* MBB */
+	     && (t3 & 0xf0fc0000) == 0x20000000)
+	    || (template == 0x16			/* BBB */
+		&& (t1 & 0x3c3f) == 0x800
+		&& (t3 & 0xf0fc0000) == 0x20000000)))
+	return FALSE;
+      br_code1 = (t1 & 0xffffc000) >> 14 | (t2 & 0x3fff) << 18;
+      br_code2 = (t2 & 0x7fc000) >> 14;
+      break;
+    case 2:
+      /* Check if slot 1 is NOP. Possible templates are MIB, MBB, BBB,
+	 MMB and MFB. For BBB, slot 0 also has to be nop.b.  */
+      if (!((template == 0x10				/* MIB */
+	     && (t2 & 0x7bff00) == 0x200)
+	    || (template == 0x12			/* MBB */
+		&& (t2 & 0x787e00) == 0x100000)
+	    || (template == 0x16			/* BBB */
+		&& (t1 & 0x3c3f) == 0x800
+		&& (t2 & 0x787e00) == 0x100000)
+	    || (template == 0x18			/* MMB */
+		&& (t2 & 0x7bff00) == 0x200)
+	    || (template == 0x1c			/* MFB */
+		&& (t2 & 0x78ff00) == 0x200)))
+	return FALSE;
+      br_code1 = (t2 & 0xff800000) >> 23 | (t3 & 0x7fffff) << 9;
+      br_code2 = (t3 & 0xff800000) >> 23;
+      break;
+    default:
+      /* It should never happen.  */
+      abort ();
+    }
+  
+  /* Check if we can turn br into brl.  */
+  if (!(((br_code2 & 0x1e0) == 0xa0)
+	|| ((br_code1 & 0x1c0) == 0 && (br_code2 & 0x1e0) == 0x80)))
+    return FALSE;
+
+  /* Turn br into brl by setting bit 40.  */
+  br_code2 |= 0x100;
+
+  /* Turn the old bundle into a MLX bundle with the same stop-bit
+     variety.  */
+  if (t0 & 0x1)
+    mlx = 0x5;
+  else
+    mlx = 0x4;
+
+  if (template == 0x16)
+    {
+      /* For BBB, we need to put nop.m in slot 0 and keep the original
+	 predicate.  */
+      t0 &= 0x7e0;
+      t1 &= ~0x3fff;
+      t1 |= 0x1;
+    }
+  else
+    {
+      /* Keep the original instruction in slot 0.  */
+      t0 &= 0xffffffe0;
+      t1 &= 0x3fff;
+    }
+
+  t0 |= mlx;
+
+  /* Put brl in slot 1.  */
+  t2 = br_code1 << 23;
+  t3 = (br_code1 >> 9) | (br_code2 << 23);
+
+  bfd_putl32 (t0, hit_addr);
+  bfd_putl32 (t1, hit_addr + 4);
+  bfd_putl32 (t2, hit_addr + 8);
+  bfd_putl32 (t3, hit_addr + 12);
+  return TRUE;
+}
+
 static void
 elfNN_ia64_relax_brl (bfd_byte *contents, bfd_vma off)
 {
@@ -985,6 +1093,16 @@ elfNN_ia64_relax_section (abfd, sec, lin
 	    }
 	  else if (r_type == R_IA64_PCREL60B)
 	    continue;
+	  else if (elfNN_ia64_relax_br (contents, roff))
+	    {
+	      irel->r_info
+		= ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info),
+				R_IA64_PCREL60B);
+
+	      /* Make the relocation offset point to slot 1.  */
+	      irel->r_offset = (irel->r_offset & ~((bfd_vma) 0x3)) + 1;
+	      continue;
+	    }
 
 	  /* We can't put a trampoline in a .init/.fini section. Issue
 	     an error.  */

PATCH: PR 834: IA64: Change br to brl for "far" branches when possible

[H. J. Lu]

This patch will try to turn br into brl when it is possible.


H.J.
-----
2005-05-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR 834
	* elfxx-ia64.c (elfNN_ia64_relax_br): New.
	(elfNN_ia64_relax_brl): Use it.

--- bfd/elfxx-ia64.c.brl	2005-05-07 06:58:12.000000000 -0700
+++ bfd/elfxx-ia64.c	2005-05-12 09:03:18.000000000 -0700
@@ -681,6 +681,113 @@ bfd_elfNN_ia64_after_parse (int itanium)
   oor_branch_size = itanium ? sizeof (oor_ip) : sizeof (oor_brl);
 }
 
+static bfd_boolean
+elfNN_ia64_relax_br (bfd_byte *contents, bfd_vma off)
+{
+  unsigned int template, t0, t1, t2, t3, br_code1, br_code2;
+  long br_slot;
+  bfd_byte *hit_addr;
+
+  hit_addr = (bfd_byte *) (contents + off);
+  br_slot = (long) hit_addr & 0x3;
+  hit_addr -= br_slot;
+  t0 = bfd_getl32 (hit_addr + 0);
+  t1 = bfd_getl32 (hit_addr + 4);
+  t2 = bfd_getl32 (hit_addr + 8);
+  t3 = bfd_getl32 (hit_addr + 12);
+
+  /* Check if we can turn br into brl.  A label is always at the start
+     of the bundle.  Even if there are predicates on NOPs, we still
+     perform this optimization.  */
+  template = t0 & 0x1e;
+  switch (br_slot)
+    {
+    case 0:
+      /* Check if slot 1 and slot 2 are NOPs. Possible template is
+         BBB.  We only need to check nop.b.  */
+      if (!((t2 & 0x787e00) == 0x100000
+	    && (t3 & 0xf0fc0000) == 0x20000000))
+	return FALSE;
+      br_code1 = (t0 & 0xffffffe0) >> 5 | (t1 & 0x1f) << 27;
+      br_code2 = (t1 & 0x3fe0) >> 5;
+      break;
+    case 1:
+      /* Check if slot 0 and slot 2 are NOPs. Possible templates are
+         MBB and BBB.  */
+      if (!((template == 0x12				/* MBB */
+	     && (t0 & 0x80000000) == 0x0
+	     && (t1 & 0x37ff) == 0x1
+	     && (t3 & 0xf0fc0000) == 0x20000000)
+	    || (template == 0x16			/*  BBB */
+		&& (t1 & 0x3c3f) == 0x800
+		&& (t3 & 0xf0fc0000) == 0x20000000)))
+	return FALSE;
+      br_code1 = (t1 & 0xffffc000) >> 14 | (t2 & 0x3fff) << 18;
+      br_code2 = (t2 & 0x7fc000) >> 14;
+      break;
+    case 2:
+      /* Check if slot 0 and slot 1 are NOPs. Possible templates are
+	 MIB, MBB, BBB, MMB and MFB.  */
+      if (!((template == 0x10				/* MIB */
+	     && (t0 & 0x80000000) == 0x0
+	     && (t1 & 0x37ff) == 0x1
+	     && (t2 & 0x7bff00) == 0x200)
+	    || (template == 0x12			/* MBB */
+		&& (t0 & 0x80000000) == 0x0
+		&& (t1 & 0x37ff) == 0x1
+		&& (t2 & 0x787e00) == 0x100000)
+	    || (template == 0x16			/* BBB */
+		&& (t1 & 0x3c3f) == 0x800
+		&& (t2 & 0x787e00) == 0x100000)
+	    || (template == 0x18			/* MMB */
+		&& (t0 & 0x80000000) == 0x0
+		&& (t1 & 0x37ff) == 0x1
+		&& (t2 & 0x7bff00) == 0x200)
+	    || (template == 0x1c			/* MFB */
+		&& (t0 & 0x80000000) == 0x0
+		&& (t1 & 0x37ff) == 0x1
+		&& (t2 & 0x78ff00) == 0x200)))
+	return FALSE;
+      br_code1 = (t2 & 0xff800000) >> 23 | (t3 & 0x7fffff) << 9;
+      br_code2 = (t3 & 0xff800000) >> 23;
+      break;
+    default:
+      /* It should never happen.  */
+      abort ();
+    }
+  
+  /* Check if we can turn br into brl.  */
+  if (!(((br_code2 & 0x1e0) == 0xa0)
+	|| ((br_code1 & 0x1c0) == 0 && (br_code2 & 0x1e0) == 0x80)))
+    return FALSE;
+
+  /* Turn br into brl by setting bit 40.  */
+  br_code2 |= 0x100;
+
+  /* Turn the old bundle into a MLX bundle with the same stop-bit
+     variety.  */
+  if (t0 & 0x1)
+    template = 0x5;
+  else
+    template = 0x4;
+
+  /* Put nop.m in slot 0 and keep the original predicate. */
+  t0 &= 0x7e0;
+  t0 |= template;
+  t1 &= ~0x3fff;
+  t1 |= 0x1;
+
+  /* Put brl in slot 1.  */
+  t2 = br_code1 << 23;
+  t3 = (br_code1 >> 9) | (br_code2 << 23);
+
+  bfd_putl32 (t0, hit_addr);
+  bfd_putl32 (t1, hit_addr + 4);
+  bfd_putl32 (t2, hit_addr + 8);
+  bfd_putl32 (t3, hit_addr + 12);
+  return TRUE;
+}
+
 static void
 elfNN_ia64_relax_brl (bfd_byte *contents, bfd_vma off)
 {
@@ -985,6 +1092,16 @@ elfNN_ia64_relax_section (abfd, sec, lin
 	    }
 	  else if (r_type == R_IA64_PCREL60B)
 	    continue;
+	  else if (elfNN_ia64_relax_br (contents, roff))
+	    {
+	      irel->r_info
+		= ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info),
+				R_IA64_PCREL60B);
+
+	      /* Make the relocation offset point to slot 1.  */
+	      irel->r_offset = (irel->r_offset & ~((bfd_vma) 0x3)) + 1;
+	      continue;
+	    }
 
 	  /* We can't put a trampoline in a .init/.fini section. Issue
 	     an error.  */