<VR4133 Problem> ===========================================================

[Restriction 15] CPU (4)

When "mult/div/macc" instruction (NOTE1) follows "mflo/mfhi" instruction, 
the "mult/div/macc" result is mistaken for "mflo/mfhi" one in the following
conditions.

NOTE1 MULT/MULTU/DMULT/DMULTU, DIV/DIVU/DDIV/DDIVU, 
      MACC/DMACC, MACCU/DMACCU, MACCHI/DMACCHI, 
      MACCHIU/DMACCHIU, MACCS/DMACCS, MACCUS/DMACCUS, 
      MACCHIS/DMACCHIS, MACCHIUS/DMACCHIUS

  Conditions:
       - The instruction steps are less than 4 between "mflo/mfhi" and 
         "mult/div/macc".
       - The "mflo/mfhi" execution is stalled or held during executing
         the load/store instructions located in right before the mflo/mfhi
         (within 2 instructions).


<Relevant instruction sequence>
The following instruction sequence causes the problem.
---------------------------
all load/store instruction
 (0 or 1 instruction)
mflo/mfhi
 (3 or less instructions)
mult/div/macc NOTE1, NOTE2

NOTE2 The following case is the exception and doesn't cause
      the problem.
   - The case which the result of mflo/mfhi is used for 
     the source of mult/div/macc
---------------------------


<Possible work-arounds>

Either one of the following four can be the work-around.

(1) Place 4 or more instructions between mflo/mfhi and mult/div/macc.

ex.
　　mflo  s2
    nop
    nop
    nop
    nop
    mult  s1,v1

(2) Place the dummy instruction which generates the source interlock right after
    the mflo/mfhi.

ex1.
    mflo  s2
    or    zero,zero,s2
    mult  s1,v1

ex2.
　　mflo  s2
    addu  zero,zero,s2
    mult  s1,v1

(3) Don't put load/store instruction before mflo/mfhi within 2 instructions.
    Or don't put mflo/mfhi instruction after load/store instruction within 
    2 instructions. 

ex.
    lw  s0,0(a0)
    nop
    nop
    mflo  s2
    mult  s1,v1

(4) Use the MACC type of instructions which have destination instead of
    "mflo/mfhi" instructions.

ex1.
    mtlo zero
    macc  s2,a1,v0   /* alternative to mflo */
    mult  s1,v1

ex2.
    mtlo zero
    mthi zero
    macchi  s2,a1,v0 /* alternative to mfhi */
    mult  s1,v1

<End> ===========================================================