From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5503 invoked by alias); 2 Dec 2003 11:04:32 -0000 Mailing-List: contact cgen-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sources.redhat.com Received: (qmail 5140 invoked from network); 2 Dec 2003 11:04:14 -0000 Received: from unknown (HELO mail04.idc.renesas.com) (202.234.163.13) by sources.redhat.com with SMTP; 2 Dec 2003 11:04:14 -0000 Received: (from root@localhost) by guardian02.idc.renesas.com with id hB2B463U014782; Tue, 2 Dec 2003 20:04:06 +0900 (JST) Received: from unknown [172.20.8.71] by guardian02.idc.renesas.com with SMTP id WAA14781 ; Tue, 2 Dec 2003 20:04:06 +0900 Received: from dnma02 (dnma02.rso.renesas.com [10.15.11.200]) by dnma01.rso.renesas.com (iPlanet Messaging Server 5.2 HotFix 1.12 (built Feb 13 2003)) with ESMTP id <0HP900K5DLEORZ@dnma01.rso.renesas.com>; Tue, 02 Dec 2003 20:04:01 +0900 (JST) Received: from t1pcapricot.tool.maec.co.jp ([10.145.105.37]) by dnma02.rso.renesas.com (iPlanet Messaging Server 5.2 HotFix 1.12 (built Feb 13 2003)) with SMTP id <0HP900CL0LEL2R@dnma02.rso.renesas.com>; Tue, 02 Dec 2003 20:04:00 +0900 (JST) Date: Tue, 02 Dec 2003 11:04:00 -0000 From: Kazuhiro Inaoka Subject: [PATCH] Add new model m32r2 of Renesas M32R. To: cgen@sources.redhat.com Cc: gdb-patches@sources.redhat.com, binutils@sources.redhat.com Message-id: <003901c3b8c4$b3599840$2569910a@tool.maec.co.jp> MIME-version: 1.0 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Content-type: multipart/mixed; boundary="Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w)" X-Priority: 3 X-MSMail-priority: Normal X-SW-Source: 2003-q4/txt/msg00029.txt.bz2 This is a multi-part message in MIME format. --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: text/plain; charset=iso-2022-jp Content-transfer-encoding: 7BIT Content-length: 1859 Hi, The attached patches and files add new model m32r2 of Renesas M32R architecture support. Please commit. Kazuhiro Inaoka. cgen/ChangLog 2003-12-02 Kazuhiro Inaoka * cpu/m32r.cpu : Add new model m32r2. Add new instructions. Replace occurrances of 'Mitsubishi' with 'Renesas'. Changed PIPE attr of push from O to OS. Care for Little-endian of M32R. * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn): Care for Little-endian of M32R. (parse_slo16): signed extension for value. bfd/ChangeLog 2003-12-02 Kazuhiro Inaoka * archures.c (bfd_mach_m32r2): New machine types. * cpu-m32r.c : New machine types. * elf32-m32r.c (m32r_elf_object_p, m32r_elf_final_write_processing, m32r_elf_merge_private_bfd_data): New machine types. gas/ChangeLog 2003-12-02 Kazuhiro Inaoka * config/tc-m32r.c : Add new machine m32r2. Add new instructions. (line_separator_chars) : Use '!'. * config/tc-m32r.h : Add new machine m32r2. gas/tsetsuite/ChangeLog 2003-12-02 Kazuhiro Inaoka * gas/m32r/m32r2.exp : New file for m32r2. * gas/m32r/m32r2.s : Likewise. * gas/m32r/m32r2.d : Likewise. include/ChangeLog 2003-12-02 Kazuhiro Inaoka * elf/m32r.h : Add new machine type m32r2 and instruction modes. ChangeLog/sim/m32r 2003-12-02 Kazuhiro Inaoka * Makefile.in : Add new machine m32r2. * m32r2.c : New file for m32r2. * mloop2.in : Ditto * model2.c : Ditto * sem2-switch.c : Ditto * m32r-sim.h : Add EVB register. * sim-if.h : Ditto * sim-main.h : Ditto * traps.c : Ditto --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=sem2-switch.c Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=sem2-switch.c Content-length: 211899 /* Simulator instruction semantics for m32r2f.=0A= =0A= THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= =0A= Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foun= dation, Inc.=0A= =0A= This file is part of the GNU simulators.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= */=0A= =0A= #ifdef DEFINE_LABELS=0A= =0A= /* The labels have the case they have because the enum of insn types=0A= is all uppercase and in the non-stdc case the insn symbol is built=0A= into the enum name. */=0A= =0A= static struct {=0A= int index;=0A= void *label;=0A= } labels[] =3D {=0A= { M32R2F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },=0A= { M32R2F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },=0A= { M32R2F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },=0A= { M32R2F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },=0A= { M32R2F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },=0A= { M32R2F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },=0A= { M32R2F_INSN_ADD, && case_sem_INSN_ADD },=0A= { M32R2F_INSN_ADD3, && case_sem_INSN_ADD3 },=0A= { M32R2F_INSN_AND, && case_sem_INSN_AND },=0A= { M32R2F_INSN_AND3, && case_sem_INSN_AND3 },=0A= { M32R2F_INSN_OR, && case_sem_INSN_OR },=0A= { M32R2F_INSN_OR3, && case_sem_INSN_OR3 },=0A= { M32R2F_INSN_XOR, && case_sem_INSN_XOR },=0A= { M32R2F_INSN_XOR3, && case_sem_INSN_XOR3 },=0A= { M32R2F_INSN_ADDI, && case_sem_INSN_ADDI },=0A= { M32R2F_INSN_ADDV, && case_sem_INSN_ADDV },=0A= { M32R2F_INSN_ADDV3, && case_sem_INSN_ADDV3 },=0A= { M32R2F_INSN_ADDX, && case_sem_INSN_ADDX },=0A= { M32R2F_INSN_BC8, && case_sem_INSN_BC8 },=0A= { M32R2F_INSN_BC24, && case_sem_INSN_BC24 },=0A= { M32R2F_INSN_BEQ, && case_sem_INSN_BEQ },=0A= { M32R2F_INSN_BEQZ, && case_sem_INSN_BEQZ },=0A= { M32R2F_INSN_BGEZ, && case_sem_INSN_BGEZ },=0A= { M32R2F_INSN_BGTZ, && case_sem_INSN_BGTZ },=0A= { M32R2F_INSN_BLEZ, && case_sem_INSN_BLEZ },=0A= { M32R2F_INSN_BLTZ, && case_sem_INSN_BLTZ },=0A= { M32R2F_INSN_BNEZ, && case_sem_INSN_BNEZ },=0A= { M32R2F_INSN_BL8, && case_sem_INSN_BL8 },=0A= { M32R2F_INSN_BL24, && case_sem_INSN_BL24 },=0A= { M32R2F_INSN_BCL8, && case_sem_INSN_BCL8 },=0A= { M32R2F_INSN_BCL24, && case_sem_INSN_BCL24 },=0A= { M32R2F_INSN_BNC8, && case_sem_INSN_BNC8 },=0A= { M32R2F_INSN_BNC24, && case_sem_INSN_BNC24 },=0A= { M32R2F_INSN_BNE, && case_sem_INSN_BNE },=0A= { M32R2F_INSN_BRA8, && case_sem_INSN_BRA8 },=0A= { M32R2F_INSN_BRA24, && case_sem_INSN_BRA24 },=0A= { M32R2F_INSN_BNCL8, && case_sem_INSN_BNCL8 },=0A= { M32R2F_INSN_BNCL24, && case_sem_INSN_BNCL24 },=0A= { M32R2F_INSN_CMP, && case_sem_INSN_CMP },=0A= { M32R2F_INSN_CMPI, && case_sem_INSN_CMPI },=0A= { M32R2F_INSN_CMPU, && case_sem_INSN_CMPU },=0A= { M32R2F_INSN_CMPUI, && case_sem_INSN_CMPUI },=0A= { M32R2F_INSN_CMPEQ, && case_sem_INSN_CMPEQ },=0A= { M32R2F_INSN_CMPZ, && case_sem_INSN_CMPZ },=0A= { M32R2F_INSN_DIV, && case_sem_INSN_DIV },=0A= { M32R2F_INSN_DIVU, && case_sem_INSN_DIVU },=0A= { M32R2F_INSN_REM, && case_sem_INSN_REM },=0A= { M32R2F_INSN_REMU, && case_sem_INSN_REMU },=0A= { M32R2F_INSN_REMH, && case_sem_INSN_REMH },=0A= { M32R2F_INSN_REMUH, && case_sem_INSN_REMUH },=0A= { M32R2F_INSN_REMB, && case_sem_INSN_REMB },=0A= { M32R2F_INSN_REMUB, && case_sem_INSN_REMUB },=0A= { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH },=0A= { M32R2F_INSN_DIVB, && case_sem_INSN_DIVB },=0A= { M32R2F_INSN_DIVUB, && case_sem_INSN_DIVUB },=0A= { M32R2F_INSN_DIVH, && case_sem_INSN_DIVH },=0A= { M32R2F_INSN_JC, && case_sem_INSN_JC },=0A= { M32R2F_INSN_JNC, && case_sem_INSN_JNC },=0A= { M32R2F_INSN_JL, && case_sem_INSN_JL },=0A= { M32R2F_INSN_JMP, && case_sem_INSN_JMP },=0A= { M32R2F_INSN_LD, && case_sem_INSN_LD },=0A= { M32R2F_INSN_LD_D, && case_sem_INSN_LD_D },=0A= { M32R2F_INSN_LDB, && case_sem_INSN_LDB },=0A= { M32R2F_INSN_LDB_D, && case_sem_INSN_LDB_D },=0A= { M32R2F_INSN_LDH, && case_sem_INSN_LDH },=0A= { M32R2F_INSN_LDH_D, && case_sem_INSN_LDH_D },=0A= { M32R2F_INSN_LDUB, && case_sem_INSN_LDUB },=0A= { M32R2F_INSN_LDUB_D, && case_sem_INSN_LDUB_D },=0A= { M32R2F_INSN_LDUH, && case_sem_INSN_LDUH },=0A= { M32R2F_INSN_LDUH_D, && case_sem_INSN_LDUH_D },=0A= { M32R2F_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },=0A= { M32R2F_INSN_LD24, && case_sem_INSN_LD24 },=0A= { M32R2F_INSN_LDI8, && case_sem_INSN_LDI8 },=0A= { M32R2F_INSN_LDI16, && case_sem_INSN_LDI16 },=0A= { M32R2F_INSN_LOCK, && case_sem_INSN_LOCK },=0A= { M32R2F_INSN_MACHI_A, && case_sem_INSN_MACHI_A },=0A= { M32R2F_INSN_MACLO_A, && case_sem_INSN_MACLO_A },=0A= { M32R2F_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A },=0A= { M32R2F_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A },=0A= { M32R2F_INSN_MUL, && case_sem_INSN_MUL },=0A= { M32R2F_INSN_MULHI_A, && case_sem_INSN_MULHI_A },=0A= { M32R2F_INSN_MULLO_A, && case_sem_INSN_MULLO_A },=0A= { M32R2F_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A },=0A= { M32R2F_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A },=0A= { M32R2F_INSN_MV, && case_sem_INSN_MV },=0A= { M32R2F_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A },=0A= { M32R2F_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A },=0A= { M32R2F_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A },=0A= { M32R2F_INSN_MVFC, && case_sem_INSN_MVFC },=0A= { M32R2F_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A },=0A= { M32R2F_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A },=0A= { M32R2F_INSN_MVTC, && case_sem_INSN_MVTC },=0A= { M32R2F_INSN_NEG, && case_sem_INSN_NEG },=0A= { M32R2F_INSN_NOP, && case_sem_INSN_NOP },=0A= { M32R2F_INSN_NOT, && case_sem_INSN_NOT },=0A= { M32R2F_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI },=0A= { M32R2F_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI },=0A= { M32R2F_INSN_RTE, && case_sem_INSN_RTE },=0A= { M32R2F_INSN_SETH, && case_sem_INSN_SETH },=0A= { M32R2F_INSN_SLL, && case_sem_INSN_SLL },=0A= { M32R2F_INSN_SLL3, && case_sem_INSN_SLL3 },=0A= { M32R2F_INSN_SLLI, && case_sem_INSN_SLLI },=0A= { M32R2F_INSN_SRA, && case_sem_INSN_SRA },=0A= { M32R2F_INSN_SRA3, && case_sem_INSN_SRA3 },=0A= { M32R2F_INSN_SRAI, && case_sem_INSN_SRAI },=0A= { M32R2F_INSN_SRL, && case_sem_INSN_SRL },=0A= { M32R2F_INSN_SRL3, && case_sem_INSN_SRL3 },=0A= { M32R2F_INSN_SRLI, && case_sem_INSN_SRLI },=0A= { M32R2F_INSN_ST, && case_sem_INSN_ST },=0A= { M32R2F_INSN_ST_D, && case_sem_INSN_ST_D },=0A= { M32R2F_INSN_STB, && case_sem_INSN_STB },=0A= { M32R2F_INSN_STB_D, && case_sem_INSN_STB_D },=0A= { M32R2F_INSN_STH, && case_sem_INSN_STH },=0A= { M32R2F_INSN_STH_D, && case_sem_INSN_STH_D },=0A= { M32R2F_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },=0A= { M32R2F_INSN_STH_PLUS, && case_sem_INSN_STH_PLUS },=0A= { M32R2F_INSN_STB_PLUS, && case_sem_INSN_STB_PLUS },=0A= { M32R2F_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },=0A= { M32R2F_INSN_SUB, && case_sem_INSN_SUB },=0A= { M32R2F_INSN_SUBV, && case_sem_INSN_SUBV },=0A= { M32R2F_INSN_SUBX, && case_sem_INSN_SUBX },=0A= { M32R2F_INSN_TRAP, && case_sem_INSN_TRAP },=0A= { M32R2F_INSN_UNLOCK, && case_sem_INSN_UNLOCK },=0A= { M32R2F_INSN_SATB, && case_sem_INSN_SATB },=0A= { M32R2F_INSN_SATH, && case_sem_INSN_SATH },=0A= { M32R2F_INSN_SAT, && case_sem_INSN_SAT },=0A= { M32R2F_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ },=0A= { M32R2F_INSN_SADD, && case_sem_INSN_SADD },=0A= { M32R2F_INSN_MACWU1, && case_sem_INSN_MACWU1 },=0A= { M32R2F_INSN_MSBLO, && case_sem_INSN_MSBLO },=0A= { M32R2F_INSN_MULWU1, && case_sem_INSN_MULWU1 },=0A= { M32R2F_INSN_MACLH1, && case_sem_INSN_MACLH1 },=0A= { M32R2F_INSN_SC, && case_sem_INSN_SC },=0A= { M32R2F_INSN_SNC, && case_sem_INSN_SNC },=0A= { M32R2F_INSN_CLRPSW, && case_sem_INSN_CLRPSW },=0A= { M32R2F_INSN_SETPSW, && case_sem_INSN_SETPSW },=0A= { M32R2F_INSN_BSET, && case_sem_INSN_BSET },=0A= { M32R2F_INSN_BCLR, && case_sem_INSN_BCLR },=0A= { M32R2F_INSN_BTST, && case_sem_INSN_BTST },=0A= { M32R2F_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },=0A= { M32R2F_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },=0A= { M32R2F_INSN_PAR_AND, && case_sem_INSN_PAR_AND },=0A= { M32R2F_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND },=0A= { M32R2F_INSN_PAR_OR, && case_sem_INSN_PAR_OR },=0A= { M32R2F_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR },=0A= { M32R2F_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR },=0A= { M32R2F_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR },=0A= { M32R2F_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI },=0A= { M32R2F_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI },=0A= { M32R2F_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV },=0A= { M32R2F_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV },=0A= { M32R2F_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX },=0A= { M32R2F_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX },=0A= { M32R2F_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 },=0A= { M32R2F_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 },=0A= { M32R2F_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 },=0A= { M32R2F_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 },=0A= { M32R2F_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 },=0A= { M32R2F_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 },=0A= { M32R2F_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 },=0A= { M32R2F_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 },=0A= { M32R2F_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 },=0A= { M32R2F_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 },=0A= { M32R2F_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 },=0A= { M32R2F_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 },=0A= { M32R2F_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP },=0A= { M32R2F_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP },=0A= { M32R2F_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU },=0A= { M32R2F_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU },=0A= { M32R2F_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ },=0A= { M32R2F_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ },=0A= { M32R2F_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ },=0A= { M32R2F_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ },=0A= { M32R2F_INSN_PAR_JC, && case_sem_INSN_PAR_JC },=0A= { M32R2F_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC },=0A= { M32R2F_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC },=0A= { M32R2F_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC },=0A= { M32R2F_INSN_PAR_JL, && case_sem_INSN_PAR_JL },=0A= { M32R2F_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL },=0A= { M32R2F_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP },=0A= { M32R2F_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP },=0A= { M32R2F_INSN_PAR_LD, && case_sem_INSN_PAR_LD },=0A= { M32R2F_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD },=0A= { M32R2F_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB },=0A= { M32R2F_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB },=0A= { M32R2F_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH },=0A= { M32R2F_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH },=0A= { M32R2F_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB },=0A= { M32R2F_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB },=0A= { M32R2F_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH },=0A= { M32R2F_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH },=0A= { M32R2F_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS },=0A= { M32R2F_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS },=0A= { M32R2F_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 },=0A= { M32R2F_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 },=0A= { M32R2F_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK },=0A= { M32R2F_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK },=0A= { M32R2F_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A },=0A= { M32R2F_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A },=0A= { M32R2F_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A },=0A= { M32R2F_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A },=0A= { M32R2F_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A },=0A= { M32R2F_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A },=0A= { M32R2F_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A },=0A= { M32R2F_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A },=0A= { M32R2F_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL },=0A= { M32R2F_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL },=0A= { M32R2F_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A },=0A= { M32R2F_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A },=0A= { M32R2F_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A },=0A= { M32R2F_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A },=0A= { M32R2F_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A },=0A= { M32R2F_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A },=0A= { M32R2F_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A },=0A= { M32R2F_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A },=0A= { M32R2F_INSN_PAR_MV, && case_sem_INSN_PAR_MV },=0A= { M32R2F_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV },=0A= { M32R2F_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A },=0A= { M32R2F_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A },=0A= { M32R2F_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A },=0A= { M32R2F_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A },=0A= { M32R2F_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A },=0A= { M32R2F_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A },=0A= { M32R2F_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC },=0A= { M32R2F_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC },=0A= { M32R2F_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A },=0A= { M32R2F_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A },=0A= { M32R2F_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A },=0A= { M32R2F_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A },=0A= { M32R2F_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC },=0A= { M32R2F_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC },=0A= { M32R2F_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG },=0A= { M32R2F_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG },=0A= { M32R2F_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP },=0A= { M32R2F_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP },=0A= { M32R2F_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT },=0A= { M32R2F_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT },=0A= { M32R2F_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI },=0A= { M32R2F_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI },=0A= { M32R2F_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI },=0A= { M32R2F_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI },=0A= { M32R2F_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE },=0A= { M32R2F_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE },=0A= { M32R2F_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL },=0A= { M32R2F_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL },=0A= { M32R2F_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI },=0A= { M32R2F_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI },=0A= { M32R2F_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA },=0A= { M32R2F_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA },=0A= { M32R2F_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI },=0A= { M32R2F_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI },=0A= { M32R2F_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL },=0A= { M32R2F_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL },=0A= { M32R2F_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI },=0A= { M32R2F_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI },=0A= { M32R2F_INSN_PAR_ST, && case_sem_INSN_PAR_ST },=0A= { M32R2F_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST },=0A= { M32R2F_INSN_PAR_STB, && case_sem_INSN_PAR_STB },=0A= { M32R2F_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB },=0A= { M32R2F_INSN_PAR_STH, && case_sem_INSN_PAR_STH },=0A= { M32R2F_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },=0A= { M32R2F_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },=0A= { M32R2F_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },=0A= { M32R2F_INSN_PAR_STH_PLUS, && case_sem_INSN_PAR_STH_PLUS },=0A= { M32R2F_INSN_WRITE_STH_PLUS, && case_sem_INSN_WRITE_STH_PLUS },=0A= { M32R2F_INSN_PAR_STB_PLUS, && case_sem_INSN_PAR_STB_PLUS },=0A= { M32R2F_INSN_WRITE_STB_PLUS, && case_sem_INSN_WRITE_STB_PLUS },=0A= { M32R2F_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },=0A= { M32R2F_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },=0A= { M32R2F_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },=0A= { M32R2F_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB },=0A= { M32R2F_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV },=0A= { M32R2F_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV },=0A= { M32R2F_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX },=0A= { M32R2F_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX },=0A= { M32R2F_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP },=0A= { M32R2F_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP },=0A= { M32R2F_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK },=0A= { M32R2F_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK },=0A= { M32R2F_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ },=0A= { M32R2F_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ },=0A= { M32R2F_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD },=0A= { M32R2F_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD },=0A= { M32R2F_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 },=0A= { M32R2F_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 },=0A= { M32R2F_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO },=0A= { M32R2F_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO },=0A= { M32R2F_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 },=0A= { M32R2F_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 },=0A= { M32R2F_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 },=0A= { M32R2F_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 },=0A= { M32R2F_INSN_PAR_SC, && case_sem_INSN_PAR_SC },=0A= { M32R2F_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },=0A= { M32R2F_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },=0A= { M32R2F_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },=0A= { M32R2F_INSN_PAR_CLRPSW, && case_sem_INSN_PAR_CLRPSW },=0A= { M32R2F_INSN_WRITE_CLRPSW, && case_sem_INSN_WRITE_CLRPSW },=0A= { M32R2F_INSN_PAR_SETPSW, && case_sem_INSN_PAR_SETPSW },=0A= { M32R2F_INSN_WRITE_SETPSW, && case_sem_INSN_WRITE_SETPSW },=0A= { M32R2F_INSN_PAR_BTST, && case_sem_INSN_PAR_BTST },=0A= { M32R2F_INSN_WRITE_BTST, && case_sem_INSN_WRITE_BTST },=0A= { 0, 0 }=0A= };=0A= int i;=0A= =0A= for (i =3D 0; labels[i].label !=3D 0; ++i)=0A= {=0A= #if FAST_P=0A= CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab =3D labels[i].= label;=0A= #else=0A= CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab =3D labels[i].= label;=0A= #endif=0A= }=0A= =0A= #undef DEFINE_LABELS=0A= #endif /* DEFINE_LABELS */=0A= =0A= #ifdef DEFINE_SWITCH=0A= =0A= /* If hyper-fast [well not unnecessarily slow] execution is selected, turn= =0A= off frills like tracing and profiling. */=0A= /* FIXME: A better way would be to have TRACE_RESULT check for something=0A= that can cause it to be optimized out. Another way would be to emit=0A= special handlers into the instruction "stream". */=0A= =0A= #if FAST_P=0A= #undef TRACE_RESULT=0A= #define TRACE_RESULT(cpu, abuf, name, type, val)=0A= #endif=0A= =0A= #undef GET_ATTR=0A= #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)= =0A= #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs,= CGEN_INSN_##attr)=0A= #else=0A= #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs,= CGEN_INSN_/**/attr)=0A= #endif=0A= =0A= {=0A= =0A= #if WITH_SCACHE_PBB=0A= =0A= /* Branch to next handler without going around main loop. */=0A= #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case=0A= SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)=0A= =0A= #else /* ! WITH_SCACHE_PBB */=0A= =0A= #define NEXT(vpc) BREAK (sem)=0A= #ifdef __GNUC__=0A= #if FAST_P=0A= SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)=0A= #else=0A= SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)=0A= #endif=0A= #else=0A= SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)=0A= #endif=0A= =0A= #endif /* ! WITH_SCACHE_PBB */=0A= =0A= {=0A= =0A= CASE (sem, INSN_X_INVALID) : /* --invalid-- */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= {=0A= /* Update the recorded pc in the cpu state struct.=0A= Only necessary for WITH_SCACHE case, but to avoid the=0A= conditional compilation .... */=0A= SET_H_PC (pc);=0A= /* Virtual insns have zero size. Overwrite vpc with address of next in= sn=0A= using the default-insn-bitsize spec. When executing insns in parall= el=0A= we may want to queue the fault and continue execution. */=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= vpc =3D sim_engine_invalid_insn (current_cpu, pc, vpc);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_X_AFTER) : /* --after-- */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= {=0A= #if WITH_SCACHE_PBB_M32R2F=0A= m32r2f_pbb_after (current_cpu, sem_arg);=0A= #endif=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_X_BEFORE) : /* --before-- */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= {=0A= #if WITH_SCACHE_PBB_M32R2F=0A= m32r2f_pbb_before (current_cpu, sem_arg);=0A= #endif=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= {=0A= #if WITH_SCACHE_PBB_M32R2F=0A= #ifdef DEFINE_SWITCH=0A= vpc =3D m32r2f_pbb_cti_chain (current_cpu, sem_arg,=0A= pbb_br_type, pbb_br_npc);=0A= BREAK (sem);=0A= #else=0A= /* FIXME: Allow provision of explicit ifmt spec in insn spec. */=0A= vpc =3D m32r2f_pbb_cti_chain (current_cpu, sem_arg,=0A= CPU_PBB_BR_TYPE (current_cpu),=0A= CPU_PBB_BR_NPC (current_cpu));=0A= #endif=0A= #endif=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_X_CHAIN) : /* --chain-- */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= {=0A= #if WITH_SCACHE_PBB_M32R2F=0A= vpc =3D m32r2f_pbb_chain (current_cpu, sem_arg);=0A= #ifdef DEFINE_SWITCH=0A= BREAK (sem);=0A= #endif=0A= #endif=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_X_BEGIN) : /* --begin-- */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= {=0A= #if WITH_SCACHE_PBB_M32R2F=0A= #if defined DEFINE_SWITCH || defined FAST_P=0A= /* In the switch case FAST_P is a constant, allowing several optimizati= ons=0A= in any called inline functions. */=0A= vpc =3D m32r2f_pbb_begin (current_cpu, FAST_P);=0A= #else=0A= #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */=0A= vpc =3D m32r2f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (cur= rent_cpu)));=0A= #else=0A= vpc =3D m32r2f_pbb_begin (current_cpu, 0);=0A= #endif=0A= #endif=0A= #endif=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ADD) : /* add $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ADDSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D ADDSI (* FLD (i_sr), FLD (f_simm16));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_AND) : /* and $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ANDSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_and3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D ANDSI (* FLD (i_sr), FLD (f_uimm16));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_OR) : /* or $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ORSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_and3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D ORSI (* FLD (i_sr), FLD (f_uimm16));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_XOR) : /* xor $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D XORSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_and3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D XORSI (* FLD (i_sr), FLD (f_uimm16));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ADDSI (* FLD (i_dr), FLD (f_simm8));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ADDV) : /* addv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D ADDSI (* FLD (i_dr), * FLD (i_sr));=0A= temp1 =3D ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);=0A= {=0A= SI opval =3D temp0;=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D ADDSI (* FLD (i_sr), FLD (f_simm16));=0A= temp1 =3D ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);=0A= {=0A= SI opval =3D temp0;=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ADDX) : /* addx $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));=0A= temp1 =3D ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));=0A= {=0A= SI opval =3D temp0;=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BC8) : /* bc.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (CPU (h_cond)) {=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BC24) : /* bc.l $disp24 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (CPU (h_cond)) {=0A= {=0A= USI opval =3D FLD (i_disp24);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (EQSI (* FLD (i_src1), * FLD (i_src2))) {=0A= {=0A= USI opval =3D FLD (i_disp16);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 3);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (EQSI (* FLD (i_src2), 0)) {=0A= {=0A= USI opval =3D FLD (i_disp16);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (GESI (* FLD (i_src2), 0)) {=0A= {=0A= USI opval =3D FLD (i_disp16);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (GTSI (* FLD (i_src2), 0)) {=0A= {=0A= USI opval =3D FLD (i_disp16);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (LESI (* FLD (i_src2), 0)) {=0A= {=0A= USI opval =3D FLD (i_disp16);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (LTSI (* FLD (i_src2), 0)) {=0A= {=0A= USI opval =3D FLD (i_disp16);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_src2), 0)) {=0A= {=0A= USI opval =3D FLD (i_disp16);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BL8) : /* bl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= {=0A= SI opval =3D ADDSI (ANDSI (pc, -4), 4);=0A= CPU (h_gr[((UINT) 14)]) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BL24) : /* bl.l $disp24 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= {=0A= SI opval =3D ADDSI (pc, 4);=0A= CPU (h_gr[((UINT) 14)]) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp24);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (CPU (h_cond)) {=0A= {=0A= {=0A= SI opval =3D ADDSI (ANDSI (pc, -4), 4);=0A= CPU (h_gr[((UINT) 14)]) =3D opval;=0A= written |=3D (1 << 3);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 4);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (CPU (h_cond)) {=0A= {=0A= {=0A= SI opval =3D ADDSI (pc, 4);=0A= CPU (h_gr[((UINT) 14)]) =3D opval;=0A= written |=3D (1 << 3);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp24);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 4);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (NOTBI (CPU (h_cond))) {=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NOTBI (CPU (h_cond))) {=0A= {=0A= USI opval =3D FLD (i_disp24);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_src1), * FLD (i_src2))) {=0A= {=0A= USI opval =3D FLD (i_disp16);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 3);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BRA8) : /* bra.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= USI opval =3D FLD (i_disp8);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BRA24) : /* bra.l $disp24 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= USI opval =3D FLD (i_disp24);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (NOTBI (CPU (h_cond))) {=0A= {=0A= {=0A= SI opval =3D ADDSI (ANDSI (pc, -4), 4);=0A= CPU (h_gr[((UINT) 14)]) =3D opval;=0A= written |=3D (1 << 3);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 4);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NOTBI (CPU (h_cond))) {=0A= {=0A= {=0A= SI opval =3D ADDSI (pc, 4);=0A= CPU (h_gr[((UINT) 14)]) =3D opval;=0A= written |=3D (1 << 3);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp24);=0A= SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 4);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D LTSI (* FLD (i_src1), * FLD (i_src2));=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= BI opval =3D LTSI (* FLD (i_src2), FLD (f_simm16));=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D LTUSI (* FLD (i_src1), * FLD (i_src2));=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= BI opval =3D LTUSI (* FLD (i_src2), FLD (f_simm16));=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D EQSI (* FLD (i_src1), * FLD (i_src2));=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_CMPZ) : /* cmpz $src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D EQSI (* FLD (i_src2), 0);=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_DIV) : /* div $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D DIVSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_DIVU) : /* divu $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D UDIVSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_REM) : /* rem $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D MODSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_REMU) : /* remu $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D UMODSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_REMH) : /* remh $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D MODSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));= =0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_REMUH) : /* remuh $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D UMODSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_REMB) : /* remb $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D MODSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr));= =0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_REMUB) : /* remub $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D UMODSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_DIVUH) : /* divuh $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D UDIVSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_DIVB) : /* divb $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D DIVSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr));= =0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_DIVUB) : /* divub $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D UDIVSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_DIVH) : /* divh $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= if (NESI (* FLD (i_sr), 0)) {=0A= {=0A= SI opval =3D DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));= =0A= * FLD (i_dr) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_JC) : /* jc $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (CPU (h_cond)) {=0A= {=0A= USI opval =3D ANDSI (* FLD (i_sr), -4);=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_JNC) : /* jnc $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (NOTBI (CPU (h_cond))) {=0A= {=0A= USI opval =3D ANDSI (* FLD (i_sr), -4);=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_JL) : /* jl $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;USI temp1;=0A= temp0 =3D ADDSI (ANDSI (pc, -4), 4);=0A= temp1 =3D ANDSI (* FLD (i_sr), -4);=0A= {=0A= SI opval =3D temp0;=0A= CPU (h_gr[((UINT) 14)]) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D temp1;=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_JMP) : /* jmp $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= USI opval =3D ANDSI (* FLD (i_sr), -4);=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LD) : /* ld $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D GETMEMSI (current_cpu, pc, * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_sim= m16)));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), F= LD (f_simm16))));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), F= LD (f_simm16))));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), = FLD (f_simm16))));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), = FLD (f_simm16))));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;SI temp1;=0A= temp0 =3D GETMEMSI (current_cpu, pc, * FLD (i_sr));=0A= temp1 =3D ADDSI (* FLD (i_sr), 4);=0A= {=0A= SI opval =3D temp0;=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= SI opval =3D temp1;=0A= * FLD (i_sr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld24.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D FLD (i_uimm24);=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D FLD (f_simm8);=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D FLD (f_simm16);=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= {=0A= BI opval =3D 1;=0A= CPU (h_lock) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);=0A= }=0A= {=0A= SI opval =3D GETMEMSI (current_cpu, pc, * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EX= TSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FL= D (i_src2), 16))))), 8), 8);=0A= SET_H_ACCUMS (FLD (f_acc), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EX= TSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))),= 8), 8);=0A= SET_H_ACCUMS (FLD (f_acc), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (= i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));=0A= SET_H_ACCUMS (FLD (f_acc), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (= i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));=0A= SET_H_ACCUMS (FLD (f_acc), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MUL) : /* mul $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D MULSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xfff= f0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);=0A= SET_H_ACCUMS (FLD (f_acc), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)),= EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);=0A= SET_H_ACCUMS (FLD (f_acc), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI= (* FLD (i_src2), 16))));=0A= SET_H_ACCUMS (FLD (f_acc), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD= (i_src2))));=0A= SET_H_ACCUMS (FLD (f_acc), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MV) : /* mv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D * FLD (i_sr);=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D GET_H_CR (FLD (f_r2));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xfff= fffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));=0A= SET_H_ACCUMS (FLD (f_accs), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffff= ff, 0)), ZEXTSIDI (* FLD (i_src1)));=0A= SET_H_ACCUMS (FLD (f_accs), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= USI opval =3D * FLD (i_sr);=0A= SET_H_CR (FLD (f_r1), opval);=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_NEG) : /* neg $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D NEGSI (* FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_NOP) : /* nop */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_NOT) : /* not $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D INVSI (* FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI tmp_tmp1;=0A= tmp_tmp1 =3D SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));=0A= tmp_tmp1 =3D ADDDI (tmp_tmp1, MAKEDI (0, 32768));=0A= {=0A= DI opval =3D (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (3= 2767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0= xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));=0A= SET_H_ACCUMS (FLD (f_accd), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI tmp_tmp1;=0A= tmp_tmp1 =3D SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));=0A= tmp_tmp1 =3D ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));=0A= {=0A= DI opval =3D (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0))= : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (= ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));=0A= SET_H_ACCUMS (FLD (f_accd), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_RTE) : /* rte */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= {=0A= USI opval =3D ANDSI (GET_H_CR (((UINT) 6)), -4);=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= {=0A= USI opval =3D GET_H_CR (((UINT) 14));=0A= SET_H_CR (((UINT) 6), opval);=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D CPU (h_bpsw);=0A= SET_H_PSW (opval);=0A= TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D CPU (h_bbpsw);=0A= CPU (h_bpsw) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);=0A= }=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_seth.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D SLLSI (FLD (f_hi16), 16);=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SLL) : /* sll $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SLLSI (* FLD (i_dr), FLD (f_uimm5));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SRA) : /* sra $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SRASI (* FLD (i_dr), FLD (f_uimm5));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SRL) : /* srl $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SRLSI (* FLD (i_dr), FLD (f_uimm5));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ST) : /* st $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D * FLD (i_src1);=0A= SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D * FLD (i_src1);=0A= SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opva= l);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_STB) : /* stb $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= QI opval =3D * FLD (i_src1);=0A= SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= QI opval =3D * FLD (i_src1);=0A= SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opva= l);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_STH) : /* sth $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= HI opval =3D * FLD (i_src1);=0A= SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= HI opval =3D * FLD (i_src1);=0A= SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opva= l);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI tmp_new_src2;=0A= tmp_new_src2 =3D ADDSI (* FLD (i_src2), 4);=0A= {=0A= SI opval =3D * FLD (i_src1);=0A= SETMEMSI (current_cpu, pc, tmp_new_src2, opval);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= {=0A= SI opval =3D tmp_new_src2;=0A= * FLD (i_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_STH_PLUS) : /* sth $src1,@$src2+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= HI tmp_new_src2;=0A= {=0A= HI opval =3D * FLD (i_src1);=0A= SETMEMHI (current_cpu, pc, tmp_new_src2, opval);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= tmp_new_src2 =3D ADDSI (* FLD (i_src2), 2);=0A= {=0A= SI opval =3D tmp_new_src2;=0A= * FLD (i_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_STB_PLUS) : /* stb $src1,@$src2+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= QI tmp_new_src2;=0A= {=0A= QI opval =3D * FLD (i_src1);=0A= SETMEMQI (current_cpu, pc, tmp_new_src2, opval);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= tmp_new_src2 =3D ADDSI (* FLD (i_src2), 1);=0A= {=0A= SI opval =3D tmp_new_src2;=0A= * FLD (i_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI tmp_new_src2;=0A= tmp_new_src2 =3D SUBSI (* FLD (i_src2), 4);=0A= {=0A= SI opval =3D * FLD (i_src1);=0A= SETMEMSI (current_cpu, pc, tmp_new_src2, opval);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= {=0A= SI opval =3D tmp_new_src2;=0A= * FLD (i_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SUB) : /* sub $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SUBSI (* FLD (i_dr), * FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SUBV) : /* subv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D SUBSI (* FLD (i_dr), * FLD (i_sr));=0A= temp1 =3D SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);=0A= {=0A= SI opval =3D temp0;=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SUBX) : /* subx $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));=0A= temp1 =3D SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));=0A= {=0A= SI opval =3D temp0;=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_TRAP) : /* trap $uimm4 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_trap.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= {=0A= USI opval =3D GET_H_CR (((UINT) 6));=0A= SET_H_CR (((UINT) 14), opval);=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D ADDSI (pc, 4);=0A= SET_H_CR (((UINT) 6), opval);=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D CPU (h_bpsw);=0A= CPU (h_bbpsw) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D GET_H_PSW ();=0A= CPU (h_bpsw) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D ANDQI (GET_H_PSW (), 128);=0A= SET_H_PSW (opval);=0A= TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);=0A= }=0A= {=0A= SI opval =3D m32r_trap (current_cpu, pc, FLD (f_uimm4));=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= if (CPU (h_lock)) {=0A= {=0A= SI opval =3D * FLD (i_src1);=0A= SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);=0A= written |=3D (1 << 4);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= }=0A= {=0A= BI opval =3D 0;=0A= CPU (h_lock) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SATB) : /* satb $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), = -128)) ? (-128) : (* FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SATH) : /* sath $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_s= r), -32768)) ? (-32768) : (* FLD (i_sr));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SAT) : /* sat $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= SI opval =3D ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647= ) : (0x80000000))) : (* FLD (i_sr)));=0A= * FLD (i_dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (AND= SI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711= 680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0= );=0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SADD) : /* sadd */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS= (((UINT) 0)));=0A= SET_H_ACCUMS (((UINT) 0), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXT= SIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);= =0A= SET_H_ACCUMS (((UINT) 1), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (= EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))= , 32), 16)), 8), 8);=0A= SET_H_ACCUM (opval);=0A= TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (AN= DSI (* FLD (i_src2), 65535))), 16), 16);=0A= SET_H_ACCUMS (((UINT) 1), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXT= SIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 1= 6))), 16)), 8), 8);=0A= SET_H_ACCUMS (((UINT) 1), opval);=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SC) : /* sc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (ZEXTBISI (CPU (h_cond)))=0A= SEM_SKIP_INSN (current_cpu, sem_arg, vpc);=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SNC) : /* snc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (ZEXTBISI (NOTBI (CPU (h_cond))))=0A= SEM_SKIP_INSN (current_cpu, sem_arg, vpc);=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)),= 65280));=0A= SET_H_CR (((UINT) 0), opval);=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D FLD (f_uimm8);=0A= SET_H_CR (((UINT) 0), opval);=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= QI opval =3D ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD = (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));=0A= SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval)= ;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= =0A= {=0A= QI opval =3D ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD= (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));=0A= SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval)= ;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);= =0A= CPU (h_cond) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ADDSI (* FLD (i_dr), * FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ANDSI (* FLD (i_dr), * FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ORSI (* FLD (i_dr), * FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D XORSI (* FLD (i_dr), * FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= #define OPRND(f) par_exec->operands.sfmt_addi.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ADDSI (* FLD (i_dr), FLD (f_simm8));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= #define OPRND(f) par_exec->operands.sfmt_addi.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_addv.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D ADDSI (* FLD (i_dr), * FLD (i_sr));=0A= temp1 =3D ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);=0A= {=0A= SI opval =3D temp0;=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_addv.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_addx.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));=0A= temp1 =3D ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));=0A= {=0A= SI opval =3D temp0;=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_addx.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bc8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (CPU (h_cond)) {=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= OPRND (pc) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bc8.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= if (written & (1 << 2))=0A= {=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= {=0A= SI opval =3D ADDSI (ANDSI (pc, -4), 4);=0A= OPRND (h_gr_SI_14) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= OPRND (pc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bl8.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_gr[((UINT) 14)]) =3D OPRND (h_gr_SI_14);=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bcl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (CPU (h_cond)) {=0A= {=0A= {=0A= SI opval =3D ADDSI (ANDSI (pc, -4), 4);=0A= OPRND (h_gr_SI_14) =3D opval;=0A= written |=3D (1 << 3);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= OPRND (pc) =3D opval;=0A= written |=3D (1 << 4);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bcl8.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= if (written & (1 << 3))=0A= {=0A= CPU (h_gr[((UINT) 14)]) =3D OPRND (h_gr_SI_14);=0A= }=0A= if (written & (1 << 4))=0A= {=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bc8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (NOTBI (CPU (h_cond))) {=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= OPRND (pc) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bc8.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= if (written & (1 << 2))=0A= {=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bra8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= USI opval =3D FLD (i_disp8);=0A= OPRND (pc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bra8.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bcl8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (NOTBI (CPU (h_cond))) {=0A= {=0A= {=0A= SI opval =3D ADDSI (ANDSI (pc, -4), 4);=0A= OPRND (h_gr_SI_14) =3D opval;=0A= written |=3D (1 << 3);=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D FLD (i_disp8);=0A= OPRND (pc) =3D opval;=0A= written |=3D (1 << 4);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= #define OPRND(f) par_exec->operands.sfmt_bcl8.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= if (written & (1 << 3))=0A= {=0A= CPU (h_gr[((UINT) 14)]) =3D OPRND (h_gr_SI_14);=0A= }=0A= if (written & (1 << 4))=0A= {=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmp.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D LTSI (* FLD (i_src1), * FLD (i_src2));=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmp.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmp.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D LTUSI (* FLD (i_src1), * FLD (i_src2));=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmp.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmp.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D EQSI (* FLD (i_src1), * FLD (i_src2));=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmp.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmpz.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D EQSI (* FLD (i_src2), 0);=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmpz.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_JC) : /* jc $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= #define OPRND(f) par_exec->operands.sfmt_jc.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (CPU (h_cond)) {=0A= {=0A= USI opval =3D ANDSI (* FLD (i_sr), -4);=0A= OPRND (pc) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_JC) : /* jc $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= #define OPRND(f) par_exec->operands.sfmt_jc.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= if (written & (1 << 2))=0A= {=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_JNC) : /* jnc $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= #define OPRND(f) par_exec->operands.sfmt_jc.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (NOTBI (CPU (h_cond))) {=0A= {=0A= USI opval =3D ANDSI (* FLD (i_sr), -4);=0A= OPRND (pc) =3D opval;=0A= written |=3D (1 << 2);=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= #define OPRND(f) par_exec->operands.sfmt_jc.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= if (written & (1 << 2))=0A= {=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= }=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_JL) : /* jl $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= #define OPRND(f) par_exec->operands.sfmt_jl.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;USI temp1;=0A= temp0 =3D ADDSI (ANDSI (pc, -4), 4);=0A= temp1 =3D ANDSI (* FLD (i_sr), -4);=0A= {=0A= SI opval =3D temp0;=0A= OPRND (h_gr_SI_14) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D temp1;=0A= OPRND (pc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_JL) : /* jl $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= #define OPRND(f) par_exec->operands.sfmt_jl.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_gr[((UINT) 14)]) =3D OPRND (h_gr_SI_14);=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_JMP) : /* jmp $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= #define OPRND(f) par_exec->operands.sfmt_jmp.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= USI opval =3D ANDSI (* FLD (i_sr), -4);=0A= OPRND (pc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= #define OPRND(f) par_exec->operands.sfmt_jmp.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ld.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D GETMEMSI (current_cpu, pc, * FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ld.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldb.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldb.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldh.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldh.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldb.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldb.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldh.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldh.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ld_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;SI temp1;=0A= temp0 =3D GETMEMSI (current_cpu, pc, * FLD (i_sr));=0A= temp1 =3D ADDSI (* FLD (i_sr), 4);=0A= {=0A= SI opval =3D temp0;=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= SI opval =3D temp1;=0A= OPRND (sr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_ld_plus.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= * FLD (i_sr) =3D OPRND (sr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldi8.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D FLD (f_simm8);=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= #define OPRND(f) par_exec->operands.sfmt_ldi8.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_lock.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= {=0A= BI opval =3D 1;=0A= OPRND (h_lock_BI) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);=0A= }=0A= {=0A= SI opval =3D GETMEMSI (current_cpu, pc, * FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_lock.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= CPU (h_lock) =3D OPRND (h_lock_BI);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EX= TSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FL= D (i_src2), 16))))), 8), 8);=0A= OPRND (acc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_machi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_acc), OPRND (acc));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EX= TSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))),= 8), 8);=0A= OPRND (acc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_machi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_acc), OPRND (acc));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (= i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));=0A= OPRND (acc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_machi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_acc), OPRND (acc));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_machi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (= i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));=0A= OPRND (acc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_machi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_acc), OPRND (acc));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D MULSI (* FLD (i_dr), * FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xfff= f0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);=0A= OPRND (acc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_acc), OPRND (acc));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)),= EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);=0A= OPRND (acc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_acc), OPRND (acc));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI= (* FLD (i_src2), 16))));=0A= OPRND (acc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_acc), OPRND (acc));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD= (i_src2))));=0A= OPRND (acc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_acc), OPRND (acc));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mv.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D * FLD (i_sr);=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mv.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvfc.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D GET_H_CR (FLD (f_r2));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvfc.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xfff= fffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));=0A= OPRND (accs) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_accs), OPRND (accs));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffff= ff, 0)), ZEXTSIDI (* FLD (i_src1)));=0A= OPRND (accs) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_accs), OPRND (accs));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvtc.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= USI opval =3D * FLD (i_sr);=0A= OPRND (dcr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mvtc.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_CR (FLD (f_r1), OPRND (dcr));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mv.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D NEGSI (* FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mv.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_NOP) : /* nop */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_nop.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_NOP) : /* nop */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_nop.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mv.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D INVSI (* FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mv.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= #define OPRND(f) par_exec->operands.sfmt_rac_dsi.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI tmp_tmp1;=0A= tmp_tmp1 =3D SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));=0A= tmp_tmp1 =3D ADDDI (tmp_tmp1, MAKEDI (0, 32768));=0A= {=0A= DI opval =3D (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (3= 2767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0= xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));=0A= OPRND (accd) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= #define OPRND(f) par_exec->operands.sfmt_rac_dsi.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_accd), OPRND (accd));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= #define OPRND(f) par_exec->operands.sfmt_rac_dsi.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI tmp_tmp1;=0A= tmp_tmp1 =3D SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));=0A= tmp_tmp1 =3D ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));=0A= {=0A= DI opval =3D (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0))= : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (= ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));=0A= OPRND (accd) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= #define OPRND(f) par_exec->operands.sfmt_rac_dsi.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (FLD (f_accd), OPRND (accd));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_RTE) : /* rte */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_rte.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= {=0A= USI opval =3D ANDSI (GET_H_CR (((UINT) 6)), -4);=0A= OPRND (pc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= {=0A= USI opval =3D GET_H_CR (((UINT) 14));=0A= OPRND (h_cr_USI_6) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D CPU (h_bpsw);=0A= OPRND (h_psw_UQI) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D CPU (h_bbpsw);=0A= OPRND (h_bpsw_UQI) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_RTE) : /* rte */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_rte.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_bpsw) =3D OPRND (h_bpsw_UQI);=0A= SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));=0A= SET_H_PSW (OPRND (h_psw_UQI));=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= #define OPRND(f) par_exec->operands.sfmt_slli.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SLLSI (* FLD (i_dr), FLD (f_uimm5));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= #define OPRND(f) par_exec->operands.sfmt_slli.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= #define OPRND(f) par_exec->operands.sfmt_slli.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SRASI (* FLD (i_dr), FLD (f_uimm5));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= #define OPRND(f) par_exec->operands.sfmt_slli.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= #define OPRND(f) par_exec->operands.sfmt_slli.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SRLSI (* FLD (i_dr), FLD (f_uimm5));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= #define OPRND(f) par_exec->operands.sfmt_slli.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_st.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D * FLD (i_src1);=0A= OPRND (h_memory_SI_src2_idx) =3D * FLD (i_src2);=0A= OPRND (h_memory_SI_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_st.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_= SI_src2));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_stb.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= QI opval =3D * FLD (i_src1);=0A= OPRND (h_memory_QI_src2_idx) =3D * FLD (i_src2);=0A= OPRND (h_memory_QI_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_stb.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_src2_idx), OPRND (h_memory_= QI_src2));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_sth.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= HI opval =3D * FLD (i_src1);=0A= OPRND (h_memory_HI_src2_idx) =3D * FLD (i_src2);=0A= OPRND (h_memory_HI_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_sth.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_src2_idx), OPRND (h_memory_= HI_src2));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI tmp_new_src2;=0A= tmp_new_src2 =3D ADDSI (* FLD (i_src2), 4);=0A= {=0A= SI opval =3D * FLD (i_src1);=0A= OPRND (h_memory_SI_new_src2_idx) =3D tmp_new_src2;=0A= OPRND (h_memory_SI_new_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= {=0A= SI opval =3D tmp_new_src2;=0A= OPRND (src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_st_plus.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_mem= ory_SI_new_src2));=0A= * FLD (i_src2) =3D OPRND (src2);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_STH_PLUS) : /* sth $src1,@$src2+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_sth_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= HI tmp_new_src2;=0A= {=0A= HI opval =3D * FLD (i_src1);=0A= OPRND (h_memory_HI_new_src2_idx) =3D tmp_new_src2;=0A= OPRND (h_memory_HI_new_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= tmp_new_src2 =3D ADDSI (* FLD (i_src2), 2);=0A= {=0A= SI opval =3D tmp_new_src2;=0A= OPRND (src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_sth_plus.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_new_src2_idx), OPRND (h_mem= ory_HI_new_src2));=0A= * FLD (i_src2) =3D OPRND (src2);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_STB_PLUS) : /* stb $src1,@$src2+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_stb_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= QI tmp_new_src2;=0A= {=0A= QI opval =3D * FLD (i_src1);=0A= OPRND (h_memory_QI_new_src2_idx) =3D tmp_new_src2;=0A= OPRND (h_memory_QI_new_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= tmp_new_src2 =3D ADDSI (* FLD (i_src2), 1);=0A= {=0A= SI opval =3D tmp_new_src2;=0A= OPRND (src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_STB_PLUS) : /* stb $src1,@$src2+ */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_stb_plus.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_new_src2_idx), OPRND (h_mem= ory_QI_new_src2));=0A= * FLD (i_src2) =3D OPRND (src2);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_st_plus.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI tmp_new_src2;=0A= tmp_new_src2 =3D SUBSI (* FLD (i_src2), 4);=0A= {=0A= SI opval =3D * FLD (i_src1);=0A= OPRND (h_memory_SI_new_src2_idx) =3D tmp_new_src2;=0A= OPRND (h_memory_SI_new_src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= {=0A= SI opval =3D tmp_new_src2;=0A= OPRND (src2) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_st_plus.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_mem= ory_SI_new_src2));=0A= * FLD (i_src2) =3D OPRND (src2);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D SUBSI (* FLD (i_dr), * FLD (i_sr));=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_add.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_addv.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D SUBSI (* FLD (i_dr), * FLD (i_sr));=0A= temp1 =3D SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);=0A= {=0A= SI opval =3D temp0;=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_addv.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_addx.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI temp0;BI temp1;=0A= temp0 =3D SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));=0A= temp1 =3D SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));=0A= {=0A= SI opval =3D temp0;=0A= OPRND (dr) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= }=0A= {=0A= BI opval =3D temp1;=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= #define OPRND(f) par_exec->operands.sfmt_addx.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= * FLD (i_dr) =3D OPRND (dr);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_trap.f=0A= #define OPRND(f) par_exec->operands.sfmt_trap.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= {=0A= USI opval =3D GET_H_CR (((UINT) 6));=0A= OPRND (h_cr_USI_14) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= {=0A= USI opval =3D ADDSI (pc, 4);=0A= OPRND (h_cr_USI_6) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D CPU (h_bpsw);=0A= OPRND (h_bbpsw_UQI) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D GET_H_PSW ();=0A= OPRND (h_bpsw_UQI) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);=0A= }=0A= {=0A= UQI opval =3D ANDQI (GET_H_PSW (), 128);=0A= OPRND (h_psw_UQI) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);=0A= }=0A= {=0A= SI opval =3D m32r_trap (current_cpu, pc, FLD (f_uimm4));=0A= OPRND (pc) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= }=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_trap.f=0A= #define OPRND(f) par_exec->operands.sfmt_trap.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= SEM_BRANCH_INIT=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_bbpsw) =3D OPRND (h_bbpsw_UQI);=0A= CPU (h_bpsw) =3D OPRND (h_bpsw_UQI);=0A= SET_H_CR (((UINT) 14), OPRND (h_cr_USI_14));=0A= SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));=0A= SET_H_PSW (OPRND (h_psw_UQI));=0A= SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);=0A= =0A= SEM_BRANCH_FINI (vpc);=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_unlock.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= if (CPU (h_lock)) {=0A= {=0A= SI opval =3D * FLD (i_src1);=0A= OPRND (h_memory_SI_src2_idx) =3D * FLD (i_src2);=0A= OPRND (h_memory_SI_src2) =3D opval;=0A= written |=3D (1 << 4);=0A= TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= }=0A= }=0A= {=0A= BI opval =3D 0;=0A= OPRND (h_lock_BI) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);=0A= }=0A= }=0A= =0A= abuf->written =3D written;=0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_unlock.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_lock) =3D OPRND (h_lock_BI);=0A= if (written & (1 << 4))=0A= {=0A= SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_mem= ory_SI_src2));=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmpz.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (AND= SI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711= 680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0= );=0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_cmpz.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SADD) : /* sadd */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_sadd.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS= (((UINT) 0)));=0A= OPRND (h_accums_DI_0) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SADD) : /* sadd */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_sadd.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_DI_0));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_macwu1.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXT= SIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);= =0A= OPRND (h_accums_DI_1) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_macwu1.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_msblo.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (= EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))= , 32), 16)), 8), 8);=0A= OPRND (accum) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_msblo.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUM (OPRND (accum));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulwu1.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (AN= DSI (* FLD (i_src2), 65535))), 16), 16);=0A= OPRND (h_accums_DI_1) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_mulwu1.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_macwu1.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= DI opval =3D SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXT= SIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 1= 6))), 16)), 8), 8);=0A= OPRND (h_accums_DI_1) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= #define OPRND(f) par_exec->operands.sfmt_macwu1.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SC) : /* sc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_sc.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (ZEXTBISI (CPU (h_cond)))=0A= SEM_SKIP_INSN (current_cpu, sem_arg, vpc);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SC) : /* sc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_sc.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SNC) : /* snc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_sc.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= if (ZEXTBISI (NOTBI (CPU (h_cond))))=0A= SEM_SKIP_INSN (current_cpu, sem_arg, vpc);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SNC) : /* snc */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= #define OPRND(f) par_exec->operands.sfmt_sc.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_CLRPSW) : /* clrpsw $uimm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= #define OPRND(f) par_exec->operands.sfmt_clrpsw.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)),= 65280));=0A= OPRND (h_cr_USI_0) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= #define OPRND(f) par_exec->operands.sfmt_clrpsw.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_SETPSW) : /* setpsw $uimm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= #define OPRND(f) par_exec->operands.sfmt_setpsw.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= SI opval =3D FLD (f_uimm8);=0A= OPRND (h_cr_USI_0) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= #define OPRND(f) par_exec->operands.sfmt_setpsw.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_PAR_BTST) : /* btst $uimm3,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= #define OPRND(f) par_exec->operands.sfmt_btst.f=0A= int UNUSED written =3D 0;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 2);=0A= =0A= {=0A= BI opval =3D ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);= =0A= OPRND (condbit) =3D opval;=0A= TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);=0A= }=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= CASE (sem, INSN_WRITE_BTST) : /* btst $uimm3,$sr */=0A= {=0A= SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= const ARGBUF *abuf =3D SEM_ARGBUF (sem_arg)->fields.write.abuf;=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= #define OPRND(f) par_exec->operands.sfmt_btst.f=0A= int UNUSED written =3D abuf->written;=0A= IADDR UNUSED pc =3D abuf->addr;=0A= vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= =0A= CPU (h_cond) =3D OPRND (condbit);=0A= =0A= #undef OPRND=0A= #undef FLD=0A= }=0A= NEXT (vpc);=0A= =0A= =0A= }=0A= ENDSWITCH (sem) /* End of semantic switch. */=0A= =0A= /* At this point `vpc' contains the next insn to execute. */=0A= }=0A= =0A= #undef DEFINE_SWITCH=0A= #endif /* DEFINE_SWITCH */=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=m32r2.d Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=m32r2.d Content-length: 2860 #as: -m32r2=0A= #objdump: -dr=0A= #name: m32r2=0A= =0A= .*: +file format .*=0A= =0A= Disassembly of section .text:=0A= =0A= 0+0000 :=0A= 0: 71 c1 71 ff setpsw #0xc1 -> setpsw #0xff=0A= =0A= 0+0004 :=0A= 4: 72 c1 72 ff clrpsw #0xc1 -> clrpsw #0xff=0A= =0A= 0+0008 :=0A= 8: a0 61 00 04 bset #0x0,@\(4,r1\)=0A= c: a1 61 00 04 bset #0x1,@\(4,r1\)=0A= 10: a7 61 00 04 bset #0x7,@\(4,r1\)=0A= =0A= 0+0014 :=0A= 14: a0 71 00 04 bclr #0x0,@\(4,r1\)=0A= 18: a1 71 00 04 bclr #0x1,@\(4,r1\)=0A= 1c: a7 71 00 04 bclr #0x7,@\(4,r1\)=0A= =0A= 0+0020 :=0A= 20: 00 fd 01 fd btst #0x0,fp -> btst #0x1,fp=0A= 24: 07 fd f0 00 btst #0x7,fp \|\| nop=0A= 28: 01 fd 90 82 btst #0x1,fp \|\| mv r0,r2=0A= 2c: 01 fd 90 82 btst #0x1,fp \|\| mv r0,r2=0A= =0A= 0+0030 :=0A= 30: 9d 1d 00 10 divuh fp,fp=0A= =0A= 0+0034 :=0A= 34: 9d 0d 00 18 divb fp,fp=0A= =0A= 0+0038 :=0A= 38: 9d 1d 00 18 divub fp,fp=0A= =0A= 0+003c :=0A= 3c: 9d 2d 00 10 remh fp,fp=0A= =0A= 0+0040 :=0A= 40: 9d 3d 00 10 remuh fp,fp=0A= =0A= 0+0044 :=0A= 44: 9d 2d 00 18 remb fp,fp=0A= =0A= 0+0048 :=0A= 48: 9d 3d 00 18 remub fp,fp=0A= =0A= 0+004c :=0A= 4c: 10 41 92 43 sll r0,r1 \|\| sll r2,r3=0A= 50: 12 43 90 61 sll r2,r3 \|\| mul r0,r1=0A= 54: 10 41 92 63 sll r0,r1 \|\| mul r2,r3=0A= 58: 60 01 92 43 ldi r0,#1 \|\| sll r2,r3=0A= 5c: 10 41 e2 01 sll r0,r1 \|\| ldi r2,#1=0A= =0A= 0+0060 :=0A= 60: 50 41 d2 5f slli r0,#0x1 \|\| slli r2,#0x1f=0A= 64: 52 5f 90 61 slli r2,#0x1f \|\| mul r0,r1=0A= 68: 50 41 92 63 slli r0,#0x1 \|\| mul r2,r3=0A= 6c: 60 01 d2 5f ldi r0,#1 \|\| slli r2,#0x1f=0A= 70: 50 41 e2 01 slli r0,#0x1 \|\| ldi r2,#1=0A= =0A= 0+0074 :=0A= 74: 10 21 92 23 sra r0,r1 \|\| sra r2,r3=0A= 78: 12 23 90 61 sra r2,r3 \|\| mul r0,r1=0A= 7c: 10 21 92 63 sra r0,r1 \|\| mul r2,r3=0A= 80: 60 01 92 23 ldi r0,#1 \|\| sra r2,r3=0A= 84: 10 21 e2 01 sra r0,r1 \|\| ldi r2,#1=0A= =0A= 0+0088 :=0A= 88: 50 21 d2 3f srai r0,#0x1 \|\| srai r2,#0x1f=0A= 8c: 52 3f 90 61 srai r2,#0x1f \|\| mul r0,r1=0A= 90: 50 21 92 63 srai r0,#0x1 \|\| mul r2,r3=0A= 94: 60 01 d2 3f ldi r0,#1 \|\| srai r2,#0x1f=0A= 98: 50 21 e2 01 srai r0,#0x1 \|\| ldi r2,#1=0A= =0A= 0+009c :=0A= 9c: 10 01 92 03 srl r0,r1 \|\| srl r2,r3=0A= a0: 12 03 90 61 srl r2,r3 \|\| mul r0,r1=0A= a4: 10 01 92 63 srl r0,r1 \|\| mul r2,r3=0A= a8: 60 01 92 03 ldi r0,#1 \|\| srl r2,r3=0A= ac: 10 01 e2 01 srl r0,r1 \|\| ldi r2,#1=0A= =0A= 0+00b0 :=0A= b0: 50 01 d2 1f srli r0,#0x1 \|\| srli r2,#0x1f=0A= b4: 52 1f 90 61 srli r2,#0x1f \|\| mul r0,r1=0A= b8: 50 01 92 63 srli r0,#0x1 \|\| mul r2,r3=0A= bc: 60 01 d2 1f ldi r0,#1 \|\| srli r2,#0x1f=0A= c0: 50 01 e2 01 srli r0,#0x1 \|\| ldi r2,#1=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=m32r2.exp Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=m32r2.exp Content-length: 104 # M32R2 assembler testsuite.=0A= =0A= if [istarget m32r*-*-*] {=0A= run_dump_test "m32r2"=0A= }=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=mloop2.in Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=mloop2.in Content-length: 14911 # Simulator main loop for m32r2. -*- C -*-=0A= # Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.=0A= #=0A= # This file is part of the GNU Simulators.=0A= #=0A= # This program is free software; you can redistribute it and/or modify=0A= # it under the terms of the GNU General Public License as published by=0A= # the Free Software Foundation; either version 2, or (at your option)=0A= # any later version.=0A= #=0A= # This program is distributed in the hope that it will be useful,=0A= # but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= # GNU General Public License for more details.=0A= #=0A= # You should have received a copy of the GNU General Public License along= =0A= # with this program; if not, write to the Free Software Foundation, Inc.,= =0A= # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= # Syntax:=0A= # /bin/sh mainloop.in command=0A= #=0A= # Command is one of:=0A= #=0A= # init=0A= # support=0A= # extract-{simple,scache,pbb}=0A= # {full,fast}-exec-{simple,scache,pbb}=0A= #=0A= # A target need only provide a "full" version of one of simple,scache,pbb.= =0A= # If the target wants it can also provide a fast version of same, or if=0A= # the slow (full featured) version is `simple', then the fast version can b= e=0A= # one of scache/pbb.=0A= # A target can't provide more than this.=0A= =0A= # ??? After a few more ports are done, revisit.=0A= # Will eventually need to machine generate a lot of this.=0A= =0A= case "x$1" in=0A= =0A= xsupport)=0A= =0A= cat <argbuf;=0A= id1 =3D id1->par_idesc;=0A= abuf->fields.write.abuf =3D &sc1->argbuf;=0A= @cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0);=0A= /* no need to set trace_p,profile_p */=0A= #if 0 /* not currently needed for id2 since results written directly */=0A= abuf =3D &sc[1].argbuf;=0A= id2 =3D id2->par_idesc;=0A= abuf->fields.write.abuf =3D &sc2->argbuf;=0A= @cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0);=0A= /* no need to set trace_p,profile_p */=0A= #endif=0A= }=0A= =0A= static INLINE const IDESC *=0A= emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,=0A= SCACHE *sc, int fast_p, int parallel_p)=0A= {=0A= ARGBUF *abuf =3D &sc->argbuf;=0A= const IDESC *id =3D @cpu@_decode (current_cpu, pc, insn, insn, abuf);=0A= =0A= if (parallel_p)=0A= id =3D id->par_idesc;=0A= @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);=0A= return id;=0A= }=0A= =0A= static INLINE const IDESC *=0A= emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *s= c,=0A= int trace_p, int profile_p)=0A= {=0A= const IDESC *id;=0A= =0A= @cpu@_emit_before (current_cpu, sc, pc, 1);=0A= id =3D emit_16 (current_cpu, pc, insn, sc + 1, 0, 0);=0A= @cpu@_emit_after (current_cpu, sc + 2, pc);=0A= sc[1].argbuf.trace_p =3D trace_p;=0A= sc[1].argbuf.profile_p =3D profile_p;=0A= return id;=0A= }=0A= =0A= static INLINE const IDESC *=0A= emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,=0A= SCACHE *sc, int fast_p)=0A= {=0A= const IDESC *id,*id2;=0A= =0A= /* Emit both insns, then emit a finisher-upper.=0A= We speed things up by handling the second insn serially=0A= [not parallelly]. Then the writeback only has to deal=0A= with the first insn. */=0A= /* ??? Revisit to handle exceptions right. */=0A= =0A= /* FIXME: No need to handle this parallely if second is nop. */=0A= id =3D emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);=0A= =0A= /* Note that this can never be a cti. No cti's go in the S pipeline. */= =0A= id2 =3D emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0);= =0A= =0A= /* Set sc/snc insns notion of where to skip to. */=0A= if (IDESC_SKIP_P (id))=0A= SEM_SKIP_COMPILE (current_cpu, sc, 1);=0A= =0A= /* Emit code to finish executing the semantics=0A= (write back the results). */=0A= emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2);=0A= =0A= return id;=0A= }=0A= =0A= static INLINE const IDESC *=0A= emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,=0A= SCACHE *sc, int trace_p, int profile_p)=0A= {=0A= const IDESC *id,*id2;=0A= =0A= /* Emit both insns, then emit a finisher-upper.=0A= We speed things up by handling the second insn serially=0A= [not parallelly]. Then the writeback only has to deal=0A= with the first insn. */=0A= /* ??? Revisit to handle exceptions right. */=0A= =0A= @cpu@_emit_before (current_cpu, sc, pc, 1);=0A= =0A= /* FIXME: No need to handle this parallelly if second is nop. */=0A= id =3D emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1);=0A= sc[1].argbuf.trace_p =3D trace_p;=0A= sc[1].argbuf.profile_p =3D profile_p;=0A= =0A= @cpu@_emit_before (current_cpu, sc + 2, pc, 0);=0A= =0A= /* Note that this can never be a cti. No cti's go in the S pipeline. */= =0A= id2 =3D emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0);=0A= sc[3].argbuf.trace_p =3D trace_p;=0A= sc[3].argbuf.profile_p =3D profile_p;=0A= =0A= /* Set sc/snc insns notion of where to skip to. */=0A= if (IDESC_SKIP_P (id))=0A= SEM_SKIP_COMPILE (current_cpu, sc, 4);=0A= =0A= /* Emit code to finish executing the semantics=0A= (write back the results). */=0A= emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2);=0A= =0A= @cpu@_emit_after (current_cpu, sc + 5, pc);=0A= =0A= return id;=0A= }=0A= =0A= static INLINE const IDESC *=0A= emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,=0A= SCACHE *sc, int fast_p)=0A= {=0A= ARGBUF *abuf =3D &sc->argbuf;=0A= const IDESC *id =3D @cpu@_decode (current_cpu, pc,=0A= (USI) insn >> 16, insn, abuf);=0A= =0A= @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);=0A= return id;=0A= }=0A= =0A= static INLINE const IDESC *=0A= emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *s= c,=0A= int trace_p, int profile_p)=0A= {=0A= const IDESC *id;=0A= =0A= @cpu@_emit_before (current_cpu, sc, pc, 1);=0A= id =3D emit_32 (current_cpu, pc, insn, sc + 1, 0);=0A= @cpu@_emit_after (current_cpu, sc + 2, pc);=0A= sc[1].argbuf.trace_p =3D trace_p;=0A= sc[1].argbuf.profile_p =3D profile_p;=0A= return id;=0A= }=0A= =0A= EOF=0A= =0A= ;;=0A= =0A= xinit)=0A= =0A= # Nothing needed.=0A= =0A= ;;=0A= =0A= xextract-pbb)=0A= =0A= # Inputs: current_cpu, pc, sc, max_insns, FAST_P=0A= # Outputs: sc, pc=0A= # sc must be left pointing past the last created entry.=0A= # pc must be left pointing past the last created entry.=0A= # If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called=0A= # to record the vpc of the cti insn.=0A= # SET_INSN_COUNT(n) must be called to record number of real insns.=0A= =0A= cat < 0)=0A= {=0A= USI insn =3D GETIMEMUSI (current_cpu, pc);=0A= if ((SI) insn < 0)=0A= {=0A= /* 32 bit insn */=0A= idesc =3D emit_32 (current_cpu, pc, insn, sc, 1);=0A= ++sc;=0A= --max_insns;=0A= ++icount;=0A= pc +=3D 4;=0A= if (IDESC_CTI_P (idesc))=0A= {=0A= SET_CTI_VPC (sc - 1);=0A= break;=0A= }=0A= }=0A= else=0A= {=0A= if ((insn & 0x8000) !=3D 0) /* parallel? */=0A= {=0A= /* Yep. Here's the "interesting" [sic] part. */=0A= idesc =3D emit_parallel (current_cpu, pc, insn, sc, 1);=0A= sc +=3D 3;=0A= max_insns -=3D 3;=0A= icount +=3D 2;=0A= pc +=3D 4;=0A= if (IDESC_CTI_P (idesc))=0A= {=0A= SET_CTI_VPC (sc - 3);=0A= break;=0A= }=0A= }=0A= else /* 2 serial 16 bit insns */=0A= {=0A= idesc =3D emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0);=0A= ++sc;=0A= --max_insns;=0A= ++icount;=0A= pc +=3D 2;=0A= if (IDESC_CTI_P (idesc))=0A= {=0A= SET_CTI_VPC (sc - 1);=0A= break;=0A= }=0A= /* While we're guaranteed that there's room to extract the=0A= insn, when single stepping we can't; the pbb must stop=0A= after the first insn. */=0A= if (max_insns =3D=3D 0)=0A= break;=0A= idesc =3D emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0);=0A= ++sc;=0A= --max_insns;=0A= ++icount;=0A= pc +=3D 2;=0A= if (IDESC_CTI_P (idesc))=0A= {=0A= SET_CTI_VPC (sc - 1);=0A= break;=0A= }=0A= }=0A= }=0A= }=0A= }=0A= else /* ! FAST_P */=0A= {=0A= while (max_insns > 0)=0A= {=0A= USI insn =3D GETIMEMUSI (current_cpu, pc);=0A= int trace_p =3D PC_IN_TRACE_RANGE_P (current_cpu, pc);=0A= int profile_p =3D PC_IN_PROFILE_RANGE_P (current_cpu, pc);=0A= SCACHE *cti_sc; /* ??? tmp hack */=0A= if ((SI) insn < 0)=0A= {=0A= /* 32 bit insn=0A= Only emit before/after handlers if necessary. */=0A= if (trace_p || profile_p)=0A= {=0A= idesc =3D emit_full32 (current_cpu, pc, insn, sc,=0A= trace_p, profile_p);=0A= cti_sc =3D sc + 1;=0A= sc +=3D 3;=0A= max_insns -=3D 3;=0A= }=0A= else=0A= {=0A= idesc =3D emit_32 (current_cpu, pc, insn, sc, 0);=0A= cti_sc =3D sc;=0A= ++sc;=0A= --max_insns;=0A= }=0A= ++icount;=0A= pc +=3D 4;=0A= if (IDESC_CTI_P (idesc))=0A= {=0A= SET_CTI_VPC (cti_sc);=0A= break;=0A= }=0A= }=0A= else=0A= {=0A= if ((insn & 0x8000) !=3D 0) /* parallel? */=0A= {=0A= /* Yep. Here's the "interesting" [sic] part.=0A= Only emit before/after handlers if necessary. */=0A= if (trace_p || profile_p)=0A= {=0A= idesc =3D emit_full_parallel (current_cpu, pc, insn, sc,=0A= trace_p, profile_p);=0A= cti_sc =3D sc + 1;=0A= sc +=3D 6;=0A= max_insns -=3D 6;=0A= }=0A= else=0A= {=0A= idesc =3D emit_parallel (current_cpu, pc, insn, sc, 0);=0A= cti_sc =3D sc;=0A= sc +=3D 3;=0A= max_insns -=3D 3;=0A= }=0A= icount +=3D 2;=0A= pc +=3D 4;=0A= if (IDESC_CTI_P (idesc))=0A= {=0A= SET_CTI_VPC (cti_sc);=0A= break;=0A= }=0A= }=0A= else /* 2 serial 16 bit insns */=0A= {=0A= /* Only emit before/after handlers if necessary. */=0A= if (trace_p || profile_p)=0A= {=0A= idesc =3D emit_full16 (current_cpu, pc, insn >> 16, sc,=0A= trace_p, profile_p);=0A= cti_sc =3D sc + 1;=0A= sc +=3D 3;=0A= max_insns -=3D 3;=0A= }=0A= else=0A= {=0A= idesc =3D emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0);=0A= cti_sc =3D sc;=0A= ++sc;=0A= --max_insns;=0A= }=0A= ++icount;=0A= pc +=3D 2;=0A= if (IDESC_CTI_P (idesc))=0A= {=0A= SET_CTI_VPC (cti_sc);=0A= break;=0A= }=0A= /* While we're guaranteed that there's room to extract the=0A= insn, when single stepping we can't; the pbb must stop=0A= after the first insn. */=0A= if (max_insns <=3D 0)=0A= break;=0A= /* Use the same trace/profile address for the 2nd insn.=0A= Saves us having to compute it and they come in pairs=0A= anyway (e.g. can never branch to the 2nd insn). */=0A= if (trace_p || profile_p)=0A= {=0A= idesc =3D emit_full16 (current_cpu, pc, insn & 0x7fff, sc,=0A= trace_p, profile_p);=0A= cti_sc =3D sc + 1;=0A= sc +=3D 3;=0A= max_insns -=3D 3;=0A= }=0A= else=0A= {=0A= idesc =3D emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0);=0A= cti_sc =3D sc;=0A= ++sc;=0A= --max_insns;=0A= }=0A= ++icount;=0A= pc +=3D 2;=0A= if (IDESC_CTI_P (idesc))=0A= {=0A= SET_CTI_VPC (cti_sc);=0A= break;=0A= }=0A= }=0A= }=0A= }=0A= }=0A= =0A= Finish:=0A= SET_INSN_COUNT (icount);=0A= }=0A= EOF=0A= =0A= ;;=0A= =0A= xfull-exec-pbb)=0A= =0A= # Inputs: current_cpu, vpc, FAST_P=0A= # Outputs: vpc=0A= # vpc is the virtual program counter.=0A= =0A= cat <&2=0A= exit 1=0A= ;;=0A= =0A= esac=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=m32r2.c Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=m32r2.c Content-length: 9332 /* m32r2 simulator support code=0A= Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.=0A= Contributed by Cygnus Support.=0A= =0A= This file is part of GDB, the GNU debugger.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */=0A= =0A= #define WANT_CPU m32r2f=0A= #define WANT_CPU_M32R2F=0A= =0A= #include "sim-main.h"=0A= #include "cgen-mem.h"=0A= #include "cgen-ops.h"=0A= =0A= /* The contents of BUF are in target byte order. */=0A= =0A= int=0A= m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, in= t len)=0A= {=0A= return m32rbf_fetch_register (current_cpu, rn, buf, len);=0A= }=0A= =0A= /* The contents of BUF are in target byte order. */=0A= =0A= int=0A= m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, in= t len)=0A= {=0A= return m32rbf_store_register (current_cpu, rn, buf, len);=0A= }=0A= =0C=0A= /* Cover fns to get/set the control registers.=0A= FIXME: Duplicated from m32r.c. The issue is structure offsets. */=0A= =0A= USI=0A= m32r2f_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)=0A= {=0A= switch (cr)=0A= {=0A= case H_CR_PSW : /* psw */=0A= return (((CPU (h_bpsw) & 0xc1) << 8)=0A= | ((CPU (h_psw) & 0xc0) << 0)=0A= | GET_H_COND ());=0A= case H_CR_BBPSW : /* backup backup psw */=0A= return CPU (h_bbpsw) & 0xc1;=0A= case H_CR_CBR : /* condition bit */=0A= return GET_H_COND ();=0A= case H_CR_SPI : /* interrupt stack pointer */=0A= if (! GET_H_SM ())=0A= return CPU (h_gr[H_GR_SP]);=0A= else=0A= return CPU (h_cr[H_CR_SPI]);=0A= case H_CR_SPU : /* user stack pointer */=0A= if (GET_H_SM ())=0A= return CPU (h_gr[H_GR_SP]);=0A= else=0A= return CPU (h_cr[H_CR_SPU]);=0A= case H_CR_BPC : /* backup pc */=0A= return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;=0A= case H_CR_BBPC : /* backup backup pc */=0A= return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;=0A= case 4 : /* ??? unspecified, but apparently available */=0A= case 5 : /* ??? unspecified, but apparently available */=0A= return CPU (h_cr[cr]);=0A= default :=0A= return 0;=0A= }=0A= }=0A= =0A= void=0A= m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)=0A= {=0A= switch (cr)=0A= {=0A= case H_CR_PSW : /* psw */=0A= {=0A= int old_sm =3D (CPU (h_psw) & 0x80) !=3D 0;=0A= int new_sm =3D (newval & 0x80) !=3D 0;=0A= CPU (h_bpsw) =3D (newval >> 8) & 0xff;=0A= CPU (h_psw) =3D newval & 0xff;=0A= SET_H_COND (newval & 1);=0A= /* When switching stack modes, update the registers. */=0A= if (old_sm !=3D new_sm)=0A= {=0A= if (old_sm)=0A= {=0A= /* Switching user -> system. */=0A= CPU (h_cr[H_CR_SPU]) =3D CPU (h_gr[H_GR_SP]);=0A= CPU (h_gr[H_GR_SP]) =3D CPU (h_cr[H_CR_SPI]);=0A= }=0A= else=0A= {=0A= /* Switching system -> user. */=0A= CPU (h_cr[H_CR_SPI]) =3D CPU (h_gr[H_GR_SP]);=0A= CPU (h_gr[H_GR_SP]) =3D CPU (h_cr[H_CR_SPU]);=0A= }=0A= }=0A= break;=0A= }=0A= case H_CR_BBPSW : /* backup backup psw */=0A= CPU (h_bbpsw) =3D newval & 0xff;=0A= break;=0A= case H_CR_CBR : /* condition bit */=0A= SET_H_COND (newval & 1);=0A= break;=0A= case H_CR_SPI : /* interrupt stack pointer */=0A= if (! GET_H_SM ())=0A= CPU (h_gr[H_GR_SP]) =3D newval;=0A= else=0A= CPU (h_cr[H_CR_SPI]) =3D newval;=0A= break;=0A= case H_CR_SPU : /* user stack pointer */=0A= if (GET_H_SM ())=0A= CPU (h_gr[H_GR_SP]) =3D newval;=0A= else=0A= CPU (h_cr[H_CR_SPU]) =3D newval;=0A= break;=0A= case H_CR_BPC : /* backup pc */=0A= CPU (h_cr[H_CR_BPC]) =3D newval;=0A= break;=0A= case H_CR_BBPC : /* backup backup pc */=0A= CPU (h_cr[H_CR_BBPC]) =3D newval;=0A= break;=0A= case 4 : /* ??? unspecified, but apparently available */=0A= case 5 : /* ??? unspecified, but apparently available */=0A= CPU (h_cr[cr]) =3D newval;=0A= break;=0A= default :=0A= /* ignore */=0A= break;=0A= }=0A= }=0A= =0A= /* Cover fns to access h-psw. */=0A= =0A= UQI=0A= m32r2f_h_psw_get_handler (SIM_CPU *current_cpu)=0A= {=0A= return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);=0A= }=0A= =0A= void=0A= m32r2f_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)=0A= {=0A= CPU (h_psw) =3D newval;=0A= CPU (h_cond) =3D newval & 1;=0A= }=0A= =0A= /* Cover fns to access h-accum. */=0A= =0A= DI=0A= m32r2f_h_accum_get_handler (SIM_CPU *current_cpu)=0A= {=0A= /* Sign extend the top 8 bits. */=0A= DI r;=0A= r =3D ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));=0A= r =3D XORDI (r, MAKEDI (0x800000, 0));=0A= r =3D SUBDI (r, MAKEDI (0x800000, 0));=0A= return r;=0A= }=0A= =0A= void=0A= m32r2f_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)=0A= {=0A= CPU (h_accum) =3D newval;=0A= }=0A= =0A= /* Cover fns to access h-accums. */=0A= =0A= DI=0A= m32r2f_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)=0A= {=0A= /* FIXME: Yes, this is just a quick hack. */=0A= DI r;=0A= if (regno =3D=3D 0)=0A= r =3D CPU (h_accum);=0A= else=0A= r =3D CPU (h_accums[1]);=0A= /* Sign extend the top 8 bits. */=0A= r =3D ANDDI (r, MAKEDI (0xffffff, 0xffffffff));=0A= r =3D XORDI (r, MAKEDI (0x800000, 0));=0A= r =3D SUBDI (r, MAKEDI (0x800000, 0));=0A= return r;=0A= }=0A= =0A= void=0A= m32r2f_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)= =0A= {=0A= /* FIXME: Yes, this is just a quick hack. */=0A= if (regno =3D=3D 0)=0A= CPU (h_accum) =3D newval;=0A= else=0A= CPU (h_accums[1]) =3D newval;=0A= }=0A= =0C=0A= #if WITH_PROFILE_MODEL_P=0A= =0A= /* Initialize cycle counting for an insn.=0A= FIRST_P is non-zero if this is the first insn in a set of parallel=0A= insns. */=0A= =0A= void=0A= m32r2f_model_insn_before (SIM_CPU *cpu, int first_p)=0A= {=0A= m32rbf_model_insn_before (cpu, first_p);=0A= }=0A= =0A= /* Record the cycles computed for an insn.=0A= LAST_P is non-zero if this is the last insn in a set of parallel insns,= =0A= and we update the total cycle count.=0A= CYCLES is the cycle count of the insn. */=0A= =0A= void=0A= m32r2f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)=0A= {=0A= m32rbf_model_insn_after (cpu, last_p, cycles);=0A= }=0A= =0A= static INLINE void=0A= check_load_stall (SIM_CPU *cpu, int regno)=0A= {=0A= UINT h_gr =3D CPU_M32R_MISC_PROFILE (cpu)->load_regs;=0A= =0A= if (regno !=3D -1=0A= && (h_gr & (1 << regno)) !=3D 0)=0A= {=0A= CPU_M32R_MISC_PROFILE (cpu)->load_stall +=3D 2;=0A= if (TRACE_INSN_P (cpu))=0A= cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");=0A= }=0A= }=0A= =0A= int=0A= m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc,=0A= int unit_num, int referenced,=0A= INT sr, INT sr2, INT dr)=0A= {=0A= check_load_stall (cpu, sr);=0A= check_load_stall (cpu, sr2);=0A= return idesc->timing->units[unit_num].done;=0A= }=0A= =0A= int=0A= m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc,=0A= int unit_num, int referenced,=0A= INT src1, INT src2)=0A= {=0A= check_load_stall (cpu, src1);=0A= check_load_stall (cpu, src2);=0A= return idesc->timing->units[unit_num].done;=0A= }=0A= =0A= int=0A= m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc,=0A= int unit_num, int referenced,=0A= INT src1, INT src2)=0A= {=0A= check_load_stall (cpu, src1);=0A= check_load_stall (cpu, src2);=0A= return idesc->timing->units[unit_num].done;=0A= }=0A= =0A= int=0A= m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc,=0A= int unit_num, int referenced,=0A= INT sr)=0A= {=0A= PROFILE_DATA *profile =3D CPU_PROFILE_DATA (cpu);=0A= int taken_p =3D (referenced & (1 << 1)) !=3D 0;=0A= =0A= check_load_stall (cpu, sr);=0A= if (taken_p)=0A= {=0A= CPU_M32R_MISC_PROFILE (cpu)->cti_stall +=3D 2;=0A= PROFILE_MODEL_TAKEN_COUNT (profile) +=3D 1;=0A= }=0A= else=0A= PROFILE_MODEL_UNTAKEN_COUNT (profile) +=3D 1;=0A= return idesc->timing->units[unit_num].done;=0A= }=0A= =0A= int=0A= m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc,=0A= int unit_num, int referenced,=0A= INT sr, INT dr)=0A= {=0A= CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |=3D (1 << dr);=0A= return idesc->timing->units[unit_num].done;=0A= }=0A= =0A= int=0A= m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc,=0A= int unit_num, int referenced,=0A= INT src1, INT src2)=0A= {=0A= return idesc->timing->units[unit_num].done;=0A= }=0A= =0A= #endif /* WITH_PROFILE_MODEL_P */=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=bfd.m32r2.patch Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=bfd.m32r2.patch Content-length: 4708 bfd/ChangeLog=0A= =0A= 2003-12-02 Kazuhiro Inaoka =0A= =0A= * archures.c (bfd_mach_m32r2): New machine types.=0A= * cpu-m32r.c : New machine types.=0A= * elf32-m32r.c (m32r_elf_object_p, m32r_elf_final_write_processing,= =0A= m32r_elf_merge_private_bfd_data): New machine types.=0A= =0A= =0A= Index: bfd/archures.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/bfd/archures.c,v=0A= retrieving revision 1.87=0A= diff -c -r1.87 archures.c=0A= *** bfd/archures.c 24 Nov 2003 18:06:39 -0000 1.87=0A= --- bfd/archures.c 2 Dec 2003 08:56:08 -0000=0A= ***************=0A= *** 272,277 ****=0A= --- 272,278 ----=0A= . bfd_arch_m32r, {* Renesas M32R (formerly Mitsubishi M32R/D) *}=0A= .#define bfd_mach_m32r 1 {* For backwards compatibility. *}=0A= .#define bfd_mach_m32rx 'x'=0A= + .#define bfd_mach_m32r2 '2'=0A= . bfd_arch_mn10200, {* Matsushita MN10200 *}=0A= . bfd_arch_mn10300, {* Matsushita MN10300 *}=0A= .#define bfd_mach_mn10300 300=0A= Index: bfd/cpu-m32r.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/bfd/cpu-m32r.c,v=0A= retrieving revision 1.5=0A= diff -c -r1.5 cpu-m32r.c=0A= *** bfd/cpu-m32r.c 30 Nov 2002 08:39:36 -0000 1.5=0A= --- bfd/cpu-m32r.c 2 Dec 2003 08:56:09 -0000=0A= ***************=0A= *** 26,35 ****=0A= bfd_default_compatible, bfd_default_scan, next }=0A= =20=20=0A= #define NEXT NULL=0A= =20=20=0A= static const bfd_arch_info_type arch_info_struct[] =3D=0A= {=0A= ! N (bfd_mach_m32rx, "m32rx", FALSE, NULL)=0A= };=0A= =20=20=0A= #undef NEXT=0A= --- 26,37 ----=0A= bfd_default_compatible, bfd_default_scan, next }=0A= =20=20=0A= #define NEXT NULL=0A= + #define M32R2_NEXT &arch_info_struct[1]=0A= =20=20=0A= static const bfd_arch_info_type arch_info_struct[] =3D=0A= {=0A= ! N (bfd_mach_m32rx, "m32rx", FALSE, M32R2_NEXT) ,=0A= ! N (bfd_mach_m32r2, "m32r2", FALSE, NULL)=0A= };=0A= =20=20=0A= #undef NEXT=0A= Index: bfd/elf32-m32r.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/bfd/elf32-m32r.c,v=0A= retrieving revision 1.37=0A= diff -c -r1.37 elf32-m32r.c=0A= *** bfd/elf32-m32r.c 1 Dec 2003 06:28:23 -0000 1.37=0A= --- bfd/elf32-m32r.c 2 Dec 2003 08:56:09 -0000=0A= ***************=0A= *** 1863,1868 ****=0A= --- 1863,1869 ----=0A= default:=0A= case E_M32R_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_= m32r, bfd_mach_m32r); break;=0A= case E_M32RX_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_= m32r, bfd_mach_m32rx); break;=0A= + case E_M32R2_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_= m32r, bfd_mach_m32r2); break;=0A= }=0A= return TRUE;=0A= }=0A= ***************=0A= *** 1880,1885 ****=0A= --- 1881,1887 ----=0A= default:=0A= case bfd_mach_m32r: val =3D E_M32R_ARCH; break;=0A= case bfd_mach_m32rx: val =3D E_M32RX_ARCH; break;=0A= + case bfd_mach_m32r2: val =3D E_M32R2_ARCH; break;=0A= }=0A= =20=20=0A= elf_elfheader (abfd)->e_flags &=3D~ EF_M32R_ARCH;=0A= ***************=0A= *** 1946,1952 ****=0A= =20=20=0A= if ((in_flags & EF_M32R_ARCH) !=3D (out_flags & EF_M32R_ARCH))=0A= {=0A= ! if ((in_flags & EF_M32R_ARCH) !=3D E_M32R_ARCH)=0A= {=0A= (*_bfd_error_handler)=0A= (_("%s: Instruction set mismatch with previous modules"),=0A= --- 1948,1956 ----=0A= =20=20=0A= if ((in_flags & EF_M32R_ARCH) !=3D (out_flags & EF_M32R_ARCH))=0A= {=0A= ! if (((in_flags & EF_M32R_ARCH) !=3D E_M32R_ARCH)=0A= ! || ((out_flags & EF_M32R_ARCH) =3D=3D E_M32R_ARCH)=0A= ! || ((in_flags & EF_M32R_ARCH) =3D=3D E_M32R2_ARCH))=0A= {=0A= (*_bfd_error_handler)=0A= (_("%s: Instruction set mismatch with previous modules"),=0A= ***************=0A= *** 1979,1984 ****=0A= --- 1983,1989 ----=0A= default:=0A= case E_M32R_ARCH: fprintf (file, _(": m32r instructions")); break;= =0A= case E_M32RX_ARCH: fprintf (file, _(": m32rx instructions")); break;= =0A= + case E_M32R2_ARCH: fprintf (file, _(": m32r2 instructions")); break;= =0A= }=0A= =20=20=0A= fputc ('\n', file);=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=cgen.m32r2.patch Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=cgen.m32r2.patch Content-length: 71304 cgen/ChangLog=0A= =0A= 2003-12-02 Kazuhiro Inaoka =0A= =0A= * cpu/m32r.cpu : Add new model m32r2.=0A= Add new instructions.=0A= Replace occurrances of 'Mitsubishi' with 'Renesas'.=0A= Changed PIPE attr of push from O to OS.=0A= Care for Little-endian of M32R.=0A= * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):=0A= Care for Little-endian of M32R.=0A= (parse_slo16): signed extension for value.=0A= =0A= Index: cgen/cpu/m32r.cpu=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/cgen/cpu/m32r.cpu,v=0A= retrieving revision 1.4=0A= diff -c -r1.4 m32r.cpu=0A= *** cgen/cpu/m32r.cpu 16 Jul 2003 05:35:48 -0000 1.4=0A= --- cgen/cpu/m32r.cpu 2 Dec 2003 08:56:10 -0000=0A= ***************=0A= *** 1,4 ****=0A= ! ; Mitsubishi M32R CPU description. -*- Scheme -*-=0A= ; Copyright (C) 2000 Red Hat, Inc.=0A= ; This file is part of CGEN.=0A= ; See file COPYING.CGEN for details.=0A= --- 1,4 ----=0A= ! ; Renesas M32R CPU description. -*- Scheme -*-=0A= ; Copyright (C) 2000 Red Hat, Inc.=0A= ; This file is part of CGEN.=0A= ; See file COPYING.CGEN for details.=0A= ***************=0A= *** 12,34 ****=0A= =20=20=0A= (define-arch=0A= (name m32r) ; name of cpu family=0A= ! (comment "Mitsubishi M32R")=0A= (default-alignment aligned)=0A= (insn-lsb0? #f)=0A= ! (machs m32r m32rx)=0A= (isas m32r)=0A= )=0A= =20=20=0A= ; Attributes.=0A= =20=20=0A= ; An attribute to describe which pipeline an insn runs in.=0A= =20=20=0A= (define-attr=0A= (for insn)=0A= (type enum)=0A= (name PIPE)=0A= (comment "parallel execution pipeline selection")=0A= ! (values NONE O S OS)=0A= )=0A= =20=20=0A= ; A derived attribute that says which insns can be executed in parallel= =0A= --- 12,36 ----=0A= =20=20=0A= (define-arch=0A= (name m32r) ; name of cpu family=0A= ! (comment "Renesas M32R")=0A= (default-alignment aligned)=0A= (insn-lsb0? #f)=0A= ! (machs m32r m32rx m32r2)=0A= (isas m32r)=0A= )=0A= =20=20=0A= ; Attributes.=0A= =20=20=0A= ; An attribute to describe which pipeline an insn runs in.=0A= + ; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.=0A= + ; Thease instructions have O attribute for m32rx and OS attribute for m32= r2.=0A= =20=20=0A= (define-attr=0A= (for insn)=0A= (type enum)=0A= (name PIPE)=0A= (comment "parallel execution pipeline selection")=0A= ! (values NONE O S OS O_OS)=0A= )=0A= =20=20=0A= ; A derived attribute that says which insns can be executed in parallel= =0A= ***************=0A= *** 141,148 ****=0A= ; The "b" suffix stands for "base" and is the convention.=0A= ; The "f" suffix stands for "family" and is the convention.=0A= (name m32rbf)=0A= ! (comment "Mitsubishi M32R base family")=0A= ! (endian big)=0A= (word-bitsize 32)=0A= ; Override isa spec (??? keeps things simpler, though it was more true= =0A= ; in the early days and not so much now).=0A= --- 143,150 ----=0A= ; The "b" suffix stands for "base" and is the convention.=0A= ; The "f" suffix stands for "family" and is the convention.=0A= (name m32rbf)=0A= ! (comment "Renesas M32R base family")=0A= ! (endian either)=0A= (word-bitsize 32)=0A= ; Override isa spec (??? keeps things simpler, though it was more true= =0A= ; in the early days and not so much now).=0A= ***************=0A= *** 151,163 ****=0A= =20=20=0A= (define-cpu=0A= (name m32rxf)=0A= ! (comment "Mitsubishi M32Rx family")=0A= ! (endian big)=0A= (word-bitsize 32)=0A= ; Generated files have an "x" suffix.=0A= (file-transform "x")=0A= )=0A= =20=20=0A= (define-mach=0A= (name m32r)=0A= (comment "Generic M32R cpu")=0A= --- 153,175 ----=0A= =20=20=0A= (define-cpu=0A= (name m32rxf)=0A= ! (comment "Renesas M32Rx family")=0A= ! (endian either)=0A= (word-bitsize 32)=0A= ; Generated files have an "x" suffix.=0A= (file-transform "x")=0A= )=0A= =20=20=0A= + (define-cpu=0A= + (name m32r2f)=0A= + (comment "Renesas M32R2 family")=0A= + (endian either)=0A= + (word-bitsize 32)=0A= + ; Generated files have an "2" suffix.=0A= + (file-transform "2")=0A= + )=0A= +=20=0A= +=20=0A= (define-mach=0A= (name m32r)=0A= (comment "Generic M32R cpu")=0A= ***************=0A= *** 169,174 ****=0A= --- 181,192 ----=0A= (comment "M32RX cpu")=0A= (cpu m32rxf)=0A= )=0A= +=20=0A= + (define-mach=0A= + (name m32r2)=0A= + (comment "M32R2 cpu")=0A= + (cpu m32r2f)=0A= + )=0A= =0C=0A= ; Model descriptions.=0A= =20=20=0A= ***************=0A= *** 309,314 ****=0A= --- 327,385 ----=0A= () ; profile action (default)=0A= )=0A= )=0A= +=20=0A= + (define-model=0A= + (name m32r2) (comment "m32r2") (attrs)=0A= + (mach m32r2)=0A= +=20=0A= + ; ??? It's 6 stages but I forget the details right now.=0A= + (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))=0A= + (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))=0A= + (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback= )))=0A= +=20=0A= + (unit u-exec "Execution Unit" ()=0A= + 1 1 ; issue done=0A= + () ; state=0A= + ((sr INT -1) (dr INT -1)) ; inputs=0A= + ((dr INT -1)) ; outputs=0A= + () ; profile action (default)=0A= + )=0A= + (unit u-cmp "Compare Unit" ()=0A= + 1 1 ; issue done=0A= + () ; state=0A= + ((src1 INT -1) (src2 INT -1)) ; inputs=0A= + () ; outputs=0A= + () ; profile action (default)=0A= + )=0A= + (unit u-mac "Multiply/Accumulate Unit" ()=0A= + 1 1 ; issue done=0A= + () ; state=0A= + ((src1 INT -1) (src2 INT -1)) ; inputs=0A= + () ; outputs=0A= + () ; profile action (default)=0A= + )=0A= + (unit u-cti "Branch Unit" ()=0A= + 1 1 ; issue done=0A= + () ; state=0A= + ((sr INT -1)) ; inputs=0A= + ((pc)) ; outputs=0A= + () ; profile action (default)=0A= + )=0A= + (unit u-load "Memory Load Unit" ()=0A= + 1 1 ; issue done=0A= + () ; state=0A= + ((sr INT)) ; inputs=0A= + ((dr INT)) ; outputs=0A= + () ; profile action (default)=0A= + )=0A= + (unit u-store "Memory Store Unit" ()=0A= + 1 1 ; issue done=0A= + () ; state=0A= + ((src1 INT) (src2 INT)) ; inputs=0A= + () ; outputs=0A= + () ; profile action (default)=0A= + )=0A= + )=0A= =0C=0A= ; The instruction fetch/execute cycle.=0A= ; This is split into two parts as sometimes more than one instruction is= =0A= ***************=0A= *** 379,386 ****=0A= --- 450,459 ----=0A= (df f-simm8 "simm8" () 8 8 INT #f #f)=0A= (df f-simm16 "simm16" () 16 16 INT #f #f)=0A= (dnf f-shift-op2 "shift op2" () 8 3)=0A= + (dnf f-uimm3 "uimm3" () 5 3)=0A= (dnf f-uimm4 "uimm4" () 12 4)=0A= (dnf f-uimm5 "uimm5" () 11 5)=0A= + (dnf f-uimm8 "uimm8" () 8 8)=0A= (dnf f-uimm16 "uimm16" () 16 16)=0A= (dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24)=0A= (dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16)=0A= ***************=0A= *** 400,405 ****=0A= --- 473,479 ----=0A= (dnf f-accs "accs" () 12 2)=0A= (dnf f-accd "accd" () 4 2)=0A= (dnf f-bits67 "bits67" () 6 2)=0A= + (dnf f-bit4 "bit4" () 4 1)=0A= (dnf f-bit14 "bit14" () 14 1)=0A= =20=20=0A= (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")=0A= ***************=0A= *** 472,478 ****=0A= (print-name h-cr)=0A= (prefix "")=0A= (values (psw 0) (cbr 1) (spi 2) (spu 3)=0A= ! (bpc 6) (bbpsw 8) (bbpc 14)=0A= (cr0 0) (cr1 1) (cr2 2) (cr3 3)=0A= (cr4 4) (cr5 5) (cr6 6) (cr7 7)=0A= (cr8 8) (cr9 9) (cr10 10) (cr11 11)=0A= --- 546,552 ----=0A= (print-name h-cr)=0A= (prefix "")=0A= (values (psw 0) (cbr 1) (spi 2) (spu 3)=0A= ! (bpc 6) (bbpsw 8) (bbpc 14) (evb 5)=0A= (cr0 0) (cr1 1) (cr2 2) (cr3 3)=0A= (cr4 4) (cr5 5) (cr6 6) (cr7 7)=0A= (cr8 8) (cr9 9) (cr10 10) (cr11 11)=0A= ***************=0A= *** 506,512 ****=0A= (define-hardware=0A= (name h-accums)=0A= (comment "accumulators")=0A= ! (attrs (MACH m32rx))=0A= (type register DI (2))=0A= (indices keyword "" ((a0 0) (a1 1)))=0A= ; get/set so a0 accesses are redirected to h-accum.=0A= --- 580,586 ----=0A= (define-hardware=0A= (name h-accums)=0A= (comment "accumulators")=0A= ! (attrs (MACH m32rx,m32r2))=0A= (type register DI (2))=0A= (indices keyword "" ((a0 0) (a1 1)))=0A= ; get/set so a0 accesses are redirected to h-accum.=0A= ***************=0A= *** 571,584 ****=0A= =20=20=0A= (dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8)= =0A= (dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16= )=0A= (dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4)= =0A= (dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)= =0A= (dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16= )=0A= =20=20=0A= ! (dnop imm1 "1 bit immediate" ((MACH m32rx) HASH-PREFIX) h-= uint f-imm1)=0A= ! (dnop accd "accumulator destination register" ((MACH m32rx)) h-a= ccums f-accd)=0A= ! (dnop accs "accumulator source register" ((MACH m32rx)) h-a= ccums f-accs)=0A= ! (dnop acc "accumulator reg (d)" ((MACH m32rx)) h-a= ccums f-acc)=0A= =20=20=0A= ; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.=0A= ; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX.=0A= --- 645,660 ----=0A= =20=20=0A= (dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8)= =0A= (dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16= )=0A= + (dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-uint f-uimm3)= =0A= (dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4)= =0A= (dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)= =0A= + (dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8)= =0A= (dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16= )=0A= =20=20=0A= ! (dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREF= IX) h-uint f-imm1)=0A= ! (dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) = h-accums f-accd)=0A= ! (dnop accs "accumulator source register" ((MACH m32rx,m32r2)) = h-accums f-accs)=0A= ! (dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) = h-accums f-acc)=0A= =20=20=0A= ; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.=0A= ; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX.=0A= ***************=0A= *** 676,681 ****=0A= --- 752,771 ----=0A= (comment "non-public m32rx insn")=0A= )=0A= =20=20=0A= + (define-attr=0A= + (for insn)=0A= + (type boolean)=0A= + (name SPECIAL_M32R)=0A= + (comment "non-public m32r insn")=0A= + )=0A= +=20=0A= + (define-attr=0A= + (for insn)=0A= + (type boolean)=0A= + (name SPECIAL_FLOAT)=0A= + (comment "floating point insn")=0A= + )=0A= +=20=0A= ; IDOC attribute for instruction documentation.=0A= =20=20=0A= (define-attr=0A= ***************=0A= *** 727,733 ****=0A= (+ OP1_4 dr simm8)=0A= (set dr (add dr simm8))=0A= ((m32r/d (unit u-exec))=0A= ! (m32rx (unit u-exec)))=0A= )=0A= =20=20=0A= (dni addv "addv"=0A= --- 817,824 ----=0A= (+ OP1_4 dr simm8)=0A= (set dr (add dr simm8))=0A= ((m32r/d (unit u-exec))=0A= ! (m32rx (unit u-exec))=0A= ! (m32r2 (unit u-exec)))=0A= )=0A= =20=20=0A= (dni addv "addv"=0A= ***************=0A= *** 766,772 ****=0A= (+ OP1_7 (f-r1 12) disp8)=0A= (if condbit (set pc disp8))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bc8r "relaxable bc8"=0A= --- 857,864 ----=0A= (+ OP1_7 (f-r1 12) disp8)=0A= (if condbit (set pc disp8))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bc8r "relaxable bc8"=0A= ***************=0A= *** 781,787 ****=0A= (+ OP1_15 (f-r1 12) disp24)=0A= (if condbit (set pc disp24))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bc24r "relaxable bc24"=0A= --- 873,880 ----=0A= (+ OP1_15 (f-r1 12) disp24)=0A= (if condbit (set pc disp24))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bc24r "relaxable bc24"=0A= ***************=0A= *** 796,802 ****=0A= (+ OP1_11 OP2_0 src1 src2 disp16)=0A= (if (eq src1 src2) (set pc disp16))=0A= ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32rx (unit u-cti) (unit u-cmp (cycles 0))))=0A= )=0A= =20=20=0A= (define-pmacro (cbranch sym comment op2-op comp-op)=0A= --- 889,896 ----=0A= (+ OP1_11 OP2_0 src1 src2 disp16)=0A= (if (eq src1 src2) (set pc disp16))=0A= ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32rx (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))=0A= )=0A= =20=20=0A= (define-pmacro (cbranch sym comment op2-op comp-op)=0A= ***************=0A= *** 805,811 ****=0A= (+ OP1_11 op2-op (f-r1 0) src2 disp16)=0A= (if (comp-op src2 (const WI 0)) (set pc disp16))=0A= ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32rx (unit u-cti) (unit u-cmp (cycles 0))))=0A= )=0A= )=0A= (cbranch beqz "beqz" OP2_8 eq)=0A= --- 899,906 ----=0A= (+ OP1_11 op2-op (f-r1 0) src2 disp16)=0A= (if (comp-op src2 (const WI 0)) (set pc disp16))=0A= ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32rx (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))=0A= )=0A= )=0A= (cbranch beqz "beqz" OP2_8 eq)=0A= ***************=0A= *** 824,830 ****=0A= (add (and pc (const -4)) (const 4)))=0A= (set pc disp8))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bl8r "relaxable bl8"=0A= --- 919,926 ----=0A= (add (and pc (const -4)) (const 4)))=0A= (set pc disp8))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bl8r "relaxable bl8"=0A= ***************=0A= *** 841,847 ****=0A= (set (reg h-gr 14) (add pc (const 4)))=0A= (set pc disp24))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bl24r "relaxable bl24"=0A= --- 937,944 ----=0A= (set (reg h-gr 14) (add pc (const 4)))=0A= (set pc disp24))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bl24r "relaxable bl24"=0A= ***************=0A= *** 851,857 ****=0A= )=0A= =20=20=0A= (dni bcl8 "bcl with 8 bit displacement"=0A= ! (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR))=0A= "bcl.s $disp8"=0A= (+ OP1_7 (f-r1 8) disp8)=0A= (if condbit=0A= --- 948,954 ----=0A= )=0A= =20=20=0A= (dni bcl8 "bcl with 8 bit displacement"=0A= ! (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))=0A= "bcl.s $disp8"=0A= (+ OP1_7 (f-r1 8) disp8)=0A= (if condbit=0A= ***************=0A= *** 860,887 ****=0A= (add (and pc (const -4))=0A= (const 4)))=0A= (set pc disp8)))=0A= ! ((m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bcl8r "relaxable bcl8"=0A= ! (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR))=0A= "bcl $disp8"=0A= (emit bcl8 disp8)=0A= )=0A= =20=20=0A= (dni bcl24 "bcl with 24 bit displacement"=0A= ! (COND-CTI (MACH m32rx) (IDOC BR))=0A= "bcl.l $disp24"=0A= (+ OP1_15 (f-r1 8) disp24)=0A= (if condbit=0A= (sequence ()=0A= (set (reg h-gr 14) (add pc (const 4)))=0A= (set pc disp24)))=0A= ! ((m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bcl24r "relaxable bcl24"=0A= ! (COND-CTI (MACH m32rx) RELAXED (IDOC BR))=0A= "bcl $disp24"=0A= (emit bcl24 disp24)=0A= )=0A= --- 957,986 ----=0A= (add (and pc (const -4))=0A= (const 4)))=0A= (set pc disp8)))=0A= ! ((m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bcl8r "relaxable bcl8"=0A= ! (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))= =0A= "bcl $disp8"=0A= (emit bcl8 disp8)=0A= )=0A= =20=20=0A= (dni bcl24 "bcl with 24 bit displacement"=0A= ! (COND-CTI (MACH m32rx,m32r2) (IDOC BR))=0A= "bcl.l $disp24"=0A= (+ OP1_15 (f-r1 8) disp24)=0A= (if condbit=0A= (sequence ()=0A= (set (reg h-gr 14) (add pc (const 4)))=0A= (set pc disp24)))=0A= ! ((m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bcl24r "relaxable bcl24"=0A= ! (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))=0A= "bcl $disp24"=0A= (emit bcl24 disp24)=0A= )=0A= ***************=0A= *** 892,898 ****=0A= (+ OP1_7 (f-r1 13) disp8)=0A= (if (not condbit) (set pc disp8))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bnc8r "relaxable bnc8"=0A= --- 991,998 ----=0A= (+ OP1_7 (f-r1 13) disp8)=0A= (if (not condbit) (set pc disp8))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bnc8r "relaxable bnc8"=0A= ***************=0A= *** 907,913 ****=0A= (+ OP1_15 (f-r1 13) disp24)=0A= (if (not condbit) (set pc disp24))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bnc24r "relaxable bnc24"=0A= --- 1007,1014 ----=0A= (+ OP1_15 (f-r1 13) disp24)=0A= (if (not condbit) (set pc disp24))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bnc24r "relaxable bnc24"=0A= ***************=0A= *** 922,928 ****=0A= (+ OP1_11 OP2_1 src1 src2 disp16)=0A= (if (ne src1 src2) (set pc disp16))=0A= ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32rx (unit u-cti) (unit u-cmp (cycles 0))))=0A= )=0A= =20=20=0A= (dni bra8 "bra with 8 bit displacement"=0A= --- 1023,1030 ----=0A= (+ OP1_11 OP2_1 src1 src2 disp16)=0A= (if (ne src1 src2) (set pc disp16))=0A= ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32rx (unit u-cti) (unit u-cmp (cycles 0)))=0A= ! (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))=0A= )=0A= =20=20=0A= (dni bra8 "bra with 8 bit displacement"=0A= ***************=0A= *** 931,937 ****=0A= (+ OP1_7 (f-r1 15) disp8)=0A= (set pc disp8)=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bra8r "relaxable bra8"=0A= --- 1033,1040 ----=0A= (+ OP1_7 (f-r1 15) disp8)=0A= (set pc disp8)=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bra8r "relaxable bra8"=0A= ***************=0A= *** 946,952 ****=0A= (+ OP1_15 (f-r1 15) disp24)=0A= (set pc disp24)=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bra24r "relaxable bra24"=0A= --- 1049,1056 ----=0A= (+ OP1_15 (f-r1 15) disp24)=0A= (set pc disp24)=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bra24r "relaxable bra24"=0A= ***************=0A= *** 956,962 ****=0A= )=0A= =20=20=0A= (dni bncl8 "bncl with 8 bit displacement"=0A= ! (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR))=0A= "bncl.s $disp8"=0A= (+ OP1_7 (f-r1 9) disp8)=0A= (if (not condbit)=20=0A= --- 1060,1066 ----=0A= )=0A= =20=20=0A= (dni bncl8 "bncl with 8 bit displacement"=0A= ! (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))=0A= "bncl.s $disp8"=0A= (+ OP1_7 (f-r1 9) disp8)=0A= (if (not condbit)=20=0A= ***************=0A= *** 965,992 ****=0A= (add (and pc (const -4))=0A= (const 4)))=0A= (set pc disp8)))=0A= ! ((m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bncl8r "relaxable bncl8"=0A= ! (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR))=0A= "bncl $disp8"=0A= (emit bncl8 disp8)=0A= )=0A= =20=20=0A= (dni bncl24 "bncl with 24 bit displacement"=0A= ! (COND-CTI (MACH m32rx) (IDOC BR))=0A= "bncl.l $disp24"=0A= (+ OP1_15 (f-r1 9) disp24)=0A= (if (not condbit)=0A= (sequence ()=0A= (set (reg h-gr 14) (add pc (const 4)))=0A= (set pc disp24)))=0A= ! ((m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bncl24r "relaxable bncl24"=0A= ! (COND-CTI (MACH m32rx) RELAXED (IDOC BR))=0A= "bncl $disp24"=0A= (emit bncl24 disp24)=0A= )=0A= --- 1069,1098 ----=0A= (add (and pc (const -4))=0A= (const 4)))=0A= (set pc disp8)))=0A= ! ((m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bncl8r "relaxable bncl8"=0A= ! (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))= =0A= "bncl $disp8"=0A= (emit bncl8 disp8)=0A= )=0A= =20=20=0A= (dni bncl24 "bncl with 24 bit displacement"=0A= ! (COND-CTI (MACH m32rx,m32r2) (IDOC BR))=0A= "bncl.l $disp24"=0A= (+ OP1_15 (f-r1 9) disp24)=0A= (if (not condbit)=0A= (sequence ()=0A= (set (reg h-gr 14) (add pc (const 4)))=0A= (set pc disp24)))=0A= ! ((m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dnmi bncl24r "relaxable bncl24"=0A= ! (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))=0A= "bncl $disp24"=0A= (emit bncl24 disp24)=0A= )=0A= ***************=0A= *** 997,1003 ****=0A= (+ OP1_0 OP2_4 src1 src2)=0A= (set condbit (lt src1 src2))=0A= ((m32r/d (unit u-cmp))=0A= ! (m32rx (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpi "cmpi"=0A= --- 1103,1110 ----=0A= (+ OP1_0 OP2_4 src1 src2)=0A= (set condbit (lt src1 src2))=0A= ((m32r/d (unit u-cmp))=0A= ! (m32rx (unit u-cmp))=0A= ! (m32r2 (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpi "cmpi"=0A= ***************=0A= *** 1006,1012 ****=0A= (+ OP1_8 (f-r1 0) OP2_4 src2 simm16)=0A= (set condbit (lt src2 simm16))=0A= ((m32r/d (unit u-cmp))=0A= ! (m32rx (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpu "cmpu"=0A= --- 1113,1120 ----=0A= (+ OP1_8 (f-r1 0) OP2_4 src2 simm16)=0A= (set condbit (lt src2 simm16))=0A= ((m32r/d (unit u-cmp))=0A= ! (m32rx (unit u-cmp))=0A= ! (m32r2 (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpu "cmpu"=0A= ***************=0A= *** 1015,1021 ****=0A= (+ OP1_0 OP2_5 src1 src2)=0A= (set condbit (ltu src1 src2))=0A= ((m32r/d (unit u-cmp))=0A= ! (m32rx (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpui "cmpui"=0A= --- 1123,1130 ----=0A= (+ OP1_0 OP2_5 src1 src2)=0A= (set condbit (ltu src1 src2))=0A= ((m32r/d (unit u-cmp))=0A= ! (m32rx (unit u-cmp))=0A= ! (m32r2 (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpui "cmpui"=0A= ***************=0A= *** 1024,1046 ****=0A= (+ OP1_8 (f-r1 0) OP2_5 src2 simm16)=0A= (set condbit (ltu src2 simm16))=0A= ((m32r/d (unit u-cmp))=0A= ! (m32rx (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpeq "cmpeq"=0A= ! ((MACH m32rx) (PIPE OS) (IDOC ALU))=0A= "cmpeq $src1,$src2"=0A= (+ OP1_0 OP2_6 src1 src2)=0A= (set condbit (eq src1 src2))=0A= ! ((m32rx (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpz "cmpz"=0A= ! ((MACH m32rx) (PIPE OS) (IDOC ALU))=0A= "cmpz $src2"=0A= (+ OP1_0 OP2_7 (f-r1 0) src2)=0A= (set condbit (eq src2 (const 0)))=0A= ! ((m32rx (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni div "div"=0A= --- 1133,1158 ----=0A= (+ OP1_8 (f-r1 0) OP2_5 src2 simm16)=0A= (set condbit (ltu src2 simm16))=0A= ((m32r/d (unit u-cmp))=0A= ! (m32rx (unit u-cmp))=0A= ! (m32r2 (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpeq "cmpeq"=0A= ! ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))=0A= "cmpeq $src1,$src2"=0A= (+ OP1_0 OP2_6 src1 src2)=0A= (set condbit (eq src1 src2))=0A= ! ((m32rx (unit u-cmp))=0A= ! (m32r2 (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni cmpz "cmpz"=0A= ! ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))=0A= "cmpz $src2"=0A= (+ OP1_0 OP2_7 (f-r1 0) src2)=0A= (set condbit (eq src2 (const 0)))=0A= ! ((m32rx (unit u-cmp))=0A= ! (m32r2 (unit u-cmp)))=0A= )=0A= =20=20=0A= (dni div "div"=0A= ***************=0A= *** 1049,1055 ****=0A= (+ OP1_9 OP2_0 dr sr (f-simm16 0))=0A= (if (ne sr (const 0)) (set dr (div dr sr)))=0A= ((m32r/d (unit u-exec (cycles 37)))=0A= ! (m32rx (unit u-exec (cycles 37))))=0A= )=0A= =20=20=0A= (dni divu "divu"=0A= --- 1161,1168 ----=0A= (+ OP1_9 OP2_0 dr sr (f-simm16 0))=0A= (if (ne sr (const 0)) (set dr (div dr sr)))=0A= ((m32r/d (unit u-exec (cycles 37)))=0A= ! (m32rx (unit u-exec (cycles 37)))=0A= ! (m32r2 (unit u-exec (cycles 37))))=0A= )=0A= =20=20=0A= (dni divu "divu"=0A= ***************=0A= *** 1058,1064 ****=0A= (+ OP1_9 OP2_1 dr sr (f-simm16 0))=0A= (if (ne sr (const 0)) (set dr (udiv dr sr)))=0A= ((m32r/d (unit u-exec (cycles 37)))=0A= ! (m32rx (unit u-exec (cycles 37))))=0A= )=0A= =20=20=0A= (dni rem "rem"=0A= --- 1171,1178 ----=0A= (+ OP1_9 OP2_1 dr sr (f-simm16 0))=0A= (if (ne sr (const 0)) (set dr (udiv dr sr)))=0A= ((m32r/d (unit u-exec (cycles 37)))=0A= ! (m32rx (unit u-exec (cycles 37)))=0A= ! (m32r2 (unit u-exec (cycles 37))))=0A= )=0A= =20=20=0A= (dni rem "rem"=0A= ***************=0A= *** 1068,1074 ****=0A= ; FIXME: Check rounding direction.=0A= (if (ne sr (const 0)) (set dr (mod dr sr)))=0A= ((m32r/d (unit u-exec (cycles 37)))=0A= ! (m32rx (unit u-exec (cycles 37))))=0A= )=0A= =20=20=0A= (dni remu "remu"=0A= --- 1182,1189 ----=0A= ; FIXME: Check rounding direction.=0A= (if (ne sr (const 0)) (set dr (mod dr sr)))=0A= ((m32r/d (unit u-exec (cycles 37)))=0A= ! (m32rx (unit u-exec (cycles 37)))=0A= ! (m32r2 (unit u-exec (cycles 37))))=0A= )=0A= =20=20=0A= (dni remu "remu"=0A= ***************=0A= *** 1078,1108 ****=0A= ; FIXME: Check rounding direction.=0A= (if (ne sr (const 0)) (set dr (umod dr sr)))=0A= ((m32r/d (unit u-exec (cycles 37)))=0A= ! (m32rx (unit u-exec (cycles 37))))=0A= )=0A= =20=20=0A= (dni divh "divh"=0A= ! ((MACH m32rx) (IDOC ALU))=0A= "divh $dr,$sr"=0A= (+ OP1_9 OP2_0 dr sr (f-simm16 #x10))=0A= (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))=0A= ! ((m32rx (unit u-exec (cycles 21))))=0A= )=0A= =20=20=0A= (dni jc "jc"=0A= ! (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR))=0A= "jc $sr"=0A= (+ OP1_1 (f-r1 12) OP2_12 sr)=0A= (if condbit (set pc (and sr (const -4))))=0A= ! ((m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dni jnc "jnc"=0A= ! (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR))=0A= "jnc $sr"=0A= (+ OP1_1 (f-r1 13) OP2_12 sr)=0A= (if (not condbit) (set pc (and sr (const -4))))=0A= ! ((m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dni jl "jl"=0A= --- 1193,1287 ----=0A= ; FIXME: Check rounding direction.=0A= (if (ne sr (const 0)) (set dr (umod dr sr)))=0A= ((m32r/d (unit u-exec (cycles 37)))=0A= ! (m32rx (unit u-exec (cycles 37)))=0A= ! (m32r2 (unit u-exec (cycles 37))))=0A= ! )=0A= !=20=0A= ! (dni remh "remh"=0A= ! ((MACH m32r2))=0A= ! "remh $dr,$sr"=0A= ! (+ OP1_9 OP2_2 dr sr (f-simm16 #x10))=0A= ! ; FIXME: Check rounding direction.=0A= ! (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))=0A= ! ((m32r2 (unit u-exec (cycles 21))))=0A= ! )=0A= !=20=0A= ! (dni remuh "remuh"=0A= ! ((MACH m32r2))=0A= ! "remuh $dr,$sr"=0A= ! (+ OP1_9 OP2_3 dr sr (f-simm16 #x10))=0A= ! ; FIXME: Check rounding direction.=0A= ! (if (ne sr (const 0)) (set dr (umod dr sr)))=0A= ! ((m32r2 (unit u-exec (cycles 21))))=0A= ! )=0A= !=20=0A= ! (dni remb "remb"=0A= ! ((MACH m32r2))=0A= ! "remb $dr,$sr"=0A= ! (+ OP1_9 OP2_2 dr sr (f-simm16 #x18))=0A= ! ; FIXME: Check rounding direction.=0A= ! (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))=0A= ! ((m32r2 (unit u-exec (cycles 21))))=0A= ! )=0A= !=20=0A= ! (dni remub "remub"=0A= ! ((MACH m32r2))=0A= ! "remub $dr,$sr"=0A= ! (+ OP1_9 OP2_3 dr sr (f-simm16 #x18))=0A= ! ; FIXME: Check rounding direction.=0A= ! (if (ne sr (const 0)) (set dr (umod dr sr)))=0A= ! ((m32r2 (unit u-exec (cycles 21))))=0A= ! )=0A= !=20=0A= ! (dni divuh "divuh"=0A= ! ((MACH m32r2))=0A= ! "divuh $dr,$sr"=0A= ! (+ OP1_9 OP2_1 dr sr (f-simm16 #x10))=0A= ! (if (ne sr (const 0)) (set dr (udiv dr sr)))=0A= ! ((m32r2 (unit u-exec (cycles 21))))=0A= ! )=0A= !=20=0A= ! (dni divb "divb"=0A= ! ((MACH m32r2))=0A= ! "divb $dr,$sr"=0A= ! (+ OP1_9 OP2_0 dr sr (f-simm16 #x18))=0A= ! (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))=0A= ! ((m32r2 (unit u-exec (cycles 21))))=0A= ! )=0A= !=20=0A= ! (dni divub "divub"=0A= ! ((MACH m32r2))=0A= ! "divub $dr,$sr"=0A= ! (+ OP1_9 OP2_1 dr sr (f-simm16 #x18))=0A= ! (if (ne sr (const 0)) (set dr (udiv dr sr)))=0A= ! ((m32r2 (unit u-exec (cycles 21))))=0A= )=0A= =20=20=0A= (dni divh "divh"=0A= ! ((MACH m32rx,m32r2) (IDOC ALU))=0A= "divh $dr,$sr"=0A= (+ OP1_9 OP2_0 dr sr (f-simm16 #x10))=0A= (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))=0A= ! ((m32rx (unit u-exec (cycles 21)))=0A= ! (m32r2 (unit u-exec (cycles 21))))=0A= )=0A= =20=20=0A= (dni jc "jc"=0A= ! (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))=0A= "jc $sr"=0A= (+ OP1_1 (f-r1 12) OP2_12 sr)=0A= (if condbit (set pc (and sr (const -4))))=0A= ! ((m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dni jnc "jnc"=0A= ! (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))=0A= "jnc $sr"=0A= (+ OP1_1 (f-r1 13) OP2_12 sr)=0A= (if (not condbit) (set pc (and sr (const -4))))=0A= ! ((m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dni jl "jl"=0A= ***************=0A= *** 1114,1120 ****=0A= (add (and pc (const -4)) (const 4)))=0A= (set pc (and sr (const -4))))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (dni jmp "jmp"=0A= --- 1293,1300 ----=0A= (add (and pc (const -4)) (const 4)))=0A= (set pc (and sr (const -4))))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (dni jmp "jmp"=0A= ***************=0A= *** 1136,1142 ****=0A= ; (add WI (and WI pc (const WI -4)) (const WI 4))))=0A= ; (set WI pc sr))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti)))=0A= )=0A= =20=20=0A= (define-pmacro (no-ext-expr mode expr) expr)=0A= --- 1316,1323 ----=0A= ; (add WI (and WI pc (const WI -4)) (const WI 4))))=0A= ; (set WI pc sr))=0A= ((m32r/d (unit u-cti))=0A= ! (m32rx (unit u-cti))=0A= ! (m32r2 (unit u-cti)))=0A= )=0A= =20=20=0A= (define-pmacro (no-ext-expr mode expr) expr)=0A= ***************=0A= *** 1151,1157 ****=0A= (+ OP1_2 op2-op dr sr)=0A= (set dr (ext-op WI (mem mode sr)))=0A= ((m32r/d (unit u-load))=0A= ! (m32rx (unit u-load)))=0A= )=0A= (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")=0A= (NO-DIS (PIPE O) (IDOC MEM))=0A= --- 1332,1339 ----=0A= (+ OP1_2 op2-op dr sr)=0A= (set dr (ext-op WI (mem mode sr)))=0A= ((m32r/d (unit u-load))=0A= ! (m32rx (unit u-load))=0A= ! (m32r2 (unit u-load)))=0A= )=0A= (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")=0A= (NO-DIS (PIPE O) (IDOC MEM))=0A= ***************=0A= *** 1163,1169 ****=0A= (+ OP1_10 op2-op dr sr slo16)=0A= (set dr (ext-op WI (mem mode (add sr slo16))))=0A= ((m32r/d (unit u-load (cycles 2)))=0A= ! (m32rx (unit u-load (cycles 2))))=0A= )=0A= (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")=0A= (NO-DIS (IDOC MEM))=0A= --- 1345,1352 ----=0A= (+ OP1_10 op2-op dr sr slo16)=0A= (set dr (ext-op WI (mem mode (add sr slo16))))=0A= ((m32r/d (unit u-load (cycles 2)))=0A= ! (m32rx (unit u-load (cycles 2)))=0A= ! (m32r2 (unit u-load (cycles 2))))=0A= )=0A= (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")=0A= (NO-DIS (IDOC MEM))=0A= ***************=0A= *** 1199,1204 ****=0A= --- 1382,1389 ----=0A= (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (c= onst 1))))=0A= (m32rx (unit u-load)=0A= (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (co= nst 1))))=0A= + (m32r2 (unit u-load)=0A= + (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (co= nst 1))))=0A= )=0A= )=0A= =20=20=0A= ***************=0A= *** 1254,1260 ****=0A= (set (reg h-lock) (const BI 1))=0A= (set dr (mem WI sr)))=0A= ((m32r/d (unit u-load))=0A= ! (m32rx (unit u-load)))=0A= )=0A= =20=20=0A= (dni machi "machi"=0A= --- 1439,1446 ----=0A= (set (reg h-lock) (const BI 1))=0A= (set dr (mem WI sr)))=0A= ((m32r/d (unit u-load))=0A= ! (m32rx (unit u-load))=0A= ! (m32r2 (unit u-load)))=0A= )=0A= =20=20=0A= (dni machi "machi"=0A= ***************=0A= *** 1281,1287 ****=0A= )=0A= =20=20=0A= (dni machi-a "machi-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "machi $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 4) src2)=0A= (set acc=0A= --- 1467,1473 ----=0A= )=0A= =20=20=0A= (dni machi-a "machi-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "machi $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 4) src2)=0A= (set acc=0A= ***************=0A= *** 1294,1300 ****=0A= (ext DI (trunc HI (sra WI src2 (const 16))))))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dni maclo "maclo"=0A= --- 1480,1487 ----=0A= (ext DI (trunc HI (sra WI src2 (const 16))))))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dni maclo "maclo"=0A= ***************=0A= *** 1315,1321 ****=0A= )=0A= =20=20=0A= (dni maclo-a "maclo-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "maclo $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 5) src2)=0A= (set acc=0A= --- 1502,1508 ----=0A= )=0A= =20=20=0A= (dni maclo-a "maclo-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "maclo $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 5) src2)=0A= (set acc=0A= ***************=0A= *** 1328,1334 ****=0A= (ext DI (trunc HI src2))))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dni macwhi "macwhi"=0A= --- 1515,1522 ----=0A= (ext DI (trunc HI src2))))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dni macwhi "macwhi"=0A= ***************=0A= *** 1349,1355 ****=0A= )=0A= =20=20=0A= (dni macwhi-a "macwhi-a"=0A= ! ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC))=0A= "macwhi $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 6) src2)=0A= ; Note that this doesn't do the sign extension, which is correct.=0A= --- 1537,1543 ----=0A= )=0A= =20=20=0A= (dni macwhi-a "macwhi-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))=0A= "macwhi $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 6) src2)=0A= ; Note that this doesn't do the sign extension, which is correct.=0A= ***************=0A= *** 1357,1363 ****=0A= (add acc=0A= (mul (ext DI src1)=0A= (ext DI (trunc HI (sra src2 (const 16)))))))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dni macwlo "macwlo"=0A= --- 1545,1552 ----=0A= (add acc=0A= (mul (ext DI src1)=0A= (ext DI (trunc HI (sra src2 (const 16)))))))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dni macwlo "macwlo"=0A= ***************=0A= *** 1378,1384 ****=0A= )=0A= =20=20=0A= (dni macwlo-a "macwlo-a"=0A= ! ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC))=0A= "macwlo $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 7) src2)=0A= ; Note that this doesn't do the sign extension, which is correct.=0A= --- 1567,1573 ----=0A= )=0A= =20=20=0A= (dni macwlo-a "macwlo-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))=0A= "macwlo $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 7) src2)=0A= ; Note that this doesn't do the sign extension, which is correct.=0A= ***************=0A= *** 1386,1392 ****=0A= (add acc=0A= (mul (ext DI src1)=0A= (ext DI (trunc HI src2)))))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mul "mul"=0A= --- 1575,1582 ----=0A= (add acc=0A= (mul (ext DI src1)=0A= (ext DI (trunc HI src2)))))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mul "mul"=0A= ***************=0A= *** 1395,1401 ****=0A= (+ OP1_1 OP2_6 dr sr)=0A= (set dr (mul dr sr))=0A= ((m32r/d (unit u-exec (cycles 4)))=0A= ! (m32rx (unit u-exec (cycles 4))))=0A= )=0A= =20=20=0A= (dni mulhi "mulhi"=0A= --- 1585,1592 ----=0A= (+ OP1_1 OP2_6 dr sr)=0A= (set dr (mul dr sr))=0A= ((m32r/d (unit u-exec (cycles 4)))=0A= ! (m32rx (unit u-exec (cycles 4)))=0A= ! (m32r2 (unit u-exec (cycles 4))))=0A= )=0A= =20=20=0A= (dni mulhi "mulhi"=0A= ***************=0A= *** 1414,1420 ****=0A= )=0A= =20=20=0A= (dni mulhi-a "mulhi-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC ACCUM))=0A= "mulhi $src1,$src2,$acc"=0A= (+ OP1_3 (f-op23 0) src1 acc src2)=0A= (set acc=0A= --- 1605,1611 ----=0A= )=0A= =20=20=0A= (dni mulhi-a "mulhi-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))=0A= "mulhi $src1,$src2,$acc"=0A= (+ OP1_3 (f-op23 0) src1 acc src2)=0A= (set acc=0A= ***************=0A= *** 1425,1431 ****=0A= (ext DI (trunc HI (sra WI src2 (const 16)))))=0A= (const 16))=0A= (const 16)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mullo "mullo"=0A= --- 1616,1623 ----=0A= (ext DI (trunc HI (sra WI src2 (const 16)))))=0A= (const 16))=0A= (const 16)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mullo "mullo"=0A= ***************=0A= *** 1444,1450 ****=0A= )=0A= =20=20=0A= (dni mullo-a "mullo-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC ACCUM))=0A= "mullo $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 1) src2)=0A= (set acc=0A= --- 1636,1642 ----=0A= )=0A= =20=20=0A= (dni mullo-a "mullo-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))=0A= "mullo $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 1) src2)=0A= (set acc=0A= ***************=0A= *** 1455,1461 ****=0A= (ext DI (trunc HI src2)))=0A= (const 16))=0A= (const 16)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mulwhi "mulwhi"=0A= --- 1647,1654 ----=0A= (ext DI (trunc HI src2)))=0A= (const 16))=0A= (const 16)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mulwhi "mulwhi"=0A= ***************=0A= *** 1474,1487 ****=0A= )=0A= =20=20=0A= (dni mulwhi-a "mulwhi-a"=0A= ! ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM))=0A= "mulwhi $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 2) src2)=0A= ; Note that this doesn't do the sign extension, which is correct.=0A= (set acc=0A= (mul (ext DI src1)=0A= (ext DI (trunc HI (sra src2 (const 16))))))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mulwlo "mulwlo"=0A= --- 1667,1681 ----=0A= )=0A= =20=20=0A= (dni mulwhi-a "mulwhi-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))=0A= "mulwhi $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 2) src2)=0A= ; Note that this doesn't do the sign extension, which is correct.=0A= (set acc=0A= (mul (ext DI src1)=0A= (ext DI (trunc HI (sra src2 (const 16))))))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mulwlo "mulwlo"=0A= ***************=0A= *** 1500,1513 ****=0A= )=0A= =20=20=0A= (dni mulwlo-a "mulwlo-a"=0A= ! ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM))=0A= "mulwlo $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 3) src2)=0A= ; Note that this doesn't do the sign extension, which is correct.=0A= (set acc=0A= (mul (ext DI src1)=0A= (ext DI (trunc HI src2))))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mv "mv"=0A= --- 1694,1708 ----=0A= )=0A= =20=20=0A= (dni mulwlo-a "mulwlo-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))=0A= "mulwlo $src1,$src2,$acc"=0A= (+ OP1_3 src1 acc (f-op23 3) src2)=0A= ; Note that this doesn't do the sign extension, which is correct.=0A= (set acc=0A= (mul (ext DI src1)=0A= (ext DI (trunc HI src2))))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dni mv "mv"=0A= ***************=0A= *** 1527,1537 ****=0A= )=0A= =20=20=0A= (dni mvfachi-a "mvfachi-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC ACCUM))=0A= "mvfachi $dr,$accs"=0A= (+ OP1_5 dr OP2_15 accs (f-op3 0))=0A= (set dr (trunc WI (sra DI accs (const 32))))=0A= ! ((m32rx (unit u-exec (cycles 2))))=0A= )=0A= =20=20=0A= (dni mvfaclo "mvfaclo"=0A= --- 1722,1733 ----=0A= )=0A= =20=20=0A= (dni mvfachi-a "mvfachi-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))=0A= "mvfachi $dr,$accs"=0A= (+ OP1_5 dr OP2_15 accs (f-op3 0))=0A= (set dr (trunc WI (sra DI accs (const 32))))=0A= ! ((m32rx (unit u-exec (cycles 2)))=0A= ! (m32r2 (unit u-exec (cycles 2))))=0A= )=0A= =20=20=0A= (dni mvfaclo "mvfaclo"=0A= ***************=0A= *** 1543,1553 ****=0A= )=0A= =20=20=0A= (dni mvfaclo-a "mvfaclo-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC ACCUM))=0A= "mvfaclo $dr,$accs"=0A= (+ OP1_5 dr OP2_15 accs (f-op3 1))=0A= (set dr (trunc WI accs))=0A= ! ((m32rx (unit u-exec (cycles 2))))=0A= )=0A= =20=20=0A= (dni mvfacmi "mvfacmi"=0A= --- 1739,1750 ----=0A= )=0A= =20=20=0A= (dni mvfaclo-a "mvfaclo-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))=0A= "mvfaclo $dr,$accs"=0A= (+ OP1_5 dr OP2_15 accs (f-op3 1))=0A= (set dr (trunc WI accs))=0A= ! ((m32rx (unit u-exec (cycles 2)))=0A= ! (m32r2 (unit u-exec (cycles 2))))=0A= )=0A= =20=20=0A= (dni mvfacmi "mvfacmi"=0A= ***************=0A= *** 1559,1569 ****=0A= )=0A= =20=20=0A= (dni mvfacmi-a "mvfacmi-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC ACCUM))=0A= "mvfacmi $dr,$accs"=0A= (+ OP1_5 dr OP2_15 accs (f-op3 2))=0A= (set dr (trunc WI (sra DI accs (const 16))))=0A= ! ((m32rx (unit u-exec (cycles 2))))=0A= )=0A= =20=20=0A= (dni mvfc "mvfc"=0A= --- 1756,1767 ----=0A= )=0A= =20=20=0A= (dni mvfacmi-a "mvfacmi-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))=0A= "mvfacmi $dr,$accs"=0A= (+ OP1_5 dr OP2_15 accs (f-op3 2))=0A= (set dr (trunc WI (sra DI accs (const 16))))=0A= ! ((m32rx (unit u-exec (cycles 2)))=0A= ! (m32r2 (unit u-exec (cycles 2))))=0A= )=0A= =20=20=0A= (dni mvfc "mvfc"=0A= ***************=0A= *** 1586,1599 ****=0A= )=0A= =20=20=0A= (dni mvtachi-a "mvtachi-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC ACCUM))=0A= "mvtachi $src1,$accs"=0A= (+ OP1_5 src1 OP2_7 accs (f-op3 0))=0A= (set accs=0A= (or DI=0A= (and DI accs (const DI #xffffffff))=0A= (sll DI (ext DI src1) (const 32))))=0A= ! ((m32rx (unit u-exec (in sr src1))))=0A= )=0A= =20=20=0A= (dni mvtaclo "mvtaclo"=0A= --- 1784,1798 ----=0A= )=0A= =20=20=0A= (dni mvtachi-a "mvtachi-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))=0A= "mvtachi $src1,$accs"=0A= (+ OP1_5 src1 OP2_7 accs (f-op3 0))=0A= (set accs=0A= (or DI=0A= (and DI accs (const DI #xffffffff))=0A= (sll DI (ext DI src1) (const 32))))=0A= ! ((m32rx (unit u-exec (in sr src1)))=0A= ! (m32r2 (unit u-exec (in sr src1))))=0A= )=0A= =20=20=0A= (dni mvtaclo "mvtaclo"=0A= ***************=0A= *** 1608,1621 ****=0A= )=0A= =20=20=0A= (dni mvtaclo-a "mvtaclo-a"=0A= ! ((MACH m32rx) (PIPE S) (IDOC ACCUM))=0A= "mvtaclo $src1,$accs"=0A= (+ OP1_5 src1 OP2_7 accs (f-op3 1))=0A= (set accs=0A= (or DI=0A= (and DI accs (const DI #xffffffff00000000))=0A= (zext DI src1)))=0A= ! ((m32rx (unit u-exec (in sr src1))))=0A= )=0A= =20=20=0A= (dni mvtc "mvtc"=0A= --- 1807,1821 ----=0A= )=0A= =20=20=0A= (dni mvtaclo-a "mvtaclo-a"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))=0A= "mvtaclo $src1,$accs"=0A= (+ OP1_5 src1 OP2_7 accs (f-op3 1))=0A= (set accs=0A= (or DI=0A= (and DI accs (const DI #xffffffff00000000))=0A= (zext DI src1)))=0A= ! ((m32rx (unit u-exec (in sr src1)))=0A= ! (m32r2 (unit u-exec (in sr src1))))=0A= )=0A= =20=20=0A= (dni mvtc "mvtc"=0A= ***************=0A= *** 1642,1648 ****=0A= ; FIXME: quick hack: parallel nops don't contribute to cycle count.= =0A= ; Other kinds of nops do however (which we currently ignore).=0A= ((m32r/d (unit u-exec (cycles 0)))=0A= ! (m32rx (unit u-exec (cycles 0))))=0A= )=0A= =20=20=0A= (dni not "not"=0A= --- 1842,1849 ----=0A= ; FIXME: quick hack: parallel nops don't contribute to cycle count.= =0A= ; Other kinds of nops do however (which we currently ignore).=0A= ((m32r/d (unit u-exec (cycles 0)))=0A= ! (m32rx (unit u-exec (cycles 0)))=0A= ! (m32r2 (unit u-exec (cycles 0))))=0A= )=0A= =20=20=0A= (dni not "not"=0A= ***************=0A= *** 1672,1678 ****=0A= )=0A= =20=20=0A= (dni rac-dsi "rac-dsi"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "rac $accd,$accs,$imm1"=0A= (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)=0A= (sequence ((DI tmp1))=0A= --- 1873,1879 ----=0A= )=0A= =20=20=0A= (dni rac-dsi "rac-dsi"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "rac $accd,$accs,$imm1"=0A= (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)=0A= (sequence ((DI tmp1))=0A= ***************=0A= *** 1686,1702 ****=0A= (const DI #xffff800000000000))=0A= (else (and tmp1 (const DI #xffffffffffff0000)))))=0A= )=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dnmi rac-d "rac-d"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "rac $accd"=0A= (emit rac-dsi accd (f-accs 0) (f-imm1 0))=0A= )=0A= =20=20=0A= (dnmi rac-ds "rac-ds"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "rac $accd,$accs"=0A= (emit rac-dsi accd accs (f-imm1 0))=0A= )=0A= --- 1887,1904 ----=0A= (const DI #xffff800000000000))=0A= (else (and tmp1 (const DI #xffffffffffff0000)))))=0A= )=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dnmi rac-d "rac-d"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "rac $accd"=0A= (emit rac-dsi accd (f-accs 0) (f-imm1 0))=0A= )=0A= =20=20=0A= (dnmi rac-ds "rac-ds"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "rac $accd,$accs"=0A= (emit rac-dsi accd accs (f-imm1 0))=0A= )=0A= ***************=0A= *** 1730,1736 ****=0A= )=0A= =20=20=0A= (dni rach-dsi "rach-dsi"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "rach $accd,$accs,$imm1"=0A= (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)=0A= (sequence ((DI tmp1))=0A= --- 1932,1938 ----=0A= )=0A= =20=20=0A= (dni rach-dsi "rach-dsi"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "rach $accd,$accs,$imm1"=0A= (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)=0A= (sequence ((DI tmp1))=0A= ***************=0A= *** 1744,1760 ****=0A= (const DI #xffff800000000000))=0A= (else (and tmp1 (const DI #xffffffff00000000)))))=0A= )=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= (dnmi rach-d "rach-d"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "rach $accd"=0A= (emit rach-dsi accd (f-accs 0) (f-imm1 0))=0A= )=0A= =20=20=0A= (dnmi rach-ds "rach-ds"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "rach $accd,$accs"=0A= (emit rach-dsi accd accs (f-imm1 0))=0A= )=0A= --- 1946,1963 ----=0A= (const DI #xffff800000000000))=0A= (else (and tmp1 (const DI #xffffffff00000000)))))=0A= )=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= (dnmi rach-d "rach-d"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "rach $accd"=0A= (emit rach-dsi accd (f-accs 0) (f-imm1 0))=0A= )=0A= =20=20=0A= (dnmi rach-ds "rach-ds"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "rach $accd,$accs"=0A= (emit rach-dsi accd accs (f-imm1 0))=0A= )=0A= ***************=0A= *** 1786,1792 ****=0A= =20=20=0A= (define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)=0A= (begin=0A= ! (dni sym sym ((PIPE O) (IDOC ALU))=0A= (.str sym " $dr,$sr")=0A= (+ OP1_1 op2-r-op dr sr)=0A= (set dr (sem-op dr (and sr (const 31))))=0A= --- 1989,1995 ----=0A= =20=20=0A= (define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)=0A= (begin=0A= ! (dni sym sym ((PIPE O_OS) (IDOC ALU))=0A= (.str sym " $dr,$sr")=0A= (+ OP1_1 op2-r-op dr sr)=0A= (set dr (sem-op dr (and sr (const 31))))=0A= ***************=0A= *** 1798,1804 ****=0A= (set dr (sem-op sr (and WI simm16 (const 31))))=0A= ()=0A= )=0A= ! (dni (.sym sym "i") sym ((PIPE O) (IDOC ALU))=0A= (.str sym "i $dr,$uimm5")=0A= (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)=0A= (set dr (sem-op dr uimm5))=0A= --- 2001,2007 ----=0A= (set dr (sem-op sr (and WI simm16 (const 31))))=0A= ()=0A= )=0A= ! (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))=0A= (.str sym "i $dr,$uimm5")=0A= (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)=0A= (set dr (sem-op dr uimm5))=0A= ***************=0A= *** 1818,1824 ****=0A= (+ OP1_2 op2-op src1 src2)=0A= (set mode (mem mode src2) src1)=0A= ((m32r/d (unit u-store (cycles 1)))=0A= ! (m32rx (unit u-store (cycles 1))))=0A= )=0A= (dnmi (.sym st suffix "-2") (.str "st" suffix "-2")=0A= (NO-DIS (PIPE O) (IDOC MEM))=0A= --- 2021,2028 ----=0A= (+ OP1_2 op2-op src1 src2)=0A= (set mode (mem mode src2) src1)=0A= ((m32r/d (unit u-store (cycles 1)))=0A= ! (m32rx (unit u-store (cycles 1)))=0A= ! (m32r2 (unit u-store (cycles 1))))=0A= )=0A= (dnmi (.sym st suffix "-2") (.str "st" suffix "-2")=0A= (NO-DIS (PIPE O) (IDOC MEM))=0A= ***************=0A= *** 1830,1836 ****=0A= (+ OP1_10 op2-op src1 src2 slo16)=0A= (set mode (mem mode (add src2 slo16)) src1)=0A= ((m32r/d (unit u-store (cycles 2)))=0A= ! (m32rx (unit u-store (cycles 2))))=0A= )=0A= (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")=0A= (NO-DIS (IDOC MEM))=0A= --- 2034,2041 ----=0A= (+ OP1_10 op2-op src1 src2 slo16)=0A= (set mode (mem mode (add src2 slo16)) src1)=0A= ((m32r/d (unit u-store (cycles 2)))=0A= ! (m32rx (unit u-store (cycles 2)))=0A= ! (m32r2 (unit u-store (cycles 2))))=0A= )=0A= (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")=0A= (NO-DIS (IDOC MEM))=0A= ***************=0A= *** 1855,1860 ****=0A= --- 2060,2099 ----=0A= (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= (m32rx (unit u-store)=0A= (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= + (m32r2 (unit u-store)=0A= + (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= + )=0A= + )=0A= +=20=0A= + (dni sth-plus "sth+"=0A= + ((MACH m32rx,m32r2) (PIPE O) SPECIAL)=0A= + "sth $src1,@$src2+"=0A= + (+ OP1_2 OP2_3 src1 src2)=0A= + ; This has to be coded carefully to avoid an "earlyclobber" of src2.= =0A= + (sequence ((HI new-src2))=0A= + (set (mem HI new-src2) src1)=0A= + (set new-src2 (add src2 (const 2)))=0A= + (set src2 new-src2))=0A= + ((m32rx (unit u-store)=0A= + (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= + (m32r2 (unit u-store)=0A= + (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= + )=0A= + )=0A= +=20=0A= + (dni stb-plus "stb+"=0A= + ((MACH m32rx,m32r2) (PIPE O) SPECIAL)=0A= + "stb $src1,@$src2+"=0A= + (+ OP1_2 OP2_1 src1 src2)=0A= + ; This has to be coded carefully to avoid an "earlyclobber" of src2.= =0A= + (sequence ((QI new-src2))=0A= + (set (mem QI new-src2) src1)=0A= + (set new-src2 (add src2 (const 1)))=0A= + (set src2 new-src2))=0A= + ((m32rx (unit u-store)=0A= + (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= + (m32r2 (unit u-store)=0A= + (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= )=0A= )=0A= =20=20=0A= ***************=0A= *** 1875,1884 ****=0A= (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= (m32rx (unit u-store)=0A= (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= )=0A= )=0A= =20=20=0A= ! (dnmi push "push" ((IDOC MEM))=0A= "push $src1"=0A= (emit st-minus src1 (src2 15)) ; "st %0,@-sp"=0A= )=0A= --- 2114,2125 ----=0A= (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= (m32rx (unit u-store)=0A= (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= + (m32r2 (unit u-store)=0A= + (unit u-exec (in dr src2) (out dr src2) (cycles 0)))=0A= )=0A= )=0A= =20=20=0A= ! (dnmi push "push" ((PIPE O) (IDOC MEM))=0A= "push $src1"=0A= (emit st-minus src1 (src2 15)) ; "st %0,@-sp"=0A= )=0A= ***************=0A= *** 1943,1954 ****=0A= (set (mem WI src2) src1))=0A= (set (reg h-lock) (const BI 0)))=0A= ((m32r/d (unit u-load))=0A= ! (m32rx (unit u-load)))=0A= )=0A= =20=20=0A= ; Saturate into byte.=0A= (dni satb "satb"=0A= ! ((MACH m32rx) (IDOC ALU))=0A= "satb $dr,$sr"=0A= (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))=0A= (set dr=0A= --- 2184,2196 ----=0A= (set (mem WI src2) src1))=0A= (set (reg h-lock) (const BI 0)))=0A= ((m32r/d (unit u-load))=0A= ! (m32rx (unit u-load))=0A= ! (m32r2 (unit u-load)))=0A= )=0A= =20=20=0A= ; Saturate into byte.=0A= (dni satb "satb"=0A= ! ((MACH m32rx,m32r2) (IDOC ALU))=0A= "satb $dr,$sr"=0A= (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))=0A= (set dr=0A= ***************=0A= *** 1962,1968 ****=0A= =20=20=0A= ; Saturate into half word.=0A= (dni sath "sath"=0A= ! ((MACH m32rx) (IDOC ALU))=0A= "sath $dr,$sr"=0A= (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))=0A= (set dr=0A= --- 2204,2210 ----=0A= =20=20=0A= ; Saturate into half word.=0A= (dni sath "sath"=0A= ! ((MACH m32rx,m32r2) (IDOC ALU))=0A= "sath $dr,$sr"=0A= (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))=0A= (set dr=0A= ***************=0A= *** 1975,1981 ****=0A= =20=20=0A= ; Saturate word.=0A= (dni sat "sat"=0A= ! ((MACH m32rx) SPECIAL (IDOC ALU))=0A= "sat $dr,$sr"=0A= (+ OP1_8 dr OP2_6 sr (f-uimm16 0))=0A= (set dr=0A= --- 2217,2223 ----=0A= =20=20=0A= ; Saturate word.=0A= (dni sat "sat"=0A= ! ((MACH m32rx,m32r2) SPECIAL (IDOC ALU))=0A= "sat $dr,$sr"=0A= (+ OP1_8 dr OP2_6 sr (f-uimm16 0))=0A= (set dr=0A= ***************=0A= *** 1990,1996 ****=0A= ; Parallel compare byte zeros.=0A= ; Set C bit in condition register if any byte in source register is zero.= =0A= (dni pcmpbz "pcmpbz"=0A= ! ((MACH m32rx) (PIPE OS) SPECIAL (IDOC ALU))=0A= "pcmpbz $src2"=0A= (+ OP1_0 (f-r1 3) OP2_7 src2)=0A= (set condbit=0A= --- 2232,2238 ----=0A= ; Parallel compare byte zeros.=0A= ; Set C bit in condition register if any byte in source register is zero.= =0A= (dni pcmpbz "pcmpbz"=0A= ! ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))=0A= "pcmpbz $src2"=0A= (+ OP1_0 (f-r1 3) OP2_7 src2)=0A= (set condbit=0A= ***************=0A= *** 2000,2022 ****=0A= ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))=0A= ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))=0A= (else (const BI 0))))=0A= ! ((m32rx (unit u-cmp)))=0A= )=0A= =20=20=0A= ; Add accumulators=0A= (dni sadd "sadd"=0A= ! ((MACH m32rx) (PIPE S) (IDOC ACCUM))=0A= "sadd"=0A= (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))=0A= (set (reg h-accums 0)=0A= (add (sra (reg h-accums 1) (const 16))=0A= (reg h-accums 0)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= ; Multiply and add into accumulator 1=0A= (dni macwu1 "macwu1"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "macwu1 $src1,$src2"=0A= (+ OP1_5 src1 OP2_11 src2)=0A= (set (reg h-accums 1)=0A= --- 2242,2266 ----=0A= ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))=0A= ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))=0A= (else (const BI 0))))=0A= ! ((m32rx (unit u-cmp))=0A= ! (m32r2 (unit u-cmp)))=0A= )=0A= =20=20=0A= ; Add accumulators=0A= (dni sadd "sadd"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))=0A= "sadd"=0A= (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))=0A= (set (reg h-accums 0)=0A= (add (sra (reg h-accums 1) (const 16))=0A= (reg h-accums 0)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= ; Multiply and add into accumulator 1=0A= (dni macwu1 "macwu1"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "macwu1 $src1,$src2"=0A= (+ OP1_5 src1 OP2_11 src2)=0A= (set (reg h-accums 1)=0A= ***************=0A= *** 2029,2040 ****=0A= (ext DI (and src2 (const #xffff)))))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= ; Multiply and subtract from accumulator 0=0A= (dni msblo "msblo"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "msblo $src1,$src2"=0A= (+ OP1_5 src1 OP2_13 src2)=0A= (set accum=0A= --- 2273,2285 ----=0A= (ext DI (and src2 (const #xffff)))))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= ; Multiply and subtract from accumulator 0=0A= (dni msblo "msblo"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "msblo $src1,$src2"=0A= (+ OP1_5 src1 OP2_13 src2)=0A= (set accum=0A= ***************=0A= *** 2050,2061 ****=0A= (const 16)))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= ; Multiply into accumulator 1=0A= (dni mulwu1 "mulwu1"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "mulwu1 $src1,$src2"=0A= (+ OP1_5 src1 OP2_10 src2)=0A= (set (reg h-accums 1)=0A= --- 2295,2307 ----=0A= (const 16)))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= ; Multiply into accumulator 1=0A= (dni mulwu1 "mulwu1"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "mulwu1 $src1,$src2"=0A= (+ OP1_5 src1 OP2_10 src2)=0A= (set (reg h-accums 1)=0A= ***************=0A= *** 2066,2077 ****=0A= (ext DI (and src2 (const #xffff))))=0A= (const 16))=0A= (const 16)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= ; Multiply and add into accumulator 1=0A= (dni maclh1 "maclh1"=0A= ! ((MACH m32rx) (PIPE S) (IDOC MAC))=0A= "maclh1 $src1,$src2"=0A= (+ OP1_5 src1 OP2_12 src2)=0A= (set (reg h-accums 1)=0A= --- 2312,2324 ----=0A= (ext DI (and src2 (const #xffff))))=0A= (const 16))=0A= (const 16)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= ; Multiply and add into accumulator 1=0A= (dni maclh1 "maclh1"=0A= ! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))=0A= "maclh1 $src1,$src2"=0A= (+ OP1_5 src1 OP2_12 src2)=0A= (set (reg h-accums 1)=0A= ***************=0A= *** 2087,2098 ****=0A= (const 16)))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac)))=0A= )=0A= =20=20=0A= ; skip instruction if C=0A= (dni sc "sc"=0A= ! ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR))=0A= "sc"=0A= (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))=0A= (skip (zext INT condbit))=0A= --- 2334,2346 ----=0A= (const 16)))=0A= (const 8))=0A= (const 8)))=0A= ! ((m32rx (unit u-mac))=0A= ! (m32r2 (unit u-mac)))=0A= )=0A= =20=20=0A= ; skip instruction if C=0A= (dni sc "sc"=0A= ! ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))=0A= "sc"=0A= (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))=0A= (skip (zext INT condbit))=0A= ***************=0A= *** 2101,2109 ****=0A= =20=20=0A= ; skip instruction if not C=0A= (dni snc "snc"=0A= ! ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR))=0A= "snc"=0A= (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))=0A= (skip (zext INT (not condbit)))=0A= ()=0A= )=0A= --- 2349,2409 ----=0A= =20=20=0A= ; skip instruction if not C=0A= (dni snc "snc"=0A= ! ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))=0A= "snc"=0A= (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))=0A= (skip (zext INT (not condbit)))=0A= ()=0A= )=0A= +=20=0A= + ; PSW &=3D ~((unsigned char) uimm8 | 0x000ff00)=0A= + (dni clrpsw "clrpsw"=0A= + ((PIPE O) SPECIAL_M32R)=0A= + "clrpsw $uimm8"=0A= + (+ OP1_7 (f-r1 2) uimm8)=0A= + (set USI (reg h-cr 0)=0A= + (and USI (reg h-cr 0)=0A= + (or USI (inv BI uimm8) (const #xff00))))=0A= + ()=0A= + )=0A= +=20=0A= + ; PSW |=3D (unsigned char) uimm8=0A= + (dni setpsw "setpsw"=0A= + ((PIPE O) SPECIAL_M32R)=0A= + "setpsw $uimm8"=0A= + (+ OP1_7 (f-r1 1) uimm8)=0A= + (set USI (reg h-cr 0) uimm8)=0A= + ()=0A= + )=0A= +=20=0A= + ; bset=0A= + (dni bset "bset"=0A= + (SPECIAL_M32R)=0A= + "bset $uimm3,@($slo16,$sr)"=0A= + (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)=0A= + (set QI (mem QI (add sr slo16))=0A= + (or QI (mem QI (add sr slo16))=0A= + (sll USI (const 1) (sub (const 7) uimm3))))=0A= + ()=0A= + )=0A= +=20=0A= + ; bclr=0A= + (dni bclr "bclr"=0A= + (SPECIAL_M32R)=0A= + "bclr $uimm3,@($slo16,$sr)"=0A= + (+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16)=0A= + (set QI (mem QI (add sr slo16))=0A= + (and QI (mem QI (add sr slo16))=0A= + (inv QI (sll USI (const 1) (sub (const 7) uimm3)))))= =0A= + ()=0A= + )=0A= +=20=0A= + ; btst=0A= + (dni btst "btst"=0A= + (SPECIAL_M32R (PIPE O))=0A= + "btst $uimm3,$sr"=0A= + (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)=0A= + (set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))= =0A= + ()=0A= + )=0A= +=20=0A= Index: cgen/cpu/m32r.opc=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/cgen/cpu/m32r.opc,v=0A= retrieving revision 1.3=0A= diff -c -r1.3 m32r.opc=0A= *** cgen/cpu/m32r.opc 20 Nov 2001 05:16:06 -0000 1.3=0A= --- cgen/cpu/m32r.opc 2 Dec 2003 08:56:10 -0000=0A= ***************=0A= *** 23,28 ****=0A= --- 23,29 ----=0A= #undef CGEN_DIS_HASH_SIZE=0A= #define CGEN_DIS_HASH_SIZE 256=0A= #undef CGEN_DIS_HASH=0A= + #if 0=0A= #define X(b) (((unsigned char *) (b))[0] & 0xf0)=0A= #define CGEN_DIS_HASH(buffer, value) \=0A= (X (buffer) | \=0A= ***************=0A= *** 30,38 ****=0A= --- 31,69 ----=0A= : X (buffer) =3D=3D 0x70 || X (buffer) =3D=3D 0xf0 ? (((unsigned char *= ) (buffer))[0] & 0xf) \=0A= : X (buffer) =3D=3D 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >>= 4) \=0A= : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))=0A= + #else=0A= + #define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)=0A= + extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);=0A= + #endif=0A= =20=20=0A= /* -- */=0A= =0C=0A= + /* -- opc.c */=0A= + unsigned int=0A= + m32r_cgen_dis_hash (buf, value)=0A= + const char * buf ATTRIBUTE_UNUSED;=0A= + CGEN_INSN_INT value;=0A= + {=0A= + unsigned int x;=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=0A= + if (value & 0xffff0000) /* 32bit instructions */=0A= + value =3D (value >> 16) & 0xffff;=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=0A= + x =3D (value>>8) & 0xf0;=0A= + if (x =3D=3D 0x40 || x =3D=3D 0xe0 || x =3D=3D 0x60 || x =3D=3D 0x50)= =0A= + return x;=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=0A= + if (x =3D=3D 0x70 || x =3D=3D 0xf0)=0A= + return x | ((value>>8) & 0x0f);=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=0A= + if (x =3D=3D 0x30)=0A= + return x | ((value & 0x70) >> 4);=0A= + else=0A= + return x | ((value & 0xf0) >> 4);=0A= + }=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=0A= + /* -- */=0A= + =0C=0A= /* -- asm.c */=0A= static const char * parse_hash=0A= PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));=0A= ***************=0A= *** 133,139 ****=0A= ++*strp;=0A= if (errmsg =3D=3D NULL=0A= && result_type =3D=3D CGEN_PARSE_OPERAND_RESULT_NUMBER)=0A= ! value &=3D 0xffff;=0A= *valuep =3D value;=0A= return errmsg;=0A= }=0A= --- 164,174 ----=0A= ++*strp;=0A= if (errmsg =3D=3D NULL=0A= && result_type =3D=3D CGEN_PARSE_OPERAND_RESULT_NUMBER)=0A= ! {=0A= ! value &=3D 0xffff;=0A= ! if (value & 0x8000)=0A= ! value |=3D 0xffff0000;=0A= ! }=0A= *valuep =3D value;=0A= return errmsg;=0A= }=0A= ***************=0A= *** 233,238 ****=0A= --- 268,275 ----=0A= char *buf =3D buffer;=0A= int status;=0A= int buflen =3D (pc & 3) =3D=3D 0 ? 4 : 2;=0A= + int big_p =3D CGEN_CPU_INSN_ENDIAN (cd) =3D=3D CGEN_ENDIAN_BIG;=0A= + char *x;=0A= =20=20=0A= /* Read the base part of the insn. */=0A= =20=20=0A= ***************=0A= *** 244,265 ****=0A= }=0A= =20=20=0A= /* 32 bit insn? */=0A= ! if ((pc & 3) =3D=3D 0 && (buf[0] & 0x80) !=3D 0)=0A= return print_insn (cd, pc, info, buf, buflen);=0A= =20=20=0A= /* Print the first insn. */=0A= if ((pc & 3) =3D=3D 0)=0A= {=0A= if (print_insn (cd, pc, info, buf, 2) =3D=3D 0)=0A= (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);=0A= - buf +=3D 2;=0A= }=0A= =20=20=0A= ! if (buf[0] & 0x80)=0A= {=0A= /* Parallel. */=0A= (*info->fprintf_func) (info->stream, " || ");=0A= ! buf[0] &=3D 0x7f;=0A= }=0A= else=0A= (*info->fprintf_func) (info->stream, " -> ");=0A= --- 281,305 ----=0A= }=0A= =20=20=0A= /* 32 bit insn? */=0A= ! x =3D (big_p ? &buf[0] : &buf[3]);=0A= ! if ((pc & 3) =3D=3D 0 && (*x & 0x80) !=3D 0)=0A= return print_insn (cd, pc, info, buf, buflen);=0A= =20=20=0A= /* Print the first insn. */=0A= + buf +=3D (big_p ? 0 : 2);=0A= if ((pc & 3) =3D=3D 0)=0A= {=0A= if (print_insn (cd, pc, info, buf, 2) =3D=3D 0)=0A= (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);=0A= }=0A= + buf +=3D (big_p ? 2 : -2);=0A= =20=20=0A= ! x =3D (big_p ? &buf[0] : &buf[1]);=0A= ! if (*x & 0x80)=0A= {=0A= /* Parallel. */=0A= (*info->fprintf_func) (info->stream, " || ");=0A= ! *x &=3D 0x7f;=0A= }=0A= else=0A= (*info->fprintf_func) (info->stream, " -> ");=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=gas.m32r2.patch Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=gas.m32r2.patch Content-length: 24330 gas/ChangeLog=0A= =0A= 2003-12-02 Kazuhiro Inaoka =0A= =0A= * config/tc-m32r.c : Add new machine m32r2.=0A= Add new instructions.=0A= (line_separator_chars) : Use '!'.=0A= * config/tc-m32r.h : Add new machine m32r2.=0A= =0A= =0A= Index: gas/config/tc-m32r.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gas/config/tc-m32r.c,v=0A= retrieving revision 1.31=0A= diff -c -r1.31 tc-m32r.c=0A= *** gas/config/tc-m32r.c 22 Nov 2003 02:35:30 -0000 1.31=0A= --- gas/config/tc-m32r.c 2 Dec 2003 08:56:11 -0000=0A= ***************=0A= *** 27,32 ****=0A= --- 27,33 ----=0A= #include "opcodes/m32r-desc.h"=0A= #include "opcodes/m32r-opc.h"=0A= #include "cgen.h"=0A= + #include "elf/m32r.h"=0A= =20=20=0A= /* Linked list of symbols that are debugging symbols to be defined as the= =0A= beginning of the current instruction. */=0A= ***************=0A= *** 93,113 ****=0A= shouldn't assume or require it to). */=0A= static int warn_unmatched_high =3D 0;=0A= =20=20=0A= ! /* Non-zero if -m32rx has been specified, in which case support for the= =0A= ! extended M32RX instruction set should be enabled. */=0A= ! static int enable_m32rx =3D 0;=0A= =20=20=0A= /* Non-zero if -m32rx -hidden has been specified, in which case support f= or=0A= the special M32RX instruction set should be enabled. */=0A= static int enable_special =3D 0;=0A= =20=20=0A= /* Non-zero if the programmer should be warned when an explicit parallel= =0A= instruction might have constraint violations. */=0A= static int warn_explicit_parallel_conflicts =3D 1;=0A= =20=20=0A= /* Non-zero if insns can be made parallel. */=0A= static int optimize;=0A= =20=20=0A= /* Stuff for .scomm symbols. */=0A= static segT sbss_section;=0A= static asection scom_section;=0A= --- 94,136 ----=0A= shouldn't assume or require it to). */=0A= static int warn_unmatched_high =3D 0;=0A= =20=20=0A= ! /* 1 if -m32rx has been specified, in which case support for the=0A= ! extended M32RX instruction set should be enabled.=0A= ! 2 if -m32r2 has been specified, in which case support for the=0A= ! extended M32R2 instruction set should be enabled.=0A= ! */=0A= ! static int enable_m32rx =3D 0; /* default M32R */=0A= =20=20=0A= /* Non-zero if -m32rx -hidden has been specified, in which case support f= or=0A= the special M32RX instruction set should be enabled. */=0A= static int enable_special =3D 0;=0A= =20=20=0A= + /* Non-zero if -bitinst has been specified, in which case support for=0A= + extended M32R bit-field instruction set should be enabled. */=0A= + static int enable_special_m32r =3D 0;=0A= +=20=0A= + /* Non-zero if -float has been specified, in which case support for=0A= + extended M32R floating point instruction set should be enabled. */=0A= + static int enable_special_float =3D 0;=0A= +=20=0A= /* Non-zero if the programmer should be warned when an explicit parallel= =0A= instruction might have constraint violations. */=0A= static int warn_explicit_parallel_conflicts =3D 1;=0A= =20=20=0A= + /* Non-zero if the programmer should be errored when an explicit parallel= =0A= + instruction might have constraint violations. */=0A= + static int error_explicit_parallel_conflicts =3D 1;=0A= +=20=0A= + /* Non-zero if insns can be made parallel. */=0A= + static int use_parallel =3D -1;=0A= +=20=0A= /* Non-zero if insns can be made parallel. */=0A= static int optimize;=0A= =20=20=0A= + /* m32r er_flags */=0A= + static int m32r_flags =3D 0;=0A= +=20=0A= +=20=0A= /* Stuff for .scomm symbols. */=0A= static segT sbss_section;=0A= static asection scom_section;=0A= ***************=0A= *** 115,121 ****=0A= =20=20=0A= const char comment_chars[] =3D ";";=0A= const char line_comment_chars[] =3D "#";=0A= ! const char line_separator_chars[] =3D "";=0A= const char EXP_CHARS[] =3D "eE";=0A= const char FLT_CHARS[] =3D "dD";=0A= =20=20=0A= --- 138,144 ----=0A= =20=20=0A= const char comment_chars[] =3D ";";=0A= const char line_comment_chars[] =3D "#";=0A= ! const char line_separator_chars[] =3D "!";=0A= const char EXP_CHARS[] =3D "eE";=0A= const char FLT_CHARS[] =3D "dD";=0A= =20=20=0A= ***************=0A= *** 146,163 ****=0A= =20=20=0A= static struct m32r_hi_fixup *m32r_hi_fixup_list;=0A= =0C=0A= ! static void allow_m32rx PARAMS ((int));=0A= =20=20=0A= static void=0A= ! allow_m32rx (on)=0A= ! int on;=0A= {=0A= enable_m32rx =3D on;=0A= =20=20=0A= if (stdoutput !=3D NULL)=0A= ! bfd_set_arch_mach (stdoutput, TARGET_ARCH,=0A= ! enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);=0A= }=0A= =0C=0A= #define M32R_SHORTOPTS "O"=0A= =20=20=0A= --- 169,197 ----=0A= =20=20=0A= static struct m32r_hi_fixup *m32r_hi_fixup_list;=0A= =0C=0A= ! struct {=0A= ! enum bfd_architecture bfd_mach;=0A= ! int mach_flags;=0A= ! } mach_table[] =3D=0A= ! {=0A= ! { bfd_mach_m32r, (1<machs =3D mach_table[on].mach_flags;=0A= }=0A= +=20=0A= =0C=0A= #define M32R_SHORTOPTS "O"=0A= =20=20=0A= ***************=0A= *** 167,184 ****=0A= {=0A= #define OPTION_M32R (OPTION_MD_BASE)=0A= #define OPTION_M32RX (OPTION_M32R + 1)=0A= ! #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1)=0A= #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)=0A= ! #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1)=0A= ! #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1)=0A= #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)=0A= {"m32r", no_argument, NULL, OPTION_M32R},=0A= {"m32rx", no_argument, NULL, OPTION_M32RX},=0A= {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PAR= ALLEL},=0A= {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},=0A= {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WA= RN_PARALLEL},=0A= {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},=0A= {"hidden", no_argument, NULL, OPTION_SPECIAL},=0A= /* Sigh. I guess all warnings must now have both variants. */=0A= {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},=0A= {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},=0A= --- 201,240 ----=0A= {=0A= #define OPTION_M32R (OPTION_MD_BASE)=0A= #define OPTION_M32RX (OPTION_M32R + 1)=0A= ! #define OPTION_M32R2 (OPTION_M32RX + 1)=0A= ! #define OPTION_BIG (OPTION_M32R2 + 1)=0A= ! #define OPTION_LITTLE (OPTION_BIG + 1)=0A= ! #define OPTION_PARALLEL (OPTION_LITTLE + 1)=0A= ! #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1)=0A= ! #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1)=0A= #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)=0A= ! #define OPTION_ERROR_PARALLEL (OPTION_NO_WARN_PARALLEL + 1)=0A= ! #define OPTION_NO_ERROR_PARALLEL (OPTION_ERROR_PARALLEL + 1)=0A= ! #define OPTION_SPECIAL (OPTION_NO_ERROR_PARALLEL + 1)=0A= ! #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1)=0A= ! #define OPTION_SPECIAL_FLOAT (OPTION_SPECIAL_M32R + 1)=0A= ! #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1)=0A= #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)=0A= {"m32r", no_argument, NULL, OPTION_M32R},=0A= {"m32rx", no_argument, NULL, OPTION_M32RX},=0A= + {"m32r2", no_argument, NULL, OPTION_M32R2},=0A= + {"big", no_argument, NULL, OPTION_BIG},=0A= + {"little", no_argument, NULL, OPTION_LITTLE},=0A= + {"EB", no_argument, NULL, OPTION_BIG},=0A= + {"EL", no_argument, NULL, OPTION_LITTLE},=0A= + {"parallel", no_argument, NULL, OPTION_PARALLEL},=0A= + {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},=0A= {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PAR= ALLEL},=0A= {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},=0A= {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WA= RN_PARALLEL},=0A= {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},=0A= + {"error-explicit-parallel-conflicts", no_argument, NULL, OPTION_ERROR_P= ARALLEL},=0A= + {"Ep", no_argument, NULL, OPTION_ERROR_PARALLEL},=0A= + {"no-error-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_E= RROR_PARALLEL},=0A= + {"Enp", no_argument, NULL, OPTION_NO_ERROR_PARALLEL},=0A= {"hidden", no_argument, NULL, OPTION_SPECIAL},=0A= + {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},=0A= + {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},=0A= /* Sigh. I guess all warnings must now have both variants. */=0A= {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},=0A= {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},=0A= ***************=0A= *** 197,202 ****=0A= --- 253,279 ----=0A= =20=20=0A= size_t md_longopts_size =3D sizeof (md_longopts);=0A= =20=20=0A= + static void little (int);=0A= + static void=0A= + little (int on)=0A= + {=0A= + target_big_endian =3D !on;=0A= + }=0A= +=20=0A= + /* Use parallel execution */=0A= + static int parallel (void);=0A= + static int=0A= + parallel (void)=0A= + {=0A= + if (!enable_m32rx)=0A= + return 0;=0A= +=20=0A= + if (use_parallel =3D=3D 1)=0A= + return 1;=0A= +=20=0A= + return 0;=0A= + }=0A= +=20=0A= int=0A= md_parse_option (c, arg)=0A= int c;=0A= ***************=0A= *** 216,221 ****=0A= --- 293,320 ----=0A= allow_m32rx (1);=0A= break;=0A= =20=20=0A= + case OPTION_M32R2:=0A= + allow_m32rx (2);=0A= + enable_special =3D 1;=0A= + enable_special_m32r =3D 1;=0A= + break;=0A= +=20=0A= + case OPTION_BIG:=0A= + target_big_endian =3D 1;=0A= + break;=0A= +=20=0A= + case OPTION_LITTLE:=0A= + target_big_endian =3D 0;=0A= + break;=0A= +=20=0A= + case OPTION_PARALLEL:=0A= + use_parallel =3D 1;=0A= + break;=0A= +=20=0A= + case OPTION_NO_PARALLEL:=0A= + use_parallel =3D 0;=0A= + break;=0A= +=20=0A= case OPTION_WARN_PARALLEL:=0A= warn_explicit_parallel_conflicts =3D 1;=0A= break;=0A= ***************=0A= *** 224,229 ****=0A= --- 323,336 ----=0A= warn_explicit_parallel_conflicts =3D 0;=0A= break;=0A= =20=20=0A= + case OPTION_ERROR_PARALLEL:=0A= + error_explicit_parallel_conflicts =3D 1;=0A= + break;=0A= +=20=0A= + case OPTION_NO_ERROR_PARALLEL:=0A= + error_explicit_parallel_conflicts =3D 0;=0A= + break;=0A= +=20=0A= case OPTION_SPECIAL:=0A= if (enable_m32rx)=0A= enable_special =3D 1;=0A= ***************=0A= *** 235,240 ****=0A= --- 342,355 ----=0A= }=0A= break;=0A= =20=20=0A= + case OPTION_SPECIAL_M32R:=0A= + enable_special_m32r =3D 1;=0A= + break;=0A= +=20=0A= + case OPTION_SPECIAL_FLOAT:=0A= + enable_special_float =3D 1;=0A= + break;=0A= +=20=0A= case OPTION_WARN_UNMATCHED:=0A= warn_unmatched_high =3D 1;=0A= break;=0A= ***************=0A= *** 271,276 ****=0A= --- 386,395 ----=0A= fprintf (stream, _("\=0A= -m32rx support the extended m32rx instruction set\n"))= ;=0A= fprintf (stream, _("\=0A= + -m32r2 support the extended m32r2 instruction set\n"))= ;=0A= + fprintf (stream, _("\=0A= + -EL,-little use little endian\n"));=0A= + fprintf (stream, _("\=0A= -O try to combine instructions in parallel\n"));= =0A= =20=20=0A= fprintf (stream, _("\=0A= ***************=0A= *** 285,290 ****=0A= --- 404,421 ----=0A= -Wp synonym for -warn-explicit-parallel-conflicts\n= "));=0A= fprintf (stream, _("\=0A= -Wnp synonym for -no-warn-explicit-parallel-conflict= s\n"));=0A= + fprintf (stream, _("\=0A= + -error-explicit-parallel-conflicts error when parallel instructions= \n"));=0A= + fprintf (stream, _("\=0A= + violate contraints\n"));=0A= + fprintf (stream, _("\=0A= + -no-error-explicit-parallel-conflicts do not error when parallel\n"));= =0A= + fprintf (stream, _("\=0A= + instructions violate contraints\= n"));=0A= + fprintf (stream, _("\=0A= + -Ep synonym for -error-explicit-parallel-conflicts\= n"));=0A= + fprintf (stream, _("\=0A= + -Enp synonym for -no-error-explicit-parallel-conflic= ts\n"));=0A= =20=20=0A= fprintf (stream, _("\=0A= -warn-unmatched-high warn when an (s)high reloc has no matching low = reloc\n"));=0A= ***************=0A= *** 295,300 ****=0A= --- 426,432 ----=0A= fprintf (stream, _("\=0A= -Wnuh synonym for -no-warn-unmatched-high\n"));=0A= =20=20=0A= +=20=0A= #if 0=0A= fprintf (stream, _("\=0A= -relax create linker relaxable code\n"));=0A= ***************=0A= *** 322,327 ****=0A= --- 454,461 ----=0A= /* Not documented as so far there is no need for them.... */=0A= { "m32r", allow_m32rx, 0 },=0A= { "m32rx", allow_m32rx, 1 },=0A= + { "m32r2", allow_m32rx, 2 },=0A= + { "little", little, 1 },=0A= { NULL, NULL, 0 }=0A= };=0A= =20=20=0A= ***************=0A= *** 459,464 ****=0A= --- 593,608 ----=0A= input_line_pointer =3D save_input_line;=0A= }=0A= =20=20=0A= + void=0A= + m32r_flush_pending_output()=0A= + {=0A= + if (debug_sym_link)=0A= + {=0A= + expand_debug_syms (debug_sym_link, 1);=0A= + debug_sym_link =3D (sym_linkS *) 0;=0A= + }=0A= + }=0A= +=20=0A= /* Cover function to fill_insn called after a label and at end of assembl= y.=0A= The result is always 1: we're called in a conditional to see if the=0A= current line is a label. */=0A= ***************=0A= *** 488,493 ****=0A= --- 632,656 ----=0A= return 1;=0A= }=0A= =0C=0A= +=20=0A= + /* The default target format to use. */=0A= +=20=0A= + const char *=0A= + m32r_target_format ()=0A= + {=0A= + #ifdef TE_LINUX=0A= + if (target_big_endian)=0A= + return "elf32-m32r-linux";=0A= + else=0A= + return "elf32-m32rle-linux";=0A= + #else=0A= + if (target_big_endian)=0A= + return "elf32-m32r";=0A= + else=0A= + return "elf32-m32rle";=0A= + #endif=0A= + }=0A= +=20=0A= void=0A= md_begin ()=0A= {=0A= ***************=0A= *** 500,506 ****=0A= /* Set the machine number and endian. */=0A= gas_cgen_cpu_desc =3D m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,=0A= CGEN_CPU_OPEN_ENDIAN,=0A= ! CGEN_ENDIAN_BIG,=0A= CGEN_CPU_OPEN_END);=0A= m32r_cgen_init_asm (gas_cgen_cpu_desc);=0A= =20=20=0A= --- 663,670 ----=0A= /* Set the machine number and endian. */=0A= gas_cgen_cpu_desc =3D m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,=0A= CGEN_CPU_OPEN_ENDIAN,=0A= ! (target_big_endian ?=0A= ! CGEN_ENDIAN_BIG : CGEN_ENDIAN_= LITTLE),=0A= CGEN_CPU_OPEN_END);=0A= m32r_cgen_init_asm (gas_cgen_cpu_desc);=0A= =20=20=0A= ***************=0A= *** 711,717 ****=0A= go away if the instructions are swapped, and we want to make=0A= sure that any other errors are detected before this happens. */=0A= if (a_pipe =3D=3D PIPE_S=0A= ! || b_pipe =3D=3D PIPE_O)=0A= return _("Instructions share the same execution pipeline");=0A= =20=20=0A= return NULL;=0A= --- 875,882 ----=0A= go away if the instructions are swapped, and we want to make=0A= sure that any other errors are detected before this happens. */=0A= if (a_pipe =3D=3D PIPE_S=0A= ! || b_pipe =3D=3D PIPE_O=0A= ! || (b_pipe =3D=3D PIPE_O_OS && (enable_m32rx !=3D 2)))=0A= return _("Instructions share the same execution pipeline");=0A= =20=20=0A= return NULL;=0A= ***************=0A= *** 791,798 ****=0A= --- 956,981 ----=0A= as_bad (_("not a 16 bit instruction '%s'"), str);=0A= return;=0A= }=0A= + #ifdef E_M32R2_ARCH=0A= + else if ((enable_m32rx =3D=3D 1)=0A= + /* FIXME: Need standard macro to perform this test. */=0A= + && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)=0A= + & (1 << MACH_M32R2))=0A= + && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)=0A= + & (1 << MACH_M32RX)))))=0A= + {=0A= + /* xgettext:c-format */=0A= + as_bad (_("instruction '%s' is for the M32R2 only"), str);=0A= + return;=0A= + }=0A= + else if ((! enable_special=0A= + && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))=0A= + || (! enable_special_m32r=0A= + && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32= R)))=0A= + #else=0A= else if (! enable_special=0A= && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))=0A= + #endif=0A= {=0A= /* xgettext:c-format */=0A= as_bad (_("unknown instruction '%s'"), str);=0A= ***************=0A= *** 887,894 ****=0A= --- 1070,1095 ----=0A= as_bad (_("not a 16 bit instruction '%s'"), str);=0A= return;=0A= }=0A= + #ifdef E_M32R2_ARCH=0A= + else if ((enable_m32rx =3D=3D 1)=0A= + /* FIXME: Need standard macro to perform this test. */=0A= + && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)=0A= + & (1 << MACH_M32R2))=0A= + && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)=0A= + & (1 << MACH_M32RX)))))=0A= + {=0A= + /* xgettext:c-format */=0A= + as_bad (_("instruction '%s' is for the M32R2 only"), str);=0A= + return;=0A= + }=0A= + else if ((! enable_special=0A= + && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))=0A= + || (! enable_special_m32r=0A= + && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M3= 2R)))=0A= + #else=0A= else if (! enable_special=0A= && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))=0A= + #endif=0A= {=0A= /* xgettext:c-format */=0A= as_bad (_("unknown instruction '%s'"), str);=0A= ***************=0A= *** 1001,1006 ****=0A= --- 1202,1217 ----=0A= return;=0A= }=0A= =20=20=0A= + if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)=0A= + || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))=0A= + m32r_flags |=3D E_M32R_HAS_HIDDEN_INST;=0A= + if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)=0A= + || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))=0A= + m32r_flags |=3D E_M32R_HAS_BIT_INST;=0A= + if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)=0A= + || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))=0A= + m32r_flags |=3D E_M32R_HAS_FLOAT_INST;=0A= +=20=0A= /* Set these so m32r_fill_insn can use them. */=0A= prev_seg =3D now_seg;=0A= prev_subseg =3D now_subseg;=0A= ***************=0A= *** 1021,1026 ****=0A= --- 1232,1238 ----=0A= if ((str2 =3D strstr (str, "||")) !=3D NULL)=0A= {=0A= assemble_two_insns (str, str2, 1);=0A= + m32r_flags |=3D E_M32R_HAS_PARALLEL;=0A= return;=0A= }=0A= =20=20=0A= ***************=0A= *** 1043,1050 ****=0A= --- 1255,1280 ----=0A= return;=0A= }=0A= =20=20=0A= + #ifdef E_M32R2_ARCH=0A= + if ((enable_m32rx =3D=3D 1)=0A= + /* FIXME: Need standard macro to perform this test. */=0A= + && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)=0A= + & (1 << MACH_M32R2))=0A= + && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)=0A= + & (1 << MACH_M32RX)))))=0A= + {=0A= + /* xgettext:c-format */=0A= + as_bad (_("instruction '%s' is for the M32R2 only"), str);=0A= + return;=0A= + }=0A= + else if ((! enable_special=0A= + && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))=0A= + || (! enable_special_m32r=0A= + && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))= =0A= + #else=0A= if (! enable_special=0A= && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))=0A= + #endif=0A= {=0A= /* xgettext:c-format */=0A= as_bad (_("unknown instruction '%s'"), str);=0A= ***************=0A= *** 1058,1063 ****=0A= --- 1288,1300 ----=0A= return;=0A= }=0A= =20=20=0A= + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))=0A= + m32r_flags |=3D E_M32R_HAS_HIDDEN_INST;=0A= + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))=0A= + m32r_flags |=3D E_M32R_HAS_BIT_INST;=0A= + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))=0A= + m32r_flags |=3D E_M32R_HAS_FLOAT_INST;=0A= +=20=0A= if (CGEN_INSN_BITSIZE (insn.insn) =3D=3D 32)=0A= {=0A= /* 32 bit insns must live on 32 bit boundaries. */=0A= ***************=0A= *** 1948,1951 ****=0A= --- 2185,2196 ----=0A= return 0;=0A= =20=20=0A= return 1;=0A= + }=0A= +=20=0A= + void=0A= + m32r_elf_final_processing ()=0A= + {=0A= + if (use_parallel)=0A= + m32r_flags |=3D E_M32R_HAS_PARALLEL;=0A= + elf_elfheader (stdoutput)->e_flags |=3D m32r_flags;=0A= }=0A= Index: gas/config/tc-m32r.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gas/config/tc-m32r.h,v=0A= retrieving revision 1.9=0A= diff -c -r1.9 tc-m32r.h=0A= *** gas/config/tc-m32r.h 25 Jul 2003 14:35:54 -0000 1.9=0A= --- gas/config/tc-m32r.h 2 Dec 2003 08:56:11 -0000=0A= ***************=0A= *** 26,39 ****=0A= #error M32R support requires BFD_ASSEMBLER=0A= #endif=0A= =20=20=0A= ! #define LISTING_HEADER "M32R GAS "=0A= =20=20=0A= /* The target BFD architecture. */=0A= #define TARGET_ARCH bfd_arch_m32r=0A= =20=20=0A= ! #define TARGET_FORMAT "elf32-m32r"=0A= =20=20=0A= #define TARGET_BYTES_BIG_ENDIAN 1=0A= =20=20=0A= /* call md_pcrel_from_section, not md_pcrel_from */=0A= long md_pcrel_from_section PARAMS ((struct fix *, segT));=0A= --- 26,47 ----=0A= #error M32R support requires BFD_ASSEMBLER=0A= #endif=0A= =20=20=0A= ! #define LISTING_HEADER \=0A= ! (target_big_endian \=0A= ! ? "M32R GAS" : "M32R GAS Little Endian")=0A= =20=20=0A= /* The target BFD architecture. */=0A= #define TARGET_ARCH bfd_arch_m32r=0A= =20=20=0A= ! /* The endianness of the target format may change based on command=0A= ! line arguments. */=0A= ! #define TARGET_FORMAT m32r_target_format()=0A= ! extern const char *m32r_target_format PARAMS ((void));=0A= =20=20=0A= + /* Default to big endian. */=0A= + #ifndef TARGET_BYTES_BIG_ENDIAN=0A= #define TARGET_BYTES_BIG_ENDIAN 1=0A= + #endif=0A= =20=20=0A= /* call md_pcrel_from_section, not md_pcrel_from */=0A= long md_pcrel_from_section PARAMS ((struct fix *, segT));=0A= ***************=0A= *** 101,103 ****=0A= --- 109,118 ----=0A= #define md_cleanup m32r_elf_section_change_hook=0A= #define md_elf_section_change_hook m32r_elf_section_change_hook=0A= extern void m32r_elf_section_change_hook PARAMS ((void));=0A= +=20=0A= + #define md_flush_pending_output() m32r_flush_pending_output ()=0A= + extern void m32r_flush_pending_output PARAMS ((void));=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=0A= + #define elf_tc_final_processing m32r_elf_final_processing=0A= + extern void m32r_elf_final_processing PARAMS ((void));=0A= +=20=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=include.m32r2.patch Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=include.m32r2.patch Content-length: 1638 include/ChangeLog=0A= =0A= 2003-12-02 Kazuhiro Inaoka =0A= =0A= * elf/m32r.h : Add new machine type m32r2 and instruction modes.=0A= =0A= Index: include/elf/m32r.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/include/elf/m32r.h,v=0A= retrieving revision 1.5=0A= diff -c -r1.5 m32r.h=0A= *** include/elf/m32r.h 14 Mar 2001 02:27:44 -0000 1.5=0A= --- include/elf/m32r.h 2 Dec 2003 08:56:12 -0000=0A= ***************=0A= *** 63,67 ****=0A= --- 63,87 ----=0A= #define E_M32R_ARCH 0x00000000=0A= /* m32rx code. */=0A= #define E_M32RX_ARCH 0x10000000=0A= + #define E_M32RX_ARCH 0x10000000=0A= + /* m32r2 code. */=0A= + #define E_M32R2_ARCH 0x20000000=0A= +=20=0A= + /* 12 bit m32r new instructions field. */=0A= + #define EF_M32R_INST 0x0FFF0000=0A= + /* parallel instructions */=0A= + #define E_M32R_HAS_PARALLEL 0x00010000=0A= + /* hidden instructions for m32rx:=0A= + jc, jnc, macwhi-a, macwlo-a, mulwhi-a, mulwlo-a, sth+, shb+, sat, pcmp= bz,=0A= + sc, snc */=0A= + #define E_M32R_HAS_HIDDEN_INST 0x00020000=0A= + /* new bit instructions:=0A= + clrpsw, setpsw, bset, bclr, btst */=0A= + #define E_M32R_HAS_BIT_INST 0x00040000=0A= + /* floating point instructions */=0A= + #define E_M32R_HAS_FLOAT_INST 0x00080000=0A= +=20=0A= + /* 4 bit m32r ignore to check field. */=0A= + #define EF_M32R_IGNORE 0x0000000F=0A= =20=20=0A= #endif=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=sim.m32r2.patch Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=sim.m32r2.patch Content-length: 17973 ChangeLog/sim/m32r=0A= =0A= 2003-12-02 Kazuhiro Inaoka =0A= =0A= * Makefile.in : Add new machine m32r2.=0A= * m32r2.c : New file for m32r2.=0A= * mloop2.in : Ditto=0A= * model2.c : Ditto=0A= * sem2-switch.c : Ditto=0A= * m32r-sim.h : Add EVB register.=0A= * sim-if.h : Ditto=0A= * sim-main.h : Ditto=0A= * traps.c : Ditto=0A= =0A= Index: sim/m32r/Makefile.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/m32r/Makefile.in,v=0A= retrieving revision 1.6=0A= diff -c -r1.6 Makefile.in=0A= *** sim/m32r/Makefile.in 8 Sep 2003 17:26:20 -0000 1.6=0A= --- sim/m32r/Makefile.in 2 Dec 2003 08:56:19 -0000=0A= ***************=0A= *** 22,27 ****=0A= --- 22,28 ----=0A= =20=20=0A= M32R_OBJS =3D m32r.o cpu.o decode.o sem.o model.o mloop.o=0A= M32RX_OBJS =3D m32rx.o cpux.o decodex.o modelx.o mloopx.o=0A= + M32R2_OBJS =3D m32r2.o cpu2.o decode2.o model2.o mloop2.o=0A= =20=20=0A= CONFIG_DEVICES =3D dv-sockser.o=0A= CONFIG_DEVICES =3D=0A= ***************=0A= *** 38,43 ****=0A= --- 39,45 ----=0A= sim-if.o arch.o \=0A= $(M32R_OBJS) \=0A= $(M32RX_OBJS) \=0A= + $(M32R2_OBJS) \=0A= traps.o devices.o \=0A= $(CONFIG_DEVICES)=0A= =20=20=0A= ***************=0A= *** 113,122 ****=0A= semx.o: semx.c $(M32RXF_INCLUDE_DEPS)=0A= modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)=0A= =20=20=0A= m32r-clean:=0A= rm -f mloop.c eng.h stamp-mloop=0A= rm -f mloopx.c engx.h stamp-xmloop=0A= ! rm -f stamp-arch stamp-cpu stamp-xcpu=0A= rm -f tmp-*=0A= =20=20=0A= # cgen support, enable with --enable-cgen-maint=0A= --- 115,149 ----=0A= semx.o: semx.c $(M32RXF_INCLUDE_DEPS)=0A= modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)=0A= =20=20=0A= + # M32R2 objs=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=0A= + M32R2F_INCLUDE_DEPS =3D \=0A= + $(CGEN_MAIN_CPU_DEPS) \=0A= + cpu2.h decode2.h eng2.h=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=0A= + m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=0A= + # FIXME: Use of `mono' is wip.=0A= + mloop2.c eng2.h: stamp-2mloop=0A= + stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile=0A= + $(SHELL) $(srccom)/genmloop.sh \=0A= + -mono -no-fast -pbb -parallel-write -switch sem2-switch.c \=0A= + -cpu m32r2f -infile $(srcdir)/mloop2.in=0A= + $(SHELL) $(srcroot)/move-if-change eng.hin eng2.h=0A= + $(SHELL) $(srcroot)/move-if-change mloop.cin mloop2.c=0A= + touch stamp-2mloop=0A= + mloop2.o: mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)=0A= +=20=0A= + cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)=0A= + decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)=0A= + sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)=0A= + model2.o: model2.c $(M32R2F_INCLUDE_DEPS)=0A= +=20=0A= m32r-clean:=0A= rm -f mloop.c eng.h stamp-mloop=0A= rm -f mloopx.c engx.h stamp-xmloop=0A= ! rm -f mloop2.c eng2.h stamp-2mloop=0A= ! rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu=0A= rm -f tmp-*=0A= =20=20=0A= # cgen support, enable with --enable-cgen-maint=0A= ***************=0A= *** 148,150 ****=0A= --- 175,187 ----=0A= EXTRAFILES=3D"$(CGEN_CPU_SEMSW)"=0A= touch stamp-xcpu=0A= cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xc= pu=0A= +=20=0A= + stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CP= U_DIR)/m32r.cpu=0A= + $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \=0A= + cpu=3Dm32r2f mach=3Dm32r2 SUFFIX=3D2 \=0A= + archfile=3D$(CGEN_CPU_DIR)/m32r.cpu \=0A= + FLAGS=3D"with-scache with-profile=3Dfn" \=0A= + EXTRAFILES=3D"$(CGEN_CPU_SEMSW)"=0A= + touch stamp-2cpu=0A= + cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2c= pu=0A= +=20=0A= Index: sim/m32r/m32r-sim.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/m32r/m32r-sim.h,v=0A= retrieving revision 1.1.1.3=0A= diff -c -r1.1.1.3 m32r-sim.h=0A= *** sim/m32r/m32r-sim.h 12 Oct 1999 04:37:53 -0000 1.1.1.3=0A= --- sim/m32r/m32r-sim.h 2 Dec 2003 08:56:20 -0000=0A= ***************=0A= *** 34,39 ****=0A= --- 34,40 ----=0A= #define ACC1H_REGNUM 25=0A= #define BBPSW_REGNUM 26=0A= #define BBPC_REGNUM 27=0A= + #define EVB_REGNUM 28=0A= =20=20=0A= extern int m32r_decode_gdb_ctrl_regnum (int);=0A= =20=20=0A= Index: sim/m32r/m32r.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/m32r/m32r.c,v=0A= retrieving revision 1.1.1.2=0A= diff -c -r1.1.1.2 m32r.c=0A= *** sim/m32r/m32r.c 26 Apr 1999 18:32:56 -0000 1.1.1.2=0A= --- sim/m32r/m32r.c 2 Dec 2003 08:56:20 -0000=0A= ***************=0A= *** 39,44 ****=0A= --- 39,45 ----=0A= case BPC_REGNUM : return H_CR_BPC;=0A= case BBPSW_REGNUM : return H_CR_BBPSW;=0A= case BBPC_REGNUM : return H_CR_BBPC;=0A= + case EVB_REGNUM : return H_CR_CR5;=0A= }=0A= abort ();=0A= }=0A= ***************=0A= *** 62,87 ****=0A= case BPC_REGNUM :=0A= case BBPSW_REGNUM :=0A= case BBPC_REGNUM :=0A= SETTWI (buf, a_m32r_h_cr_get (current_cpu,=0A= m32r_decode_gdb_ctrl_regnum (rn)));=0A= break;=0A= case PC_REGNUM :=0A= if (mach =3D=3D MACH_M32R)=0A= SETTWI (buf, m32rbf_h_pc_get (current_cpu));=0A= ! else=0A= SETTWI (buf, m32rxf_h_pc_get (current_cpu));=0A= break;=0A= case ACCL_REGNUM :=0A= if (mach =3D=3D MACH_M32R)=0A= SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));=0A= ! else=0A= SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));=0A= break;=0A= case ACCH_REGNUM :=0A= if (mach =3D=3D MACH_M32R)=0A= SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));=0A= ! else=0A= SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));=0A= break;=0A= default :=0A= return 0;=0A= --- 63,95 ----=0A= case BPC_REGNUM :=0A= case BBPSW_REGNUM :=0A= case BBPC_REGNUM :=0A= + case EVB_REGNUM :=0A= SETTWI (buf, a_m32r_h_cr_get (current_cpu,=0A= m32r_decode_gdb_ctrl_regnum (rn)));=0A= break;=0A= case PC_REGNUM :=0A= if (mach =3D=3D MACH_M32R)=0A= SETTWI (buf, m32rbf_h_pc_get (current_cpu));=0A= ! else if (mach =3D=3D MACH_M32RX)=0A= SETTWI (buf, m32rxf_h_pc_get (current_cpu));=0A= + else=0A= + SETTWI (buf, m32r2f_h_pc_get (current_cpu));=0A= break;=0A= case ACCL_REGNUM :=0A= if (mach =3D=3D MACH_M32R)=0A= SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));=0A= ! else if (mach =3D=3D MACH_M32RX)=0A= SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));=0A= + else=0A= + SETTWI (buf, GETLODI (m32r2f_h_accum_get (current_cpu)));=0A= break;=0A= case ACCH_REGNUM :=0A= if (mach =3D=3D MACH_M32R)=0A= SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));=0A= ! else if (mach =3D=3D MACH_M32RX)=0A= SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));=0A= + else=0A= + SETTWI (buf, GETHIDI (m32r2f_h_accum_get (current_cpu)));=0A= break;=0A= default :=0A= return 0;=0A= ***************=0A= *** 109,114 ****=0A= --- 117,123 ----=0A= case BPC_REGNUM :=0A= case BBPSW_REGNUM :=0A= case BBPC_REGNUM :=0A= + case EVB_REGNUM :=0A= a_m32r_h_cr_set (current_cpu,=0A= m32r_decode_gdb_ctrl_regnum (rn),=0A= GETTWI (buf));=0A= ***************=0A= *** 116,136 ****=0A= case PC_REGNUM :=0A= if (mach =3D=3D MACH_M32R)=0A= m32rbf_h_pc_set (current_cpu, GETTWI (buf));=0A= ! else=0A= m32rxf_h_pc_set (current_cpu, GETTWI (buf));=0A= break;=0A= case ACCL_REGNUM :=0A= {=0A= DI val;=0A= if (mach =3D=3D MACH_M32R)=0A= val =3D m32rbf_h_accum_get (current_cpu);=0A= ! else=0A= val =3D m32rxf_h_accum_get (current_cpu);=0A= SETLODI (val, GETTWI (buf));=0A= if (mach =3D=3D MACH_M32R)=0A= m32rbf_h_accum_set (current_cpu, val);=0A= ! else=0A= m32rxf_h_accum_set (current_cpu, val);=0A= break;=0A= }=0A= case ACCH_REGNUM :=0A= --- 125,151 ----=0A= case PC_REGNUM :=0A= if (mach =3D=3D MACH_M32R)=0A= m32rbf_h_pc_set (current_cpu, GETTWI (buf));=0A= ! else if (mach =3D=3D MACH_M32RX)=0A= m32rxf_h_pc_set (current_cpu, GETTWI (buf));=0A= + else=0A= + m32r2f_h_pc_set (current_cpu, GETTWI (buf));=0A= break;=0A= case ACCL_REGNUM :=0A= {=0A= DI val;=0A= if (mach =3D=3D MACH_M32R)=0A= val =3D m32rbf_h_accum_get (current_cpu);=0A= ! else if (mach =3D=3D MACH_M32RX)=0A= val =3D m32rxf_h_accum_get (current_cpu);=0A= + else=0A= + val =3D m32r2f_h_accum_get (current_cpu);=0A= SETLODI (val, GETTWI (buf));=0A= if (mach =3D=3D MACH_M32R)=0A= m32rbf_h_accum_set (current_cpu, val);=0A= ! else if (mach =3D=3D MACH_M32RX)=0A= m32rxf_h_accum_set (current_cpu, val);=0A= + else=0A= + m32r2f_h_accum_set (current_cpu, val);=0A= break;=0A= }=0A= case ACCH_REGNUM :=0A= ***************=0A= *** 138,150 ****=0A= DI val;=0A= if (mach =3D=3D MACH_M32R)=0A= val =3D m32rbf_h_accum_get (current_cpu);=0A= ! else=0A= val =3D m32rxf_h_accum_get (current_cpu);=0A= SETHIDI (val, GETTWI (buf));=0A= if (mach =3D=3D MACH_M32R)=0A= m32rbf_h_accum_set (current_cpu, val);=0A= ! else=0A= m32rxf_h_accum_set (current_cpu, val);=0A= break;=0A= }=0A= default :=0A= --- 153,169 ----=0A= DI val;=0A= if (mach =3D=3D MACH_M32R)=0A= val =3D m32rbf_h_accum_get (current_cpu);=0A= ! else if (mach =3D=3D MACH_M32RX)=0A= val =3D m32rxf_h_accum_get (current_cpu);=0A= + else=0A= + val =3D m32r2f_h_accum_get (current_cpu);=0A= SETHIDI (val, GETTWI (buf));=0A= if (mach =3D=3D MACH_M32R)=0A= m32rbf_h_accum_set (current_cpu, val);=0A= ! else if (mach =3D=3D MACH_M32RX)=0A= m32rxf_h_accum_set (current_cpu, val);=0A= + else=0A= + m32r2f_h_accum_set (current_cpu, val);=0A= break;=0A= }=0A= default :=0A= ***************=0A= *** 169,174 ****=0A= --- 188,197 ----=0A= case MACH_M32RX :=20=0A= return m32rxf_h_gr_get (current_cpu, regno);=0A= #endif=0A= + #ifdef HAVE_CPU_M32R2F=0A= + case MACH_M32R2 :=20=0A= + return m32r2f_h_gr_get (current_cpu, regno);=0A= + #endif=0A= default :=0A= abort ();=0A= }=0A= ***************=0A= *** 189,194 ****=0A= --- 212,222 ----=0A= m32rxf_h_gr_set (current_cpu, regno, newval);=0A= break;=0A= #endif=0A= + #ifdef HAVE_CPU_M32RXF=0A= + case MACH_M32R2 :=20=0A= + m32r2f_h_gr_set (current_cpu, regno, newval);=0A= + break;=0A= + #endif=0A= default :=0A= abort ();=0A= }=0A= ***************=0A= *** 207,212 ****=0A= --- 235,244 ----=0A= case MACH_M32RX :=20=0A= return m32rxf_h_cr_get (current_cpu, regno);=0A= #endif=0A= + #ifdef HAVE_CPU_M32R2F=0A= + case MACH_M32R2 :=20=0A= + return m32r2f_h_cr_get (current_cpu, regno);=0A= + #endif=0A= default :=0A= abort ();=0A= }=0A= ***************=0A= *** 225,230 ****=0A= --- 257,267 ----=0A= #ifdef HAVE_CPU_M32RXF=0A= case MACH_M32RX :=20=0A= m32rxf_h_cr_set (current_cpu, regno, newval);=0A= + break;=0A= + #endif=0A= + #ifdef HAVE_CPU_M32RXF=0A= + case MACH_M32R2 :=20=0A= + m32r2f_h_cr_set (current_cpu, regno, newval);=0A= break;=0A= #endif=0A= default :=0A= Index: sim/m32r/sim-if.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/m32r/sim-if.c,v=0A= retrieving revision 1.2=0A= diff -c -r1.2 sim-if.c=0A= *** sim/m32r/sim-if.c 27 Feb 2003 23:26:34 -0000 1.2=0A= --- sim/m32r/sim-if.c 2 Dec 2003 08:56:23 -0000=0A= ***************=0A= *** 240,245 ****=0A= --- 240,250 ----=0A= PROFILE_LABEL_WIDTH, "Parallel insns:",=0A= sim_add_commas (buf, sizeof (buf),=0A= CPU_M32R_MISC_PROFILE (cpu)->parallel_count));=0A= + if (STATE_ARCHITECTURE (sd)->mach =3D=3D bfd_mach_m32r2)=0A= + sim_io_printf (sd, " %-*s %s\n\n",=0A= + PROFILE_LABEL_WIDTH, "Parallel insns:",=0A= + sim_add_commas (buf, sizeof (buf),=0A= + CPU_M32R_MISC_PROFILE (cpu)->parallel_count));=0A= }=0A= }=0A= =20=20=0A= Index: sim/m32r/sim-main.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/m32r/sim-main.h,v=0A= retrieving revision 1.1.1.2=0A= diff -c -r1.1.1.2 sim-main.h=0A= *** sim/m32r/sim-main.h 12 Oct 1999 04:37:53 -0000 1.1.1.2=0A= --- sim/m32r/sim-main.h 2 Dec 2003 08:56:23 -0000=0A= ***************=0A= *** 60,65 ****=0A= --- 60,67 ----=0A= M32RBF_CPU_DATA cpu_data;=0A= #elif defined (WANT_CPU_M32RXF)=0A= M32RXF_CPU_DATA cpu_data;=0A= + #elif defined (WANT_CPU_M32R2F)=0A= + M32R2F_CPU_DATA cpu_data;=0A= #endif=0A= };=0A= =0C=0A= Index: sim/m32r/traps.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/m32r/traps.c,v=0A= retrieving revision 1.1.1.3=0A= diff -c -r1.1.1.3 traps.c=0A= *** sim/m32r/traps.c 5 Oct 1999 23:13:56 -0000 1.1.1.3=0A= --- sim/m32r/traps.c 2 Dec 2003 08:56:23 -0000=0A= ***************=0A= *** 21,26 ****=0A= --- 21,27 ----=0A= #include "sim-main.h"=0A= #include "targ-vals.h"=0A= =20=20=0A= + #define TRAP_FLUSH_CACHE 12=0A= /* The semantic code invokes this for invalid (unrecognized) instructions= .=0A= CIA is the address with the invalid insn.=0A= VPC is the virtual pc of the following insn. */=0A= ***************=0A= *** 68,79 ****=0A= /* sm not changed */=0A= m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);= =0A= }=0A= ! else=0A= {=0A= m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));=0A= /* sm not changed */=0A= m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);= =0A= }=0A= a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);=0A= =20=20=0A= sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,=0A= --- 69,86 ----=0A= /* sm not changed */=0A= m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);= =0A= }=0A= ! else if (MACH_NUM (CPU_MACH (current_cpu)) =3D=3D MACH_M32RX)=0A= {=0A= m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));=0A= /* sm not changed */=0A= m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);= =0A= }=0A= + else=0A= + {=0A= + m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));=0A= + /* sm not changed */=0A= + m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);= =0A= + }=0A= a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);=0A= =20=20=0A= sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,=0A= ***************=0A= *** 131,138 ****=0A= if (STATE_ENVIRONMENT (sd) =3D=3D OPERATING_ENVIRONMENT)=0A= {=0A= /* The new pc is the trap vector entry.=0A= ! We assume there's a branch there to some handler. */=0A= ! USI new_pc =3D EIT_TRAP_BASE_ADDR + num * 4;=0A= return new_pc;=0A= }=0A= =20=20=0A= --- 138,147 ----=0A= if (STATE_ENVIRONMENT (sd) =3D=3D OPERATING_ENVIRONMENT)=0A= {=0A= /* The new pc is the trap vector entry.=0A= ! We assume there's a branch there to some handler.=0A= ! Use cr5 as EVB (EIT Vector Base) register. */=0A= ! /* USI new_pc =3D EIT_TRAP_BASE_ADDR + num * 4; */=0A= ! USI new_pc =3D a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;= =0A= return new_pc;=0A= }=0A= =20=20=0A= ***************=0A= *** 169,177 ****=0A= sim_stopped, SIM_SIGTRAP);=0A= break;=0A= =20=20=0A= default :=0A= {=0A= ! USI new_pc =3D EIT_TRAP_BASE_ADDR + num * 4;=0A= return new_pc;=0A= }=0A= }=0A= --- 178,192 ----=0A= sim_stopped, SIM_SIGTRAP);=0A= break;=0A= =20=20=0A= + case TRAP_FLUSH_CACHE:=0A= + /* Do nothing. */=0A= + break;=0A= +=20=0A= default :=0A= {=0A= ! /* USI new_pc =3D EIT_TRAP_BASE_ADDR + num * 4; */=0A= ! /* Use cr5 as EVB (EIT Vector Base) register. */=0A= ! USI new_pc =3D a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;= =0A= return new_pc;=0A= }=0A= }=0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w) Content-type: application/octet-stream; name=m32r2.s Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=m32r2.s Content-length: 2137 # Test new instructions=0A= =09=0A= .text=0A= .global setpsw=0A= setpsw:=0A= setpsw 0xc1=0A= setpsw 0xff=0A= =0A= .text=0A= .global clrpsw=0A= clrpsw:=0A= clrpsw 0xc1=0A= clrpsw 0xff=0A= =0A= .text=0A= .global bset=0A= bset:=0A= bset #0,@(4,r1)=0A= bset #1,@(4,r1)=0A= bset #7,@(4,r1)=0A= =0A= .text=0A= .global bclr=0A= bclr:=0A= bclr #0,@(4,r1)=0A= bclr #1,@(4,r1)=0A= bclr #7,@(4,r1)=0A= =0A= .text=0A= .global btst=0A= btst:=0A= btst #0,fp=0A= btst #1,fp=0A= btst #7,fp=0A= btst #1,fp || mv r0,r2=0A= mv r0,r2 || btst #1,fp=0A= =0A= .text=0A= .global divuh=0A= divuh:=0A= divuh fp,fp=0A= =0A= .text=0A= .global divb=0A= divb:=0A= divb fp,fp=0A= =09=0A= .text=0A= .global divub=0A= divub:=0A= divub fp,fp=0A= =09=0A= .text=0A= .global remh=0A= remh:=0A= remh fp,fp=0A= =09=0A= .text=0A= .global remuh=0A= remuh:=0A= remuh fp,fp=0A= =09=0A= .text=0A= .global remb=0A= remb:=0A= remb fp,fp=0A= =09=0A= .text=0A= .global remub=0A= remub:=0A= remub fp,fp=0A= =09=0A= .text=0A= .global sll=0A= sll:=0A= sll r0,r1 || sll r2,r3=0A= mul r0,r1 || sll r2,r3=0A= sll r0,r1 || mul r2,r3=0A= ldi r0,#1 || sll r2,r3=0A= sll r0,r1 || ldi r2,#1=0A= =0A= .text=0A= .global slli=0A= slli:=0A= slli r0,#1 || slli r2,#31=0A= mul r0,r1 || slli r2,#31=0A= slli r0,#1 || mul r2,r3=0A= ldi r0,#1 || slli r2,#31=0A= slli r0,#1 || ldi r2,#1=0A= =0A= .text=0A= .global sra=0A= sra:=0A= sra r0,r1 || sra r2,r3=0A= mul r0,r1 || sra r2,r3=0A= sra r0,r1 || mul r2,r3=0A= ldi r0,#1 || sra r2,r3=0A= sra r0,r1 || ldi r2,#1=0A= =0A= .text=0A= .global srai=0A= srai:=0A= srai r0,#1 || srai r2,#31=0A= mul r0,r1 || srai r2,#31=0A= srai r0,#1 || mul r2,r3=0A= ldi r0,#1 || srai r2,#31=0A= srai r0,#1 || ldi r2,#1=0A= =0A= .text=0A= .global sra=0A= srl:=0A= srl r0,r1 || srl r2,r3=0A= mul r0,r1 || srl r2,r3=0A= srl r0,r1 || mul r2,r3=0A= ldi r0,#1 || srl r2,r3=0A= srl r0,r1 || ldi r2,#1=0A= =0A= .text=0A= .global srai=0A= srli:=0A= srli r0,#1 || srli r2,#31=0A= mul r0,r1 || srli r2,#31=0A= srli r0,#1 || mul r2,r3=0A= ldi r0,#1 || srli r2,#31=0A= srli r0,#1 || ldi r2,#1=0A= =0A= --Boundary_(ID_y5/WuwEgZjX9MPJ8aQK1+w)--