Re: sid semantic with derived-operands

["Aurélien Buhrig" <aurelien.buhrig.gcc@gmail.com>]

Hi,

Thank you for your answer and sorry for my late reply.

> I have an issue when generating the sid semantic of derived-operands.
>> When printing C code for sid semantic, cgen tries to generate a
>> hardware index (in /gen-hw-index) from a derived ifield, which is not
>> supported by /gen-hw-index.
>> [...]
> Could you share a relevant usable extract of your .cpu file?
> Maybe there is a better way to express what you have in mind.
> The cpu file is quite complex. But I think I found why it is not supported.

One operand (encoded in a 3-bit ifield) encode a reg file. There are 7
registers & 7 possibles values for this operand. For some insns/opcodes,
the 8th encoding is reserved to encode additional operands (exact
operand depends on another opcode).
Without derived operands, it leads to decode ambiguity. When defining a
derived operands with all operands, there are asm/syntax issues, and It
seems also decode issue (i looks like the "impossible" 8th value of the
reg file is not is correctly decoded and is considered as a valid index
for reg file).
So I defined a virtual hardware and an associated operand to describe
the right operand name for the 8th encoding, with the 7 regs. But this
leads to this semantic generation issue ...

I finally found a way to make asm, disassembly, sid decode and sid
semantic to work by creating one operand & virtual hardware per each
ifield encoding. It defines many insns, but there is no more ambiguity.

Thank you for your reply,
Cheers,
Aurélein