From mboxrd@z Thu Jan  1 00:00:00 1970
From: matthew green <mrg@cygnus.com>
To: "Frank Ch. Eigler" <fche@redhat.com>
Cc: cgen@sources.redhat.com
Subject: re: generalizing the delay rtx function 
Date: Wed, 14 Mar 2001 16:43:00 -0000
Message-id: <14960.984616975@cygnus.com>
References: <20010314080539.K32628@redhat.com>
X-SW-Source: 2001-q1/msg00160.html

   
   On Wed, Mar 14, 2001 at 06:40:05PM +1100, matthew green wrote:
   : [...]
   : is this possible?  eg, (sparc) if i do:
   :=20
   : 	ba	foo
   : 	 ld	[%l1 + 4], %o0
   : vs.
   : 	ba	foo
   : 	 tst	%o0
   :=20
   : the load can take *much* longer than the tst?
   
   I'm not sure I guess correctly at your point; is it that
   these two code sequences require a different number of
   clock cycles to run on a SPARC chip?  If so, yes, but
   the delay is not a programmer-visible one, so the=20
   proposed extensions to the delay rtx would not be used
   to model it.
   

you said the delay rtx would be changed to indicate the number
of "instruction cycles" before the effect is seen.  my example
above shows a case where this isn't going to be known.  if you
didn't mean "instruction cycles" but really "instructions" then
my point is meaningless.


.mrg.