branch-delay slot semantics questions

branch-delay slot semantics questions

[lehotsky]

I found cgen pretty easy to get up and running for the most part.
It's a definitely a handy (and powerful) tool.

But I don't seem to be able to get the instruction in the "delay" slot
to execute.  My branch instructions are all of the form

       (dni "jmp"
         ...
         (delay 1
		(set pc (....)))
         ...  
       )

But my machine seems to suppress the execution of the instruction
in the delay slot, although I don't have any annul code that I'm
aware of...  (when I run the simulator with -ton, the instructions
in the delay slots are never traced.

Anything I should be looking for?  Is there something special my
mloop.in code needs to do?

Is there also any support for dealing with the semantics that
"a branch in the delay-slot is always annulled".  I think I can
implement this by having two bits in the ISA's (setup-semantics (..))
code.  

    (define-isa
      ...
      (setup-semantics (sequence
			 ()
			 (set h-annul-jmp-p h-jump-insn-p)
			 (set h-jump-insn-p (attr BI insn DELAY-SLOT))))
    )

    ; Branch instructions in the shadow of a branch are annulled.  Remember
    ; if last executed instruction was a branch
    (dsh h-annul-jmp-p "remember if last instruction was jump" ()
							       (register BI))
    (dsh h-jump-insn-p "current instruction is a jmp/ret" () (register BI))




And then in every branch instruction, if the h-annul-jmp-p is set,
then we just evaluate the jump as (nop).

Re: branch-delay slot semantics questions

[Johan Rydberg]

lehotsky@earthlink.net wrote:

> Anything I should be looking for?  Is there something special my
> mloop.in code needs to do?

I asked the same question a week ago or so, here's my reply from
Frank:

: Anyone got any suggestions how I should implement the delay slot
: handling in the best way?

If you're planning to build a simulator for the gdb/sim collection,
see sim/fr30/mloop.in. 


You can follow the thread here:

  http://sources.redhat.com/ml/cgen/2001-q2/msg00035.html

regards,
johan

Re: branch-delay slot semantics questions

[Ben Elliston]

>>>>> "lehotsky" == lehotsky  <lehotsky@earthlink.net> writes:

  lehotsky> Is there also any support for dealing with the semantics that
  lehotsky> "a branch in the delay-slot is always annulled".  I think I can
  lehotsky> implement this by having two bits in the ISA's (setup-semantics (..))
  lehotsky> code.  

On some architectures, certain classes of instructions are forbidden
in the delay slot.  If this is what you really want, it's easiest to
detect this condition during instruction extraction ("fetching").
Again, see the fr30/mloop.in for an illustration.

Ben