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From: Ben Elliston <bje@redhat.com>
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Date: Tue, 03 Sep 2002 07:38:00 -0000
To: =?gb2312?B?5rEg578=?= <dam_wang@hotmail.com>
Cc: cgen@sources.redhat.com
Subject: Re: Question about cpu description
In-Reply-To: <F122OBN8xK2efVXGmZS0000b16c@hotmail.com>
References: <F122OBN8xK2efVXGmZS0000b16c@hotmail.com>
X-SW-Source: 2002-q3/txt/msg00043.txt.bz2

Hi.

>>>>> "dam" == dam wang <gb2312> writes:

  dam> How do CGEN know what the vitual cpu would do when one Ins was excuted. I 
  dam> mean, when I write the description file, nothing that describe the action 
  dam> of each Ins(at least I haven't found it till after I read the exited m32r 
  dam> description file.) is included.

The CPU description includes a semantics definition that describes
that the instruction does when it is executed.  For example, from the
M32R description:

	(dni addv3 "addv3"
	     ()
	     "addv3 $dr,$sr,$simm16"
	     (+ OP1_8 OP2_8 dr sr simm16)
	     (parallel ()
		       (set dr (add sr simm16))
		       (set condbit (add-oflag sr simm16 (const 0))))
	     ()
	)

So, `dr' is set to the sum of `sr' and `simm16' and the condbit is set
accordingly.  The instruction semantics are defined using a register
transfer language similar to GCC -- you can read more about it in the
CGEN manual.  There is an entire chapter dedicated to CGEN RTL.

Ben