From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1661 invoked by alias); 1 Feb 2002 00:57:38 -0000 Mailing-List: contact cgen-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sources.redhat.com Received: (qmail 1560 invoked from network); 1 Feb 2002 00:57:35 -0000 Received: from unknown (HELO tooth.toronto.redhat.com) (216.138.202.10) by sources.redhat.com with SMTP; 1 Feb 2002 00:57:35 -0000 Received: (from fche@localhost) by tooth.toronto.redhat.com (8.11.6/8.11.0) id g110vYZ04871; Thu, 31 Jan 2002 19:57:34 -0500 Date: Thu, 31 Jan 2002 16:57:00 -0000 From: "Frank Ch. Eigler" To: Andrew Cagney Cc: binutils@sources.redhat.com, cgen@sources.redhat.com Subject: Re: include/dis-asm.h patch for cgen disassemblers Message-ID: <20020131195734.D6166@redhat.com> References: <20020131124350.C19966@redhat.com> <15449.42904.232177.265525@casey.transmeta.com> <20020131162132.I19966@redhat.com> <3C59BD4A.9060900@cygnus.com> <20020131184230.A6166@redhat.com> <3C59DB61.3000106@cygnus.com> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-md5; protocol="application/pgp-signature"; boundary="T7mxYSe680VjQnyC" Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: <3C59DB61.3000106@cygnus.com>; from ac131313@cygnus.com on Thu, Jan 31, 2002 at 07:03:45PM -0500 X-SW-Source: 2002-q1/txt/msg00033.txt.bz2 --T7mxYSe680VjQnyC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Content-length: 1032 Hi - cagney wrote: > [...] > > isa ~=3D instruction set ~=3D group of machine instructions decodable; > > can be a function of cpu state >=20 > Er, ISA =3D=3D Instruction Set Architecture which to me is bfd_architectu= re.=20 > I think, here you're looking for something else. >=20 > For instance, Arm has thumb and MIPS has MIPS16. They are modes but=20 > sill part of a single ISA. Yes, but not in an interesting sense. It's much like the IA32 engine inside IA64: they surely aren't the same ISA, despite being executable by the same hardware, and operating partly on the same registers. Sure, arm & thumb are closer together, and they may be documented in the same publication, but that's not substantial to this question. The conceptual issue is whether or not the choice of instructions available is a function of processor state. For the purposes of tools like disassemblers and simulators, and really even assemblers and compilers, each such group forms a separate instruction set. - FChE --T7mxYSe680VjQnyC Content-Type: application/pgp-signature Content-Disposition: inline Content-length: 232 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.0.6 (GNU/Linux) Comment: For info see http://www.gnupg.org iD8DBQE8Wef+VZbdDOm/ZT0RAkvNAJ9TKhJ3lU3+sAHk1f1OjYxkqm1NuQCfZdGv xuo28jxTPMhqBn248VhQzNM= =VewJ -----END PGP SIGNATURE----- --T7mxYSe680VjQnyC--