From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 21983 invoked by alias); 20 Feb 2002 15:59:53 -0000 Mailing-List: contact cgen-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sources.redhat.com Received: (qmail 21865 invoked from network); 20 Feb 2002 15:59:50 -0000 Received: from unknown (HELO toenail.toronto.redhat.com) (216.138.202.10) by sources.redhat.com with SMTP; 20 Feb 2002 15:59:50 -0000 Received: (from fche@localhost) by toenail.toronto.redhat.com (8.11.6/8.11.6) id g1KFxlN26468; Wed, 20 Feb 2002 10:59:47 -0500 Date: Wed, 20 Feb 2002 07:59:00 -0000 From: "Frank Ch. Eigler" To: Alan Lehotsky Cc: cgen@sources.redhat.com Subject: Re: contemplating CGEN for VLIW architecture Message-ID: <20020220105947.C3652@redhat.com> References: Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-md5; protocol="application/pgp-signature"; boundary="/e2eDi0V/xtL+Mc8" Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: ; from apl@alum.mit.edu on Wed, Feb 20, 2002 at 09:44:45AM -0500 X-SW-Source: 2002-q1/txt/msg00054.txt.bz2 --/e2eDi0V/xtL+Mc8 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Content-length: 1106 Hi - On Wed, Feb 20, 2002 at 09:44:45AM -0500, Alan Lehotsky wrote: > I'm evaluating a possible port to a VLIW microsequencer (256 bit > microword, 25 fields per micro-instruction).=20=20 It may be best to model this as a list of independent subinstructions, one for each logical operation. Let each have its own cgen isa tag. (Let another layer take care of bitfield packing / unpacking.) Otherwise, you might have to ask cgen to expand the cartesian product of all possible opcode tuples, to come up with the total list of cgen-level instructions. (Let some other layer take care of bitwise packing / unpacking.) The 32-bit limit you mention relates to something a little different: the width of the bitmask used to identify a given single cgen instruction. In this case, if you break up the VLIW word into N subinstructions, the 32-bit limit may end up not affecting you. > I guess I'm also wondering if I can build an assembler that looks more > like an expression language, viz something like > REGA =3D REGB + REGC, if R7 > R8 jump FAIL, REGZ=3D0x100; > [...] Mucho worko, amigo. - FChE --/e2eDi0V/xtL+Mc8 Content-Type: application/pgp-signature Content-Disposition: inline Content-length: 232 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.0.6 (GNU/Linux) Comment: For info see http://www.gnupg.org iD8DBQE8c8fyVZbdDOm/ZT0RApX3AJ0b+VVpZ/dUTgnXfQr7P7FaXspXxgCfeMeb zqTJJ6Cbq2YjahsiRzGdTvs= =BKAs -----END PGP SIGNATURE----- --/e2eDi0V/xtL+Mc8--