From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29959 invoked by alias); 10 Dec 2002 08:38:18 -0000 Mailing-List: contact cgen-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sources.redhat.com Received: (qmail 29952 invoked from network); 10 Dec 2002 08:38:17 -0000 Received: from unknown (HELO neon-gw.transmeta.com) (63.209.4.196) by sources.redhat.com with SMTP; 10 Dec 2002 08:38:17 -0000 Received: (from root@localhost) by neon-gw.transmeta.com (8.9.3/8.9.3) id AAA28749; Tue, 10 Dec 2002 00:38:16 -0800 Received: from mailhost.transmeta.com(10.1.1.15) by neon-gw.transmeta.com via smap (V2.1) id xma028717; Tue, 10 Dec 02 00:38:10 -0800 Received: from xris-athlon.transmeta.com (xris-athlon.transmeta.com [10.10.25.96]) by deepthought.transmeta.com (8.11.6/8.11.6) with ESMTP id gBA8cAR15355; Tue, 10 Dec 2002 00:38:10 -0800 (PST) Received: (from dje@localhost) by xris-athlon.transmeta.com (8.9.3/8.7.3) id AAA12330; Tue, 10 Dec 2002 00:38:10 -0800 Date: Tue, 10 Dec 2002 00:38:00 -0000 Message-Id: <200212100838.AAA12330@xris-athlon.transmeta.com> From: Doug Evans To: bje@redhat.com cc: cgen@sources.redhat.com, hp@axis.com Subject: m32r port breakage X-SW-Source: 2002-q4/txt/msg00059.txt.bz2 Yes, it's been ages since I've looked at the m32r port, but it's the one I like to use when playing with things. Hans-Peter has a patch he wants to go in and before it has my blessing I want to play with it on a real port. This patch breaks the m32r simulator. 2001-04-02 Ben Elliston * sim-decode.scm (@prefix@_init_idesc_table): Compute tabsize using the size of the table and its elements. (-gen-decode-insn-globals): Define the idesc table's size to be the last instruction enum plus one, not @PREFIX@_INSN_MAX. * sim-model.scm (-gen-mach-defns): Define CPU_MAX_INSNS as the last instruction enum plus one, not @CPU@_INSN_MAX. Why was @PREFIX@_INSN_MAX replaced with "last instruction enum plus one"? For the m32r they're not the same thing. The former takes into account all the parallel semantic handlers causing this table in sim/m32r/decodex.c static IDESC m32rxf_insn_data[M32RXF_INSN_SNC + 1]; to be smaller than it should be so that m32rxf_init_idesc_table ends up clobbering memory beyond the table. void m32rxf_init_idesc_table (SIM_CPU *cpu) { IDESC *id,*tabend; const struct insn_sem *t,*tend; int tabsize = sizeof (m32rxf_insn_data) / sizeof (IDESC); IDESC *table = m32rxf_insn_data; memset (table, 0, tabsize * sizeof (IDESC)); /* First set all entries to the `invalid insn'. */ t = & m32rxf_insn_sem_invalid; for (id = table, tabend = table + tabsize; id < tabend; ++id) init_idesc (cpu, id, t); /* Now fill in the values for the chosen cpu. */ for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t); t != tend; ++t) { init_idesc (cpu, & table[t->index], t); if (t->par_index != NOPAR) { >>>> init_idesc (cpu, &table[t->par_index], t); >>>> table[t->index].par_idesc = &table[t->par_index]; } if (t->par_index != NOPAR) { >>>> init_idesc (cpu, &table[t->write_index], t); >>>> table[t->par_index].par_idesc = &table[t->write_index]; } } /* Link the IDESC table into the cpu. */ CPU_IDESC (cpu) = table; }