From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 30592 invoked by alias); 2 Dec 2005 03:42:52 -0000 Received: (qmail 30584 invoked by uid 22791); 2 Dec 2005 03:42:51 -0000 X-Spam-Check-By: sourceware.org Received: from miranda.se.axis.com (HELO miranda.se.axis.com) (193.13.178.8) by sourceware.org (qpsmtpd/0.31) with ESMTP; Fri, 02 Dec 2005 03:42:47 +0000 Received: from ignucius.se.axis.com (ignucius.se.axis.com [10.83.5.18]) by miranda.se.axis.com (8.12.9/8.12.9/Debian-5local0.1) with ESMTP id jB23gaWN015112; Fri, 2 Dec 2005 04:42:36 +0100 Received: from ignucius.se.axis.com (localhost [127.0.0.1]) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) with ESMTP id jB23gZmC025780; Fri, 2 Dec 2005 04:42:35 +0100 Received: (from hp@localhost) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) id jB23gZ03025776; Fri, 2 Dec 2005 04:42:35 +0100 Date: Fri, 02 Dec 2005 03:42:00 -0000 Message-Id: <200512020342.jB23gZ03025776@ignucius.se.axis.com> From: Hans-Peter Nilsson To: cgen@sourceware.org CC: brolley@redhat.com, jimb@redhat.com Subject: Unbreak CRIS sim: fix -gen-decode-insn-entry. And why the widened mem fetch? Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2005-q4/txt/msg00043.txt.bz2 Dave Brolley's changes broke the CRIS sim in at least two places: in CGEN (see further below) and by assuming that all sims also have CGEN disassemblers (film at 11). Tsk tsk. *Please* regen, cgen-maint-rebuild and test all CGEN simulators when hacking general changes into the CGEN sim machinery. It's not like there are too many... Anyway, I think I unbroke it (clean test-results), but I'm not sure this is the best change. I don't like these diffs in the generated sim (this one seemingly unrelated to the breakage, maybe it's due to Jim Blandy's change on 2005-05-16): Index: cpuv10.h @@ -684,9 +684,9 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MOVUCWR_CODE \ length = 4; \ - word_1 = GETIMEMUHI (current_cpu, pc + 2); \ + word_1 = GETIMEMUSI (current_cpu, pc + 2); \ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \ + f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ Why fetch more than needed? Can't that cause spurious invalid accesses at the end of defined memory? Doesn't it slow down the simulator? (Hm, I guess I can measure that...) I don't have the full context of all cases when this can happen, but for the case above, it's for moving a 16-bit constant field zero-extended into a 32-bit register. And this one: @@ -364,8 +364,14 @@ crisv10f_decode (SIM_CPU *current_cpu, I case 11 : /* fall through */ case 12 : /* fall through */ case 13 : /* fall through */ - case 15 : itype = CRISV10F_INSN_BCC_B; goto extract_sfmt_bcc_b; - case 14 : itype = CRISV10F_INSN_BA_B; goto extract_sfmt_ba_b; + case 15 : + if ((base_insn & 0xf00) == 0x0) + { itype = CRISV10F_INSN_BCC_B; goto extract_sfmt_bcc_b; } + itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + case 14 : + if ((base_insn & 0xff00) == 0xe000) + { itype = CRISV10F_INSN_BA_B; goto extract_sfmt_ba_b; } + itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } Aren't those tests redundant when base_insn == entire_insn (so to speak; there is no entire_insn as per the patch below)? Should I have conditionalized the whole generated if-test? The change below mimics the test in sim-decode.scm:-gen-decode-fn where entire_insn is conditionally declared as a parameter to @prefix@_decode. Without it, I get compilation errors for the undeclared entire_insn. Ok to commit? * utils-sim.scm (-gen-decode-insn-entry): Correct last change for non-(adata-integral-insn? CURRENT-ARCH) case. Index: utils-sim.scm =================================================================== RCS file: /cvs/src/src/cgen/utils-sim.scm,v retrieving revision 1.13 diff -p -u -r1.13 utils-sim.scm --- utils-sim.scm 18 May 2005 21:52:57 -0000 1.13 +++ utils-sim.scm 2 Dec 2005 03:33:15 -0000 @@ -636,7 +636,9 @@ ";\n") "") ; Generate code to check that all of the opcode bits for this insn match - indent " if ((entire_insn & 0x" (number->hex (insn-base-mask insn)) ") == 0x" (number->hex (insn-value insn)) ")\n" + indent " if ((" + (if (adata-integral-insn? CURRENT-ARCH) "entire_insn" "base_insn") + " & 0x" (number->hex (insn-base-mask insn)) ") == 0x" (number->hex (insn-value insn)) ")\n" indent " { itype = " (gen-cpu-insn-enum (current-cpu) insn) ";" (if (with-scache?) (if fn? brgds, H-P